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AgeCommit message (Expand)AuthorFilesLines
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo1-0/+1
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo1-0/+1
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-4/+5
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang1-1/+5
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+2
2023-12-15x86: last-insn recording should be per-subsectionJan Beulich2-0/+38
2023-12-15ELF: reliably invoke md_elf_section_change_hook()Jan Beulich1-11/+18
2023-12-15ELF: drop "push" parameter from obj_elf_change_section()Jan Beulich9-24/+34
2023-12-15x86: don't needlessly override .bssJan Beulich1-8/+5
2023-12-15x86: fold assembly dialect attributesJan Beulich2-5/+5
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich2-5/+8
2023-12-15Arm64: fix build for certain gcc versionsJan Beulich1-3/+3
2023-12-13Clean base_reg and assign correct values to regs for input_output_operand (%dx).Cui, Lili1-0/+2
2023-12-12Fix whitespace snafu in tc-riscv.cNick Clifton1-5/+5
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama2-0/+23
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia2-0/+111
2023-12-11RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fixNelson Chu1-1/+1
2023-12-01x86: adjust NOP generation after potential non-insnJan Beulich2-1/+13
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich1-12/+1
2023-12-01x86: suppress optimization after potential non-insnJan Beulich1-0/+5
2023-12-01x86: last-insn recording should be per-sectionJan Beulich2-58/+64
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+68
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi1-0/+3
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi1-2/+2
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen1-2/+4
2023-11-24x86: shrink opcode sets tableJan Beulich2-130/+130
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-6/+14
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-16/+5
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich1-3/+3
2023-11-23s390: Add missing extended mnemonicsJens Remus1-4/+8
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-0/+4
2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai1-1/+5
2023-11-21bpf: Fixed register parsing disambiguating with possible symbol.Cupertino Miranda1-0/+4
2023-11-18gas: bpf: do not allow referring to register names as symbols in operandsJose E. Marchesi1-48/+65
2023-11-17bpf: avoid creating wrong symbols while parsingDavid Faust2-0/+96
2023-11-17x86: improve a few diagnosticsJan Beulich1-9/+18
2023-11-17x86: don't allow pseudo-prefixes to be overridden by legacy suffixesJan Beulich1-3/+19
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich1-1/+10
2023-11-17x86: use IS_ELFJan Beulich2-7/+4
2023-11-17x86: conditionally hide object-format-specific functionsJan Beulich2-23/+31
2023-11-17x86: fold conditionals in check_long_reg()Jan Beulich1-13/+5
2023-11-17x86-64: extend expected-size check in check_qword_reg()Jan Beulich1-1/+2
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-0/+1
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang1-5/+5
2023-11-10Add support for ilp32 register alias.Lulu Cai1-23/+18
2023-11-09x86: rework UWRMSR operand swappingJan Beulich1-15/+8
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-30/+15
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-92/+81
2023-11-09x86: Cpu64 handling improvementsJan Beulich1-5/+13
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+1
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