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AgeCommit message (Expand)AuthorFilesLines
2021-10-28arm: add unwinder encoding support for PACBTITejas Belagod1-5/+57
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-288/+304
2021-10-25x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu1-3/+5
2021-10-24LoongArch gas supportliuzhensong6-0/+2029
2021-10-22x86: Add -muse-unaligned-vector-move to assemblerH.J. Lu1-0/+39
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+3
2021-09-30arm: enable Cortex-R52+ CPUPrzemyslaw Wirkus1-0/+3
2021-09-30aarch64: Enable Cortex-X2 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: Enable Cortex-A710 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: Enable Cortex-A510 CPUPrzemyslaw Wirkus1-0/+6
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+1
2021-09-22dwarf2 sub-section testAlan Modra1-2/+5
2021-09-17RISC-V: Merged extension string tables and their version tables into one.Nelson Chu1-119/+7
2021-09-13MIPS: don't use get_symbol_name() for section parsing. With s_change_section...Jan Beulich1-14/+7
2021-09-13ia64: don't use get_symbol_name() for section parsing. With cross_section() ...Jan Beulich1-12/+4
2021-09-06Fix potential use on an uninitialised vairable in the MCore assembler.Nick Clifton1-3/+6
2021-09-06Fix potential uninitialised variable in microblaze assembler code.Nick Clifton1-1/+1
2021-09-02Add support for the haiku operating system. These are the os support patches...Alexander von Gluck IV2-0/+31
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton1-21/+18
2021-08-31RISC-V: Extend .insn directive to support hardcode encoding.Nelson Chu1-3/+55
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu2-1/+224
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
2021-08-16x86: Don't pad .tfloat directive outputH.J. Lu2-15/+1
2021-08-16as: Replace the removed symbol with the versioned symbolH.J. Lu2-2/+31
2021-08-11Fix a typo in the RX asse,bler. The Double-precision floating-point exceptio...Darius Galis1-1/+1
2021-08-11Fix an internal error in the CSKY assembler when asked to resolve an overlarg...Nick Clifton1-1/+2
2021-08-11Add a -mno-dollar-line-separator command line option to the AVR assembler.Matt Jacobson2-3/+16
2021-08-11Fix typo in previous deltaNick Clifton1-2/+2
2021-08-11gas: fold IEEE encoding of -Inf with that of +InfJan Beulich1-42/+3
2021-08-11gas: support NaN flavorsJan Beulich2-17/+34
2021-08-11Arm64: leave .bfloat16 processing to common codeJan Beulich1-49/+1
2021-08-11Arm32: leave more .bfloat16 processing to common codeJan Beulich1-46/+3
2021-08-11x86: introduce .bfloat16 directiveJan Beulich2-5/+18
2021-08-11x86: introduce .hfloat directiveJan Beulich1-1/+2
2021-08-11x86/ELF: fix .ds.x outputJan Beulich1-0/+1
2021-08-11x86/ELF: fix .tfloat outputJan Beulich3-2/+29
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-3/+42
2021-08-04gas: correctly output XCOFF tbss symbols with XTY_CM type.Clément Chigot1-1/+2
2021-08-04gas: always add dummy symbols when creating XCOFF sections.Clément Chigot1-17/+11
2021-07-30gas: ensure XCOFF DWARF subsection are initialized to 0Clément Chigot1-1/+1
2021-07-29gas: improve C_BSTAT and C_STSYM symbols handling on XCOFFClément Chigot2-2/+7
2021-07-28x86: Simplify check for distinct TMM register operandsH.J. Lu1-15/+10
2021-07-28PowerPC: ignore sticky options for .machineAlan Modra1-4/+16
2021-07-26PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.Andrea Corallo1-0/+3
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+14
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+14
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