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AgeCommit message (Expand)AuthorFilesLines
2023-05-13PR28955 mips gas segfaultAlan Modra1-2/+4
2023-05-12x86: slightly simplify i386_parse_name()Jan Beulich1-7/+2
2023-05-12gas: equates of registersJan Beulich17-3/+29
2023-05-04RISC-V: tighten post-relocation-operator separator expectationJan Beulich1-1/+3
2023-05-04gas: fix building tc-bpf.c on s390xIlya Leoshkevich1-2/+4
2023-05-03Remove unused args from bfd_make_debug_symbolAlan Modra1-1/+1
2023-04-28x86/Intel: reduce ELF/PE conditional scope in x86_cons()Jan Beulich1-6/+4
2023-04-26gas: support for the BPF pseudo-c assembly syntaxGuillermo E. Martinez2-4/+1519
2023-04-25RISC-V: adjust logic to avoid register name symbolsJan Beulich2-27/+98
2023-04-25RISC-V: don't recognize bogus relocationsJan Beulich1-2/+1
2023-04-25RISC-V: avoid redundant and misleading/wrong error messagesJan Beulich1-0/+9
2023-04-25RISC-V: drop "percent_op" parameter from my_getOpcodeExpression()Jan Beulich1-4/+4
2023-04-25RISC-V: minor effort reduction in relocation specifier parsingJan Beulich1-16/+16
2023-04-23MIPS: fix loongson3 llsc workaroundYunQiang Su1-7/+3
2023-04-19x86: parse_register() must not alter the parsed stringJan Beulich1-13/+9
2023-04-19x86: parse_real_register() does not alter the parsed stringJan Beulich1-4/+4
2023-04-18Symbols with GOT relocatios do not fix adjustbalemengqinggang1-0/+15
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-0/+1
2023-04-03ubsan: aarch64 parse_vector_reg_listAlan Modra1-4/+4
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-17/+47
2023-03-31x86: handle immediate operands for .insnJan Beulich2-3/+108
2023-03-31x86: allow for multiple immediates in output_disp()Jan Beulich1-5/+5
2023-03-31x86: handle EVEX Disp8 for .insnJan Beulich1-1/+97
2023-03-31x86: process instruction operands for .insnJan Beulich2-21/+302
2023-03-31x86: parse special opcode modifiers for .insnJan Beulich1-1/+38
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich1-6/+238
2023-03-31x86: introduce .insn directiveJan Beulich1-10/+155
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+5
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-3/+14
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-1/+2
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-9/+64
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-14/+71
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+11
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+8
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-3/+32
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-0/+23
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-1/+32
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-1/+1
2023-03-30aarch64: Add +sme2Richard Sandiford1-0/+2
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford1-5/+7
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-20/+38
2023-03-30aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford1-71/+71
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-2/+1
2023-03-30aarch64: Tweak priorities of parsing-related errorsRichard Sandiford1-5/+45
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-0/+4
2023-03-30aarch64: Tweak register list errorsRichard Sandiford1-4/+2
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