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AgeCommit message (Expand)AuthorFilesLines
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton1-0/+24
2020-09-30x86: Check register operand for AddrPrefixOpRegH.J. Lu1-0/+13
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus1-0/+14
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan1-0/+10
2020-09-30gcc-4.4.7 warning fixesAlan Modra1-2/+2
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus1-0/+3
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus1-0/+3
2020-09-28arm: Add missing Neoverse V1 featureAlex Coplan1-1/+3
2020-09-28aarch64: Neoverse V1 tweaksAlex Coplan1-8/+9
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra1-5/+3
2020-09-24RISC-V: Error for relaxable branch in absolute section.Jim Wilson1-0/+7
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan1-0/+3
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan1-0/+8
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan1-0/+5
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+3
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu1-379/+262
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-1/+9
2020-09-21PR26569, R_RISCV_RVC_JUMP results in buffer overflowAlan Modra1-3/+7
2020-09-16Tidy elf_symbol_fromAlan Modra5-11/+8
2020-09-15PR26610, ARM's "VFPv3 vldr to vmov" gas testcase failAlan Modra1-19/+20
2020-09-15Fix the assembler's new .nop directive so that the input line pointer is pres...Nick Clifton1-6/+3
2020-09-15Change the /nop directive for the BPF port of the assembler to use the encodi...David Faust1-1/+3
2020-09-14Fix support for theassembler's new ".nop" directive on the IA64 target.Nick Clifton1-0/+2
2020-09-14Add a new ".nop" directive to the assembler to allow the creation of no-op in...Nick Clifton4-3/+11
2020-09-14CSKY: Set feature flags for default cpu.Cooper Qu1-3/+2
2020-09-10CSKY: Enable extend lrw by default for CK802, CK803 and CK860.Cooper Qu1-1/+4
2020-09-10CSKY: Add new arches while refine the cpu option process.Cooper Qu1-172/+435
2020-09-09power10 on ppc32Alan Modra1-1/+2
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu1-2/+2
2020-09-09CSKY: Support option -mfloat-abi.Cooper Qu1-0/+57
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu1-31/+189
2020-09-08MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz1-1/+53
2020-09-08aarch64: Add -mcpu option for Cortex-R82Alex Coplan1-0/+1
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-4/+5
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+1
2020-09-02ubsan: tc-z80.c:3656 shift exponent 32 is too largeAlan Modra1-1/+1
2020-09-02ubsan: tc-sparc.c:1146 left shift cannot be representedAlan Modra1-1/+1
2020-09-02ubsan: tc-nios2.c:1403 shift exponent 32 is too largeAlan Modra1-1/+1
2020-09-02ubsan: tc-mips.c:9606 shift exponent 32 is too largeAlan Modra1-2/+5
2020-09-02ubsan: tc-d30v.c left shift cannot be representedAlan Modra1-2/+2
2020-09-02ubsan: rx-parse.y:1743 shift exponent 32 is too largeAlan Modra1-24/+24
2020-09-02ubsan: obj-macho.c:503 left shift cannot be representedAlan Modra1-1/+1
2020-09-02ubsan: bfin-lex.l:503 left shift cannot be representedAlan Modra1-1/+1
2020-09-0232-bit host pdp11 breakageAlan Modra1-0/+2
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu1-17/+21
2020-09-02CSKY: Refine literals pool dump process and float register parser.Cooper Qu1-3/+51
2020-09-01PR26420, PR26421, PR26425, PR26427 UBSAN: tc-arm.c left shiftsAlan Modra1-78/+78
2020-08-31PR26510 UBSAN: tc-z8k.c left shift of negative valueAlan Modra1-8/+8
2020-08-31PR26503 UBSAN: tc-v850.c:1447 left shift cannot be representedAlan Modra1-1/+1
2020-08-31PR26502 UBSAN: tc-tic6x.c left shift of negative valueAlan Modra1-21/+21
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