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2024-02-15PR30308, infinite recursion in i386_intel_simplifyAlan Modra1-9/+13
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov1-0/+1
2024-02-09PowerPC: Add support for Power11 optionsPeter Bergner1-0/+2
2024-02-09x86: change type of Dwarf2 register numbers in register tableJan Beulich1-8/+6
2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu1-22/+80
2024-02-06gas: x86: ginsn: handle sub-QWORD ALU with imm and MOV ops correctlyIndu Bhagat1-0/+23
2024-02-06x86: Warn .insn instruction with length > 15 bytesH.J. Lu1-2/+8
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao1-0/+3
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu1-2/+2
2024-02-02x86: move Q-suffix-to-REX.W translation logicJan Beulich1-17/+20
2024-02-02x86: actually implement .nooptJan Beulich1-1/+14
2024-02-01gas: x86: ginsn: adjust ginsns for certain lea opsIndu Bhagat1-65/+57
2024-01-26x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix"Jan Beulich1-8/+15
2024-01-26x86/APX: optimize MOVBEJan Beulich1-4/+11
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang1-2/+5
2024-01-24LoongArch: gas: Start a new frag after instructions that can be relaxedmengqinggang1-5/+14
2024-01-24LoongArch: gas: Don't define LoongArch .alignmengqinggang1-13/+0
2024-01-21LoongArch: Do not emit R_LARCH_RELAX for two register macrosmengqinggang1-11/+34
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich1-2/+4
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-3/+3
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+65
2024-01-15aarch64: rcpc3: Add +rcpc3 architectural feature support flagVictor Do Nascimento1-0/+1
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti1-7/+11
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-3/+2
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-0/+3
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-0/+2
2024-01-15aarch64: Add support for FEAT_SVE2p1.Srinath Parvathaneni1-0/+1
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+18
2024-01-15aarch64: Add support for FEAT_B16B16 instructions.Srinath Parvathaneni1-0/+1
2024-01-15gas: x86: synthesize CFI for hand-written asmIndu Bhagat3-0/+1152
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+1
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +flagm2 flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +frintts flag for existing instructionsAndrew Carlotti1-0/+1
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-0/+1
2024-01-12aarch64: Fix option parsing to disallow prefixes of valid optionsAndrew Carlotti1-1/+3
2024-01-12aarch64: Add +fcma alias for +compnumAndrew Carlotti1-0/+2
2024-01-12aarch64: Fix +lse feature flag dependencyAndrew Carlotti1-1/+1
2024-01-12x86: Fix indentation and use true/false instead of 1/0Cui, Lili1-14/+14
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-0/+24
2024-01-09x86: FMA insns aren't eligible to VEX2 encodingJan Beulich1-0/+2
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-4/+9
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+1
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+17
2024-01-09aarch64: Add support for optional operand pairsVictor Do Nascimento1-2/+17
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento1-0/+1
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+2
2024-01-08arm: Add support for Armv8.9-A and Armv9.4-Asrinath1-0/+6
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