aboutsummaryrefslogtreecommitdiff
path: root/gas/config
AgeCommit message (Collapse)AuthorFilesLines
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline ↵Barnaby Wilks1-5/+0
specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size. The instructions that this change apply to are: VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf Fixed this by removing the check for this warning from GAS as well as opcodes. Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size and the same source and destination operand. Also fixed tests that would previously check for this warning. gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE. * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmladh.d: New tests. * testsuite/gas/arm/mve-vqdmladh.s: New tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh.d: New tests. * testsuite/gas/arm/mve-vqdmlsdh.s: New tests. opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi1-1/+43
Tested in a x86_64 host. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c. (pe_lcomm): Likewise. (md_pseudo_table): Use pe_lcomm to implement .lcomm.
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-5/+39
This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-18gas: .lcomm gets an alignment argument in eBPFJose E. Marchesi1-1/+2
gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Make .lcomm to get a third argument with the alignment.
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+3
This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
2019-07-17x86: replace "anymem" checks where possibleJan Beulich1-8/+14
Once operand parsing has completed, the simpler check of Operand_Mem can be used in places where i.types[] got passed to operand_type_check(). Note that this has shown a couple of omissions of adjusting i.flags[] when playing with i.op[] / i.types[] / i.tm.operand_types[]. Not all of them get added here, just all of the ones needed in process_operands().
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-12/+18
... instead of an operand type bit: It's an insn property, not an operand one. There's just one actual change to be made to the templates: Most are now required to have the (unswapped) destination go into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this regard, as otherwise generated code would differ from what we've been producing so far (which I don't think is wanted). Take the opportunity and add a missing IgnoreSize to pextrb (leading to an error in 16-bit mode), and take the liberty to once again drop stray IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16x86: fold SReg{2,3}Jan Beulich2-23/+22
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-09Re: gas/ELF: don't accumulate .type settingsAlan Modra3-29/+23
git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets, and added a new test that failed for aarch64, nds32, and rl78. The mips failures are due to BSF_OBJECT being set in many cases for symbols by the mips .global/.globl directive. This patch removes that code and instead sets BSF_OBJECT in a target frob_symbol function, also moving the mips hacks in elf_frob_symbol to the new function. Note that common symbols are handled fine in elf.c:swap_out_syms without needing to set BSF_OBJECT, so that old code can disappear. * config/obj-elf.c (elf_frob_symbol): Remove mips hacks. * config/tc-mips.h (tc_frob_symbol): Define. (mips_frob_symbol): Declare. * config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix. (mips_frob_symbol): Fudge symbols for irix here. * testsuite/gas/elf/type-2.e: Allow random target symbols.
2019-07-04x86: correct "-Q" option handlingJan Beulich1-1/+3
For another patch I wanted to use a sufficiently benign option (simply to be able to specify one, which certain test case invocations require), and I stumbled across -Q in the --help output. Before realizing that this is x86-specific anyway, I've tried and and ran into a mysterious testsuite failure, until I further realized that other than the help text suggests the option requires an argument. Correct the help text, and make the implementation actually match what the comment there has been describing (and what the help text now says).
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich2-1/+40
Recently a patch was submitted for a Xen Project test harness binary to override the compiler specified @object to @func (see [1]). In a reply I suggested we shouldn't make ourselves dependent on currently unspecified behavior of gas here: It accumulates all requests, and then bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes certain flags over others. Make the behavior predictable: Generally the last .type is what counts. Exceptions are directives which set multiple bits (TLS, IFUNC, and UNIQUE): Subsequent directives requesting just the more generic bit (i.e. FUNC following IFUNC) won't clear the more specific one. Warn about incompatible changes, except from/to STT_NOTYPE. Also add a new target hook, which hppa wants to use right away afaict. In the course of adding the warning I ran into two ld testsuite failures. I can only assume that it was a copy-and-paste mistake that lead to the same symbol having its type set twice. [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect ↵Barnaby Wilks1-0/+9
structural load/store by element instruction would generate the wrong error message. For example, when provided with the (incorrect) instruction st4 {v0.16b-v3.16b}[4],[x0] currently assembler provides the following error message "Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'". This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving [4],[x0] as what it believed to be the second operand. The actual error is that the first operand should be of element type and not vector type (as provided). The new diagnostic for this error is "Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'. Added testcases to check for the correct diagnostic message as well as checking that variations of the structural load/store by element instruction also generate the error when they have the same problem. * config/tc-aarch64.c (parse_operands): Add error check. * testsuite/gas/aarch64/diagnostic.l: New test. * testsuite/gas/aarch64/diagnostic.s: New test. * testsuite/gas/aarch64/illegal.l: New tests. * testsuite/gas/aarch64/illegal.s: New tests.
2019-07-01x86: drop Vec_Imm4Jan Beulich1-25/+11
It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01x86: limit ImmExt abuseJan Beulich1-13/+10
In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+23
It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+43
When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01x86: StaticRounding implies SAEJan Beulich1-6/+3
This implication allows to simplify some conditionals, thus slightly improving performance. This change also paves the way for re-using StaticRounding for non-EVEX insns.
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-11/+19
As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-07-01x86: use encoding_length() also elsewhereJan Beulich1-32/+4
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich1-0/+32
Such insns will cause #UD when an attempt to execute them is made. See also http://www.sandpile.org/x86/opc_enc.htm.
2019-06-27This fixes a bug in the ARm assembler where an immediate operand larger than ↵Barnaby Wilk s1-4/+9
4 bits (0xF) could be passed to the SMC (Secure Monitor Call) instruction. For example, this code is invalid: smc #0x6951 The code would previously check for and encode for up to 16 bit immediate values, however this immediate should instead be only a 4 bit value (as documented herehttps://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf ). Fixed this by adding range checks in the relevant areas and also removing code that would encode more than the first 4 bits of the immediate (code that is now redundant, as any immediate operand larger than 0xF would error now anyway). gas * config/tc-arm.c (do_smc): Add range check for immediate operand. (do_t_smc): Add range check for immediate operand. Remove obsolete immediate encoding. (md_apply_fix): Fix range check. Remove obsolete immediate encoding. * testsuite/gas/arm/arch6zk.d: Fix test. * testsuite/gas/arm/arch6zk.s: Fix test. * testsuite/gas/arm/smc-bad.d: New test. * testsuite/gas/arm/smc-bad.l: New test. * testsuite/gas/arm/smc-bad.s: New test. * testsuite/gas/arm/thumb32.d: Fix test. * testsuite/gas/arm/thumb32.s: Fix test.
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-2/+2
These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
2019-06-25MIPS/gas: Fix order of instructions in LI macro expansionFaraz Shahbazker1-11/+29
When MTHC1 instruction is paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be executed first, because the semantic definition of MTC1 is not aware that software will be using an MTHC1 to complete the operation, and sets the upper half of the 64-bit FPR to an UNPREDICTABLE value[1]. Fix the order of MTHC1 and MTC1 instructions in LI macro expansion. Modify the expansions to exploit moves from $zero directly by-passing the use of $AT, where ever possible. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Wave Computing, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 217. gas/ * config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with respect to MTC1 and use $0 for either part where possible. * testsuite/gas/mips/li-d.s: Add test cases for non-zero words in double precision constants. * testsuite/gas/mips/li-d.d: Update reference output. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. * testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
2019-06-25x86: correct / adjust debug printingJan Beulich1-9/+10
For quite some time we've been using combinations of bits for specifying various registers in operands and templates. I think it was Alan who had indicated that likely the debug printing would need adjustment as a result. Here we go. Accumulator handling for GPRs gets changed to match that for FPU regs. For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their original uses replaced by direct checks of the two bits of interest, which is cheaper than operand_type_equal() invocations. For SIMD registers nothing similar appears to be needed, as respective operands get stripped from the (copy of the) template before pt() is reached. The type change on pi() is to silence a compiler diagnostic. Arguably its other parameter could also be const-qualified.
2019-06-25x86: don't open code is_any_vex_encoding()Jan Beulich1-3/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+5
The same reasoning applies here as did/does for immediates fitting in 31 bits.
2019-06-25Fix logical expression in last commitAlan Modra1-1/+1
* config/tc-ppc.c (ppc_handle_align): Add parentheses.
2019-06-25PowerPC nopsAlan Modra2-19/+54
This patch corrects ppc rs_align_code handling to choose the alignment nops based on the machine in force at the alignment directive rather than the machine at the end of file. * config/tc-ppc.h (ppc_nop_select): Declare. (NOP_OPCODE): Define. * config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu. (ppc_nop_encoding_for_rs_align_code): New enum. (ppc_nop_select): New function. (ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag. * testsuite/gas/ppc/groupnop.d, * testsuite/gas/ppc/groupnop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu1-0/+3
2019-06-06 Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .enqcmd. (cpu_noarch): Add noenqcmd. * doc/c-i386.texi: Document noenqcmd.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+3
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-05-30RISC-V: Fix lui argument parsing.Jim Wilson1-5/+4
This fixes a bug reported on the riscv.org sw-dev mailing list. This rejects "lui x1,symbol", as a symbol should only be accepted here when used inside %hi(). Without the fix, this gets assembled as "lui x1,0" with no relocation which is clearly wrong. gas/ * config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if statement. Delete O_symbol and O_constant check after if statement. * testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi. * testsuite/gas/riscv/auipc-parsing.l: Update.
2019-05-27Fix failure on powerpc 32-bit only targetsAlan Modra1-50/+120
Targets that lack ppc64 support were failing the new prefix-reloc test. This patch adds some test infrastructure to deal with that, and changes the powerpc gas usage info so that "-a64" is omitted when unsupported. I've been meaning to break up the usage message for a long time; While doing so causes translators some work now, it should make it easier next time a new powerpc option is added. * config/tc-ppc.c (is_ppc64_target): New function. (md_show_usage): Split up usage message. Don't show -a64 when unsupported. testsuite/gas/ppc/ppc.exp (supports_ppc64): New. (prefix-reloc): Only run for ppc64.
2019-05-24aarch64: override default elf .set handling in gasSzabolcs Nagy2-0/+38
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias symbols independently. This is needed for ifunc symbols which are aliased to the resolver using .set and don't expect resolver attributes to override the ifunc symbol attributes. This means .variant_pcs must be added explicitly to aliases. gas/ChangeLog: * config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define. * config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare. (OBJ_COPY_SYMBOL_ATTRIBUTES): Define. * testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
2019-05-24aarch64: handle .variant_pcs directive in gasSzabolcs Nagy1-0/+23
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS. gas/ChangeLog: * config/tc-aarch64.c (s_variant_pcs): New function. * doc/c-aarch64.texi: Document .variant_pcs. * testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
2019-05-24PowerPC relocations for prefix insnsAlan Modra2-23/+149
include/ * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), (R_PPC64_D28, R_PPC64_PCREL28): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO), (BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30), (BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34), (BFD_RELOC_PPC64_PLT_PCREL34), (BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34), (BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34), (BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34), (BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34), (BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums. * elf64-ppc.c (PNOP): Define. (ppc64_elf_howto_raw): Add reloc howtos for new relocations. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers. (ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34 relocs. (ppc64_elf_prefix_reloc): New function. (struct ppc_link_hash_table): Add notoc_plt. (is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC. (is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle possible need for dynamic relocs on non-pcrel powerxx relocs. (dec_dynrel_count): Handle non-pcrel powerxx relocs. (ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_relocate_section): Handle new powerxx relocs. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel, @plt@pcrel, @higher34, @highera34, @highest34, and @highesta34. (fixup_size): Handle new powerxx relocs. (md_assemble): Warn for @pcrel on non-prefix insns. Accept @l, @h and @ha on prefix insns, and infer reloc without any @ suffix. Translate powerxx relocs to suit DQ and DS field instructions. Include operand tests as well as opcode test to translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA. (ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs. (md_apply_fix): Handle new powerxx relocs. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34, BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34, BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28. * testsuite/gas/ppc/prefix-reloc.d, * testsuite/gas/ppc/prefix-reloc.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24PowerPC D-form prefixed loads and storesPeter Bergner1-1/+4
opcodes/ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, XTOP>): Define and add entries. (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. gas/ * config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that are 32-bits or smaller. * messages.c (as_internal_value_out_of_range): Do not truncate variables and use BFD_VMA_FMT to print them. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner2-40/+177
This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2019-05-23gas: add support for eBPFJose E. Marchesi2-0/+405
This patch adds a port for the Linux kernel eBPF to the GNU assembler. A testsuite and documentation updates are included. gas/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac: Handle bpf-*-* targets. * configure.tgt (generic_target): Likewise. * configure: Regenerate. * Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c. (TARGET_CPU_HFILES): Add tc-bpf.h. * Makefile.in: Regenerated. * config/tc-bpf.c: New file. * config/tc-bpf.h: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-bpf.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: set BPF. * doc/as.texi: Add eBPF contents. * doc/c-bpf.texi: New file. * testsuite/gas/bpf/alu.d: New file. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.s: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump.s: Likewise. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/exit-be.d: Likewise. * testsuite/gas/bpf/exit.s: Likewise. * testsuite/gas/bpf/exit.d: Likewise. * testsuite/gas/bpf/call-be.d: Likewise. * testsuite/gas/bpf/call.s: Likewise. * testsuite/gas/bpf/call.d: Likewise. * testsuite/gas/bpf/bpf.exp: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic.s: Likewise. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu.s: Likewise. * testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF. * testsuite/gas/all/org-1.s: Support nop_type 6. * testsuite/gas/all/org-1.l: Updated to reflect changes in org-1.s.
2019-05-22S12Z: GAS: New option --mdollar-hex.John Darrington1-8/+59
This option (also implied by --traditional) causes '$' to introduce literal hexadecimal constants, rather than the modern convention '0x'. gas/ * config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update. (md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args): (<global>): Use s12z_strtol instead of strtol. * doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex. * testsuite/gas/s12z/dollar-hex.d: New file. * testsuite/gas/s12z/dollar-hex.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-21[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructionsSudakshina Das1-11/+95
This patch makes changes to the <spec_reg> operand for VMRS and VMSR instructions as per the Armv8.1-M Mainline. New <spec_reg> options to support are: 0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags. 0b1100: VPR, privileged only access to the VPR register. 0b1101: P0, access to VPR.P0 predicate fields 0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating point context. 0b1111: FPCXT_S, enables saving and restoring of Secure floating point context *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (parse_operands): Update case OP_RVC to parse p0 and P0. (do_vmrs): Add checks for valid operands with respect to cpu and fpu options. (do_vmsr): Likewise. (reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS and FPCXT_S. * testsuite/gas/arm/armv8_1-m-spec-reg.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg.s: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New. * testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values. * testsuite/gas/arm/vfp1xD_t2.d: Likewise. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (coprocessor_opcodes): New instructions for VMRS and VMSR with the new operands.
2019-05-21[binutils, Arm] Add support for conditional instructions in Armv8.1-M MainlineSudakshina Das1-1/+81
This patch adds the following instructions which are part of the Armv8.1-M Mainline: CINC CINV CNEG CSINC CSINV CSNEG CSET CSETM CSEL gas/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (TOGGLE_BIT): New. (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm and csel. (operand_parse_code): New OP_RR_ZR. (parse_operand): Handle case for OP_RR_ZR. (do_t_cond): New. (insns): New instructions for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm, csel. * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. * testsuite/gas/arm/armv8_1-m-cond.d: New test. * testsuite/gas/arm/armv8_1-m-cond.s: New test. opcodes/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (enum mve_instructions): New enum for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv and cneg. (mve_opcodes): New instructions as above. (is_mve_encoding_conflict): Add cases for csinc, csinv, csneg and csel. (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
2019-05-21[binutils, Arm] Add support for shift instructions in MVESudakshina Das1-0/+50
This patch adds the following instructions which are part of Armv8.1-M MVE: ASRL (imm) ASRL (reg) LSLL (imm) LSLL (reg) LSRL SQRSHRL SRQSHR SQSHLL SQSHL SRSHRL SRSHR UQRSHLL UQRSHL UQSHLL UQSHL URSHLL URSHL *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. (insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. * testsuite/gas/arm/mve-shift.d: New. * testsuite/gas/arm/mve-shift.s: New. * testsuite/gas/arm/mve-shift-bad.d: New. * testsuite/gas/arm/mve-shift-bad.s: New. * testsuite/gas/arm/mve-shift-bad.l: New. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (emun mve_instructions): Updated for new instructions. (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. (is_mve_okay_in_it): Add new instructions to TRUE list. (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. (print_insn_mve): Updated to accept new %j, %<bitfield>m and %<bitfield>n patterns.
2019-05-21[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M BaselineAndre Vieira1-0/+5
gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 24559 * config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW replacement. * testsuite/gas/arm/load-pseudo.s: New test input. * testsuite/gas/arm/m0-load-pseudo.d: New test. * testsuite/gas/arm/m23-load-pseudo.d: New test. * testsuite/gas/arm/m33-load-pseudo.d: New test.
2019-05-21GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value.John Darrington6-3/+6
In an upcoming commit, I need to be able to set the prefix used to introduce hexadecimal literal constants using a command line flag. This is not currently possible, because the switch which determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at build time. This change substitutes it for a variable to be set at start up. gas/ChangeLog: * expr.c (literal_prefix_dollar_hex): New variable. (operand)[case '$']: Use the new variable instead of the old macro. Also, move this instance of "case '$'" next to the other one, and enable it only in the complementary proprocessor case. * expr.h (literal_prefix_dollar_hex): Declare it. * config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex. * config/tc-ip2k.c: ditto * config/tc-mt.c: ditto * config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition. * config/tc-ip2k.h: ditto * config/tc-mt.h: ditto
2019-05-21Revert "GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value."John Darrington6-6/+3
This reverts commit cffc205c9eaacfa312323807cd60b9d3d1c26894.
2019-05-20[MIPS] PR gas/14798: Limit IRIX5 specific default typing to IRIX targetsFaraz Shahbazker1-0/+4
On IRIX 5, every global symbol that is not explicitly labelled as being a function is assumed to be an object. There is no reason why IRIX behaviour should extend to all MIPS targets, so limit this to only IRIX targets. gas/ PR 14798 * config/tc-mips.c (s_mips_globl): Only treat symbols that are not explicitly labelled as BSF_OBJECTs for IRIX targets. * testsuite/gas/mips/pr14798.s: New test source. * testsuite/gas/mips/pr14798-irix.d: New test. * testsuite/gas/mips/pr14798.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ PR 14798 * testsuite/binutils-all/readelf.ss-mips: Update reference output. * testsuite/binutils-all/readelf.ss-tmips: Likewise. ld/ PR 14798 * testsuite/ld-mips-elf/reloc-6a.s: Specify .text section for global code symbols. * testsuite/ld-mips-elf/reloc-6b.s: Likewise.
2019-05-20GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value.John Darrington6-3/+6
In an upcoming commit, I need to be able to set the prefix used to introduce hexadecimal literal constants using a command line flag. This is not currently possible, because the switch which determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at build time. This change substitutes it for a variable to be set at start up. gas/ChangeLog: * expr.c (literal_prefix_dollar_hex): New variable. (operand)[case '$']: Use the new variable instead of the old macro. * expr.h (literal_prefix_dollar_hex): Declare it. * config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex. * config/tc-ip2k.c: ditto * config/tc-mt.c: ditto * config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition. * config/tc-ip2k.h: ditto * config/tc-mt.h: ditto
2019-05-16[PATCH, GAS, Arm] Refactor check_simd_pred_availabilityAndre Vieira1-50/+61
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (check_simd_pred_availability): Refactor. (do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability. (do_neon_dyadic_i64_su): Likewise. (do_neon_shl): Likewise. (do_neon_qshl): Likewise. (do_neon_rshl): Likewise. (do_neon_logic): Likewise. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_fmac): Likewise. (do_neon_mul): Likewise. (do_neon_qdmulh): Likewise. (do_neon_qrdmlah): Likewise. (do_neon_abs_neg): Likewise. (do_neon_sli): Likewise. (do_neon_sri): Likewise. (do_neon_qshlu_imm): Likewise. (do_neon_cvt_1): Likewise. (do_neon_cvttb_1): Likewise. (do_neon_mvn): Likewise. (do_neon_rev): Likewise. (do_neon_dup): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_sat_abs_neg): Likewise. (do_neon_cls): Likewise. (do_neon_clz): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_vcmla): Likewise. (do_vcadd): Likewise.
2019-05-16[PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp ↵Andre Vieira1-34/+74
and lctp gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): Add new instructions. (do_t_loloop): Changed to handle tail predication variants. (md_apply_fix): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-tailpredloop-bad.d: New test. * testsuite/gas/arm/mve-tailpredloop-bad.l: New test. * testsuite/gas/arm/mve-tailpredloop-bad.s: New test. * testsuite/gas/arm/mve-tailpredloop.d: New test.
generated by cgit v1.1 at 2024-11-22 19:53:59 +0000