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AgeCommit message (Expand)AuthorFilesLines
2024-06-10aarch64: warn on unpredictable results for new rcpc3 instructionsMatthieu Longo1-1/+39
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-1/+5
2024-06-05arm: remove FPA instructions from assemblerRichard Earnshaw1-699/+0
2024-06-05arm: remove options to select the FPARichard Earnshaw1-15/+1
2024-06-05arm: change default FPUs from FPA to noneRichard Earnshaw1-62/+63
2024-06-05arm: redirect fp constant data directives through a wrapperRichard Earnshaw1-5/+20
2024-06-05arm: adjust FPU selection logicRichard Earnshaw1-9/+2
2024-06-05arm: default to softvfp on armv6 or later coresRichard Earnshaw1-17/+17
2024-06-05arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFPRichard Earnshaw5-58/+96
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-1/+11
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang2-1/+65
2024-05-31x86: reduce check_{byte,word,long,qword}_reg() overheadJan Beulich1-4/+15
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-0/+13
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich1-2/+5
2024-05-29PR31796, Internal error in write_function_pdata at obj-coff-sehAlan Modra1-2/+22
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com1-0/+3
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com1-0/+67
2024-05-28Fix: internal error in write_function_pdata at obj-coff-sehNick Clifton1-0/+5
2024-05-24x86: simplify VexVVVV_SRC2 handling for the XOP caseJan Beulich1-9/+5
2024-05-24x86: simplify / consolidate check_{word,long,qword}_reg()Jan Beulich1-16/+4
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-5/+47
2024-05-22Support APX zero-upperCui, Lili1-2/+3
2024-05-22X86: Remove "i.rex" to eliminate extra conditional branchCui, Lili1-1/+1
2024-05-22Add check for 8-bit old registers in EVEX formatCui, Lili1-3/+4
2024-05-22x86: Split REX/REX2 old registers judgment.Cui, Lili1-16/+14
2024-05-21gas: drop remnants of ia64-*-aix*Jan Beulich1-23/+0
2024-05-20RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to...Sung-hun Kim1-1/+1
2024-05-17LoongArch: gas: Adjust DWARF CIE alignment factorsmengqinggang1-5/+9
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+1
2024-05-16arm: remove incorrect handling of FP bignums in move_or_literal_poolRichard Earnshaw1-6/+24
2024-05-15aarch64: Add sysreg features to +d128 dependenciesAndrew Carlotti1-2/+5
2024-05-15aarch64: Add simd dependency to +sha2Andrew Carlotti1-1/+1
2024-05-14arm: remove Maverick support from the assembler.Richard Earnshaw1-179/+4
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-6/+3
2024-05-06x86: Drop SwapSourcesCui, Lili1-8/+11
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-15/+17
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-2/+7
2024-04-25bpf: fix calculation when deciding to relax branchDavid Faust1-4/+33
2024-04-25LoongArch: gas: Simplify relocations in sections without code flagJinyang He1-3/+1
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas1-2/+2
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili1-1/+4
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang1-20/+50
2024-04-16x86: Fix a memory leak in md_assembleH.J. Lu1-5/+8
2024-04-10x86-64: Use long NOPs for Intel Core processorsH.J. Lu1-5/+35
2024-04-09arm: Fix encoding of MVE vqshr[u]nAlex Coplan1-4/+4
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei1-0/+181
2024-04-07Support APX NFCui, Lili1-4/+31
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-7/+0
2024-04-01LoongArch: gas: Ignore .align if it is at the start of a sectionmengqinggang1-25/+109
2024-03-31BFD: Fix the bug of R_LARCH_AGLIN caused by discard sectionmengqinggang1-4/+1