| Age | Commit message (Collapse) | Author | Files | Lines |
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bfd/
* elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter.
* elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data),
(swap_out_syms): Adjust elf_symbol_from invocation.
binutils/
* nm.c (print_symbol): Adjust elf_symbol_from invocation.
* objcopy.c (is_hidden_symbol): Likewise.
gas/
* config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust
elf_symbol_from invocation.
* config/tc-aarch64.c (s_variant_pcs): Likewise.
* config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise.
* config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation),
(ppc_fix_adjustable): Likewise.
* config/tc-xgate.c (xgate_frob_symbol): Likewise.
ld/
* plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from
invocation.
opcodes/
* ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
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We don't support power10 on ppc32, mainly because some instructions
have 34-bit fields for which we don't have relocations on ppc32.
If you try to assemble typical code, you'll see errors saying
"reloc ... not supported by object file format". Also, on 32-bit
hosts with binutils configured without a 64-bit bfd, you'll see errors
saying "bignum invalid" when using large offsets. But let's not kill
output of prefix insns entirely on 32-bit hosts.
* config/tc-ppc.c (md_assemble): Emit prefix insn by parts when
valueT is smaller than 64 bits.
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Inserting with replacement is wrong for some gas hash table uses.
This patch implements an htab_insert that conditionally replaces, and
similarly for str_hash_insert. str_hash_insert with replace=0 is
roughly equivalent to the older hash_insert, and str_hash_insert with
replace=1 to the older hash_jam, but return values are different. I
found it useful to know whether the slot was occupied prior to
inserting/replacing. I've also reinstated the fatal errors on messing
up opcode tables with duplicates.
PR 26513
* hash.h (htab_insert): Update prototype and comment.
(struct string_tuple): Make "value" a const void*.
(string_tuple_alloc): Likewise.
(str_hash_find, str_hash_find_n): Cast returned value.
(str_hash_insert): Add "replace" parameter, and return slot pointer.
Free alloc'd element when not inserted.
* hash.c (htab_insert): Likewise. Return slot when element exists,
otherwise return NULL.
* read.c (pop_insert): Insert into hash table without first searching.
* config/tc-avr.c (md_begin): Likewise.
* config/tc-msp430.c (md_begin): Likewise.
* config/tc-nds32.c (nds32_init_nds32_pseudo_opcodes): Likewise.
* config/tc-v850.c (md_begin): Likewise.
* macro.c (do_formals, define_macro, macro_expand_body): Likewise.
(delete_macro): Delete from hash table.
* config/tc-tic54x.c (subsym_create_or_replace): Correct logic.
* symbols.c (local_symbol_make, symbol_table_insert): Allow
replacement of hash table entries.
* config/obj-coff-seh.c (seh_hash_insert): Likewise.
* config/obj-coff.c (tag_insert): Likewise.
* config/tc-iq2000.c (iq2000_add_macro): Likewise.
* config/tc-m68k.c (md_begin): Likewise for aliases.
* config/tc-tic4x.c (tic4x_asg): Likewise.
* config/tc-tic6x.c (md_begin): Likewise.
* dw2gencfi.c (dwcfi_hash_find_or_make): Disallow replacement of
hash table entries.
* ecoff.c (add_string, get_tag): Likewise.
* macro.c (expand_irp): Likewise.
* config/obj-elf.c (build_additional_section_info): Likewise.
* config/tc-aarch64.c (insert_reg_alias): Likewise.
(checked_hash_insert): Likewise.
* config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise.
* config/tc-arc.c (arc_insert_opcode, declare_register): Likewise.
(declare_addrtype, md_begin, arc_extcorereg): Likewise.
* config/tc-arm.c (insert_reg_alias): Likewise.
(arm_tc_equal_in_insn, md_begin): Likewise.
* config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise.
* config/tc-cris.c (md_begin): Likewise.
* config/tc-crx.c (md_begin): Likewise.
* config/tc-csky.c (md_begin): Likewise.
* config/tc-d10v.c (md_begin): Likewise.
* config/tc-dlx.c (md_begin): Likewise.
* config/tc-ft32.c (md_begin): Likewise.
* config/tc-h8300.c (md_begin): Likewise.
* config/tc-hppa.c (md_begin): Likewise.
* config/tc-i386.c (md_begin): Likewise.
* config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise.
(md_begin, dot_alias): Likewise.
* config/tc-m68hc11.c (md_begin): Likewise.
* config/tc-m68k.c (md_begin): Likewise.
* config/tc-mcore.c (md_begin): Likewise.
* config/tc-microblaze.c (md_begin): Likewise.
* config/tc-mips.c (md_begin): Likewise.
* config/tc-mmix.c (md_begin): Likewise.
* config/tc-mn10200.c (md_begin): Likewise.
* config/tc-mn10300.c (md_begin): Likewise.
* config/tc-moxie.c (md_begin): Likewise.
* config/tc-nds32.c (nds32_relax_hint, md_begin): Likewise.
* config/tc-nios2.c (md_begin): Likewise.
* config/tc-ns32k.c (md_begin): Likewise.
* config/tc-pdp11.c (md_begin): Likewise.
* config/tc-pj.c (fake_opcode, md_begin): Likewise.
* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
* config/tc-pru.c (md_begin): Likewise.
* config/tc-riscv.c (init_ext_version_hash): Likewise.
(init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise.
(riscv_init_csr_hash): Likewise.
* config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise.
* config/tc-score.c (s3_insert_reg): Likewise.
(s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
(s7_build_dependency_insn_hsh, s7_insert_reg): Likewise.
* config/tc-sh.c (md_begin): Likewise.
* config/tc-sparc.c (md_begin): Likewise.
* config/tc-spu.c (md_begin): Likewise.
* config/tc-tic30.c (md_begin): Likewise.
* config/tc-tic4x.c (tic4x_inst_insert): Likewise.
* config/tc-tic54x.c (stag_add_field_symbols, md_begin): Likewise.
(tic54x_endstruct, tic54x_var, tic54x_macro_info): Likewise.
(subsym_substitute): Likewise.
* config/tc-tilegx.c (md_begin): Likewise.
* config/tc-tilepro.c (md_begin): Likewise.
* config/tc-vax.c (vip_begin): Likewise.
* config/tc-wasm32.c (md_begin): Likewise.
* config/tc-xgate.c (md_begin): Likewise.
* config/tc-z8k.c (md_begin): Likewise.
* testsuite/gas/ppc/dcbt.d,
* testsuite/gas/ppc/dcbt.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
* ecoff.c (add_string): Report fatal error on duplicates.
* config/tc-alpha.c (md_begin): Likewise.
* config/tc-arc.c (arc_insert_opcode, declare_register): Likewise.
(declare_addrtype, md_begin, arc_extcorereg): Likewise.
* config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise.
* config/tc-cris.c (md_begin): Likewise.
* config/tc-crx.c (md_begin): Likewise.
* config/tc-dlx.c (md_begin): Likewise.
* config/tc-hppa.c (md_begin): Likewise.
* config/tc-i386.c (md_begin): Likewise.
* config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise.
(md_begin): Likewise.
* config/tc-m68k.c (md_begin): Likewise.
* config/tc-mips.c (md_begin): Likewise.
* config/tc-nios2.c (md_begin): Likewise.
* config/tc-ns32k.c (md_begin): Likewise.
* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
* config/tc-pru.c (md_begin): Likewise.
* config/tc-riscv.c (init_ext_version_hash): Likewise.
(init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise.
* config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise.
* config/tc-sparc.c (md_begin): Likewise.
* config/tc-tic30.c (md_begin): Likewise.
* config/tc-tic4x.c (tic4x_inst_insert): Likewise.
* config/tc-tilegx.c (md_begin): Likewise.
* config/tc-tilepro.c (md_begin): Likewise.
* config/tc-vax.c (vip_begin): Likewise.
* config/tc-alpha.c,
* config/tc-arm.c,
* config/tc-avr.c,
* config/tc-cr16.c,
* config/tc-csky.c,
* config/tc-i386.c,
* config/tc-m68hc11.c,
* config/tc-m68k.c,
* config/tc-microblaze.c,
* config/tc-ns32k.c,
* config/tc-pj.c,
* config/tc-ppc.c,
* config/tc-score.c,
* config/tc-score7.c,
* config/tc-tic4x.c,
* config/tc-tic54x.c,
* config/tc-tilegx.c,
* config/tc-tilepro.c,
* config/tc-xgate.c: Formatting.
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These functions take an offset within frag, frag within section, and
section parameter. So it makes sense to order the parameters as
section, frag, offset.
* symbols.h (symbol_new, symbol_create, local_symbol_make),
(symbol_temp_new): Arrange params as section, frag, offset.
* symbols.c: Adjust to suit.
* as.c: Likewise.
* cgen.c: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* expr.c: Likewise.
* itbl-ops.c: Likewise.
* read.c: Likewise.
* stabs.c: Likewise.
* subsegs.c: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-elf.c: Likewise.
* config/obj-macho.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-csky.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-riscv.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-xtensa.c: Likewise.
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* config/obj-coff-seh.c (seh_hash_insert): Port to use new
str_htab type.
(seh_hash_find): Likewise.
(seh_hash_find_or_make): Likewise.
* config/obj-coff.c (tag_init): Likewise.
(tag_insert): Likewise.
(tag_find): Likewise.
* config/obj-elf.c (struct group_list): Likewise.
(build_additional_section_info): Likewise.
(free_section_idx): Likewise.
(elf_adjust_symtab): Likewise.
(elf_frob_file_after_relocs): Likewise.
* config/tc-aarch64.c (INSN_SIZE): Likewise.
(parse_reg): Likewise.
(insert_reg_alias): Likewise.
(create_register_alias): Likewise.
(s_unreq): Likewise.
(parse_shift): Likewise.
(parse_pldop): Likewise.
(parse_barrier): Likewise.
(parse_barrier_psb): Likewise.
(parse_bti_operand): Likewise.
(parse_sys_reg): Likewise.
(parse_sys_ins_reg): Likewise.
(lookup_mnemonic): Likewise.
(opcode_lookup): Likewise.
(parse_operands): Likewise.
(checked_hash_insert): Likewise.
(sysreg_hash_insert): Likewise.
(fill_instruction_hash_table): Likewise.
(md_begin): Likewise.
* config/tc-alpha.c (struct alpha_reloc_tag): Likewise.
(get_alpha_reloc_tag): Likewise.
(assemble_tokens_to_insn): Likewise.
(assemble_tokens): Likewise.
(md_begin): Likewise.
* config/tc-arc.c (arc_find_opcode): Likewise.
(arc_insert_opcode): Likewise.
(find_opcode_match): Likewise.
(declare_register): Likewise.
(declare_addrtype): Likewise.
(md_begin): Likewise.
(arc_parse_name): Likewise.
(tc_arc_regname_to_dw2regnum): Likewise.
(arc_extcorereg): Likewise.
* config/tc-arm.c (MVE_BAD_QREG): Likewise.
(arm_reg_parse_multi): Likewise.
(parse_reloc): Likewise.
(insert_reg_alias): Likewise.
(create_register_alias): Likewise.
(s_unreq): Likewise.
(parse_shift): Likewise.
(parse_psr): Likewise.
(parse_cond): Likewise.
(parse_barrier): Likewise.
(do_vfp_nsyn_opcode): Likewise.
(opcode_lookup): Likewise.
(arm_tc_equal_in_insn): Likewise.
(md_begin): Likewise.
* config/tc-avr.c (md_begin): Likewise.
(avr_ldi_expression): Likewise.
(md_assemble): Likewise.
(avr_update_gccisr): Likewise.
(avr_emit_insn): Likewise.
* config/tc-cr16.c (get_register): Likewise.
(get_register_pair): Likewise.
(get_index_register): Likewise.
(get_index_register_pair): Likewise.
(get_pregister): Likewise.
(get_pregisterp): Likewise.
(initialise_reg_hash_table): Likewise.
(md_begin): Likewise.
(cr16_assemble): Likewise.
(md_assemble): Likewise.
* config/tc-cris.c (cris_insn_first_word_frag): Likewise.
(md_begin): Likewise.
(cris_process_instruction): Likewise.
* config/tc-crx.c (get_register): Likewise.
(get_copregister): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-csky.c (md_begin): Likewise.
(parse_opcode): Likewise.
(get_operand_value): Likewise.
(v1_work_jbsr): Likewise.
(v2_work_rotlc): Likewise.
(v2_work_bgeni): Likewise.
(v2_work_not): Likewise.
* config/tc-d10v.c (sizeof): Likewise.
(md_begin): Likewise.
(do_assemble): Likewise.
(md_apply_fix): Likewise.
* config/tc-d30v.c (sizeof): Likewise.
(md_begin): Likewise.
(do_assemble): Likewise.
* config/tc-dlx.c (RELOC_DLX_VTENTRY): Likewise.
(md_begin): Likewise.
(machine_ip): Likewise.
* config/tc-ft32.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-h8300.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-hppa.c (pa_ip): Likewise.
(md_begin): Likewise.
* config/tc-i386.c (md_begin): Likewise.
(i386_print_statistics): Likewise.
(parse_insn): Likewise.
(process_operands): Likewise.
(i386_index_check): Likewise.
(parse_real_register): Likewise.
* config/tc-ia64.c (dot_rot): Likewise.
(dot_entry): Likewise.
(declare_register): Likewise.
(md_begin): Likewise.
(ia64_parse_name): Likewise.
(md_assemble): Likewise.
(dot_alias): Likewise.
(do_alias): Likewise.
(ia64_adjust_symtab): Likewise.
(do_secalias): Likewise.
(ia64_frob_file): Likewise.
* config/tc-m68hc11.c (m68hc11_print_statistics): Likewise.
(md_begin): Likewise.
(print_insn_format): Likewise.
(md_assemble): Likewise.
* config/tc-m68k.c (tc_gen_reloc): Likewise.
(m68k_ip): Likewise.
(md_begin): Likewise.
* config/tc-mcore.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-microblaze.c (md_begin): Likewise.
(md_assemble): Likewise.
(md_apply_fix): Likewise.
* config/tc-mips.c (nopic_need_relax): Likewise.
(md_begin): Likewise.
(macro_build): Likewise.
(mips16_macro_build): Likewise.
(mips_lookup_insn): Likewise.
(mips_ip): Likewise.
(mips16_ip): Likewise.
* config/tc-mmix.c (sizeof): Likewise.
(mmix_md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-mn10200.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-mn10300.c (HAVE_AM30): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-moxie.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-msp430.c (md_begin): Likewise.
(msp430_operands): Likewise.
(md_assemble): Likewise.
* config/tc-nds32.c (PV_DONT_CARE): Likewise.
(builtin_isreg): Likewise.
(builtin_regnum): Likewise.
(nds32_init_nds32_pseudo_opcodes): Likewise.
(nds32_lookup_pseudo_opcode): Likewise.
(nds32_relax_hint): Likewise.
(md_begin): Likewise.
(nds32_find_reloc_table): Likewise.
(nds32_elf_append_relax_relocs_traverse): Likewise.
(nds32_relax_branch_instructions): Likewise.
(md_convert_frag): Likewise.
(nds32_elf_analysis_relax_hint): Likewise.
(tc_nds32_regname_to_dw2regnum): Likewise.
* config/tc-nios2.c (nios2_opcode_lookup): Likewise.
(nios2_reg_lookup): Likewise.
(nios2_ps_lookup): Likewise.
(md_begin): Likewise.
* config/tc-ns32k.c (struct hash_control): Likewise.
(parse): Likewise.
(md_begin): Likewise.
* config/tc-pdp11.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-pj.c (fake_opcode): Likewise.
(alias): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
(md_assemble): Likewise.
* config/tc-pru.c (pru_opcode_lookup): Likewise.
(pru_reg_lookup): Likewise.
(md_begin): Likewise.
(md_end): Likewise.
* config/tc-riscv.c (init_ext_version_hash): Likewise.
(riscv_get_default_ext_version): Likewise.
(riscv_set_arch): Likewise.
(init_opcode_names_hash): Likewise.
(opcode_name_lookup): Likewise.
(enum reg_class): Likewise.
(hash_reg_name): Likewise.
(riscv_init_csr_hash): Likewise.
(reg_csr_lookup_internal): Likewise.
(reg_lookup_internal): Likewise.
(init_opcode_hash): Likewise.
(md_begin): Likewise.
(DECLARE_CSR): Likewise.
(macro_build): Likewise.
(riscv_ip): Likewise.
* config/tc-s390.c (register_name): Likewise.
(s390_setup_opcodes): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
(s390_insn): Likewise.
* config/tc-score.c (struct s3_reg_map): Likewise.
(s3_score_reg_parse): Likewise.
(s3_dependency_type_from_insn): Likewise.
(s3_parse_16_32_inst): Likewise.
(s3_parse_48_inst): Likewise.
(s3_insert_reg): Likewise.
(s3_build_reg_hsh): Likewise.
(s3_build_score_ops_hsh): Likewise.
(s3_build_dependency_insn_hsh): Likewise.
(s3_begin): Likewise.
* config/tc-score7.c (struct s7_reg_map): Likewise.
(s7_score_reg_parse): Likewise.
(s7_dependency_type_from_insn): Likewise.
(s7_parse_16_32_inst): Likewise.
(s7_build_score_ops_hsh): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
(s7_insert_reg): Likewise.
(s7_build_reg_hsh): Likewise.
(s7_begin): Likewise.
* config/tc-sh.c (EMPTY): Likewise.
(md_begin): Likewise.
(find_cooked_opcode): Likewise.
* config/tc-sparc.c (md_begin): Likewise.
(sparc_ip): Likewise.
* config/tc-spu.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-tic30.c (md_begin): Likewise.
(tic30_operand): Likewise.
(tic30_parallel_insn): Likewise.
(md_assemble): Likewise.
* config/tc-tic4x.c (TIC4X_ALT_SYNTAX): Likewise.
(tic4x_asg): Likewise.
(tic4x_inst_insert): Likewise.
(tic4x_inst_add): Likewise.
(md_begin): Likewise.
(tic4x_operand_parse): Likewise.
(md_assemble): Likewise.
* config/tc-tic54x.c (MAX_SUBSYM_HASH): Likewise.
(stag_add_field_symbols): Likewise.
(tic54x_endstruct): Likewise.
(tic54x_tag): Likewise.
(tic54x_remove_local_label): Likewise.
(tic54x_clear_local_labels): Likewise.
(tic54x_var): Likewise.
(tic54x_macro_start): Likewise.
(tic54x_macro_info): Likewise.
(tic54x_macro_end): Likewise.
(subsym_isreg): Likewise.
(subsym_structsz): Likewise.
(md_begin): Likewise.
(is_mmreg): Likewise.
(is_type): Likewise.
(encode_condition): Likewise.
(encode_cc3): Likewise.
(encode_cc2): Likewise.
(encode_operand): Likewise.
(tic54x_parse_insn): Likewise.
(tic54x_parse_parallel_insn_firstline): Likewise.
(subsym_create_or_replace): Likewise.
(subsym_lookup): Likewise.
(subsym_substitute): Likewise.
(tic54x_undefined_symbol): Likewise.
* config/tc-tic6x.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-tilegx.c (O_hw2_last_plt): Likewise.
(INSERT_SPECIAL_OP): Likewise.
(md_begin): Likewise.
(tilegx_parse_name): Likewise.
(parse_reg_expression): Likewise.
(md_assemble): Likewise.
* config/tc-tilepro.c (O_tls_ie_load): Likewise.
(INSERT_SPECIAL_OP): Likewise.
(tilepro_parse_name): Likewise.
(parse_reg_expression): Likewise.
(md_assemble): Likewise.
* config/tc-v850.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-vax.c (md_ri_to_chars): Likewise.
(vip_begin): Likewise.
(vip): Likewise.
(main): Likewise.
(md_begin): Likewise.
* config/tc-wasm32.c (md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-xgate.c (xgate_parse_operand): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-z8k.c (md_begin): Likewise.
(md_assemble): Likewise.
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* config/tc-ppc.c (md_assemble): Error for lmw, stmw, lswi, lswx,
stswi, or stswx in little-endian mode.
* testsuite/gas/ppc/476.d,
* testsuite/gas/ppc/476.s: Delete lmw, stmw, lswi, lswx, stswi, stswx.
* testsuite/gas/ppc/a2.d,
* testsuite/gas/ppc/a2.s: Move lmw, stmw, lswi, lswx, stswi, stswx..
* testsuite/gas/ppc/be.d,
* testsuite/gas/ppc/be.s: ..to here, new big-endian only test.
* testsuite/gas/ppc/le_error.d,
* testsuite/gas/ppc/le_error.l: New little-endian test.
* testsuite/gas/ppc/ppc.exp: Run new tests.
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Plus some leftover powerpc lynxos support.
bfd/
* coff-ppc.c: Delete.
* pe-ppc.c: Delete.
* pei-ppc.c: Delete.
* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Remove PE PPC.
* coffcode.h (coff_set_arch_mach_hook, coff_set_flags): Remove
PPCMAGIC code.
(coff_write_object_contents): Remove PPC_PE code.
* config.bfd: Move powerpcle-pe to removed targets.
* configure.ac: Remove powerpc PE entries.
* libcoff-in.h (ppc_allocate_toc_section): Delete.
(ppc_process_before_allocation): Delete.
* peXXigen.c: Remove POWERPC_LE_PE code and comments.
* targets.c: Remove powerpc PE vectors.
* po/SRC-POTFILES.in: Regenerate.
* libcoff.h: Regenerate.
* Makefile.in: Regenerate.
* configure: Regenerate.
binutils/
* dlltool.c: Remove powerpc PE support and comments.
* configure.ac: Remove powerpc PE dlltool config.
* configure: Regenerate.
gas/
* config/obj-coff.h: Remove TE_PE support.
* config/tc-ppc.c: Likewise.
* config/tc-ppc.h: Likewise.
* configure.tgt: Remove powerpc PE and powerpc lynxos.
* testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE
condition.
* testsuite/gas/macros/macros.exp: Don't xfail powerpc PE.
include/
* coff/powerpc.h: Delete.
ld/
* emulparams/ppcpe.sh: Delete.
* scripttempl/ppcpe.sc: Delete.
* emulparams/ppclynx.sh: Delete.
* Makefile.am (ALL_EMULATION_SOURCES): Remove ppc PE and lynxos.
* configure.tgt: Likewise.
* emultempl/beos.em: Remove powerpc PE support.
* emultempl/pe.em: Likewise.
* po/BLD-POTFILES.in: Regenerate.
* Makefile.in: Regenerate.
|
|
binutils/
* doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10.
gas/
* config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10.
* doc/c-ppc.texi: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
|
|
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
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|
include/
* opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following
PPC_OPERAND defines.
opcodes/
* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
New functions.
(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
YMSK2, XA6a, XA6ap, XB6a entries.
(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
(PPCVSX4): Define.
(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
* config/tc-ppc.c (pre_defined_registers): Add accumulators.
(md_assemble): Check acc specified in correct operand.
* testsuite/gas/ppc/outerprod.d,
* testsuite/gas/ppc/outerprod.s,
* testsuite/gas/ppc/vsx4.d,
* testsuite/gas/ppc/vsx4.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
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|
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
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|
This implements register saving and restoring in the __tls_get_addr
call stub, so that when glibc supports the optimized tls call stub gcc
can generate code that assumes only r0, r12 and of course r3 are
changed on a __tls_get_addr call. When gcc expects __tls_get_addr
calls to preserve registers the call will be to __tls_get_addr_desc,
which will be translated by the linker to a call to __tls_get_addr_opt.
bfd/
* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
tga_desc_fd.
(is_tls_get_addr): Match tga_desc and tga_desc_df too.
(STDU_R1_0R1, ADDI_R1_R1): Define.
(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd. Indirect
tga_desc_fd to opt_fd, and tga_desc to opt. Set
no_tls_get_addr_regsave.
(branch_reloc_hash_match): Add hash3 and hash4.
(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
(ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_relocate_section): Likewise.
(plt_stub_size, build_plt_stub): Likewise. Size regsave
__tls_get_addr stub.
(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
eh_frame.
(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too. Size
eh_frame for regsave __tls_get_addr.
gas/
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
__tls_get_addr_desc and __tls_get_addr_opt.
ld/
* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
--tls-get-addr-regsave and --no-tls-get-addr-regsave.
(params): Init new field.
* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
Document.
* testsuite/ld-powerpc/tlsdesc.s,
* testsuite/ld-powerpc/tlsdesc.d,
* testsuite/ld-powerpc/tlsdesc.wf,
* testsuite/ld-powerpc/tlsdesc2.d,
* testsuite/ld-powerpc/tlsdesc2.wf,
* testsuite/ld-powerpc/tlsexenors.d,
* testsuite/ld-powerpc/tlsexenors.r,
* testsuite/ld-powerpc/tlsexers.d,
* testsuite/ld-powerpc/tlsexers.r,
* testsuite/ld-powerpc/tlsexetocnors.d,
* testsuite/ld-powerpc/tlsexetocrs.d,
* testsuite/ld-powerpc/tlsexetocrs.r,
* testsuite/ld-powerpc/tlsopt6.d,
* testsuite/ld-powerpc/tlsopt6.wf: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
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|
|
|
This large patch removes the unnecessary bfd parameter from various
bfd section macros and functions. The bfd is hardly ever used and if
needed for the bfd_set_section_* or bfd_rename_section functions can
be found via section->owner except for the com, und, abs, and ind
std_section special sections. Those sections shouldn't be modified
anyway.
The patch also removes various bfd_get_section_<field> macros,
replacing their use with bfd_section_<field>, and adds
bfd_set_section_lma. I've also fixed a minor bug in gas where
compressed section renaming was done directly rather than calling
bfd_rename_section. This would have broken bfd_get_section_by_name
and similar functions, but that hardly mattered at such a late stage
in gas processing.
bfd/
* bfd-in.h (bfd_get_section_name, bfd_get_section_vma),
(bfd_get_section_lma, bfd_get_section_alignment),
(bfd_get_section_size, bfd_get_section_flags),
(bfd_get_section_userdata): Delete.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment): Lose bfd parameter.
(bfd_section_flags, bfd_section_userdata): New.
(bfd_is_com_section): Rename parameter.
* section.c (bfd_set_section_userdata, bfd_set_section_vma),
(bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section),
(bfd_set_section_size): Delete bfd parameter, rename section parameter.
(bfd_set_section_lma): New.
* bfd-in2.h: Regenerate.
* mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param,
update callers.
* aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c,
* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
* compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c,
* elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c,
* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
* elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c,
* elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c,
* elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c,
* elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c,
* elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c,
* elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c,
* elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
* elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c,
* elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c,
* mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c,
* peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c,
* xcofflink.c: Update throughout for bfd section macro and function
changes.
binutils/
* addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c,
* objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c,
* od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c,
* resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update
throughout for bfd section macro and function changes.
gas/
* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,
* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,
* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,
* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,
* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,
* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,
* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,
* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,
* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,
* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,
* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,
* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,
* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,
* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,
* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,
* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,
* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,
* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for
bfd section macro and function changes.
* write.c (compress_debug): Use bfd_rename_section.
gdb/
* aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c,
* coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c,
* dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c,
* exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h,
* hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c,
* i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c,
* maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c,
* mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c,
* objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c,
* ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c,
* rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c,
* s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c,
* solib-spu.c, * solib-svr4.c, * solib-target.c,
* spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c,
* symmisc.c, * symtab.c, * target.c, * windows-nat.c,
* xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c,
* mi/mi-interp.c: Update throughout for bfd section macro and
function changes.
* gcore (gcore_create_callback): Use bfd_set_section_lma.
* spu-tdep.c (spu_overlay_new_objfile): Likewise.
gprof/
* corefile.c, * symtab.c: Update throughout for bfd section
macro and function changes.
ld/
* ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c,
* emultempl/aarch64elf.em, * emultempl/aix.em,
* emultempl/armcoff.em, * emultempl/armelf.em,
* emultempl/cr16elf.em, * emultempl/cskyelf.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update
throughout for bfd section macro and function changes.
libctf/
* ctf-open-bfd.c: Update throughout for bfd section macro changes.
opcodes/
* arc-ext.c: Update throughout for bfd section macro changes.
sim/
* common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c,
* erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c,
* m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c,
* rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c,
* rx/trace.c: Update throughout for bfd section macro changes.
|
|
* config/tc-ppc.c (ppc_elf_suffix): Display the relocation
operator on GOT reloc warnings/errors.
|
|
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
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|
* config/tc-ppc.c (ppc_handle_align): Add parentheses.
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|
This patch corrects ppc rs_align_code handling to choose the alignment
nops based on the machine in force at the alignment directive rather
than the machine at the end of file.
* config/tc-ppc.h (ppc_nop_select): Declare.
(NOP_OPCODE): Define.
* config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu.
(ppc_nop_encoding_for_rs_align_code): New enum.
(ppc_nop_select): New function.
(ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag.
* testsuite/gas/ppc/groupnop.d,
* testsuite/gas/ppc/groupnop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
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Targets that lack ppc64 support were failing the new prefix-reloc
test. This patch adds some test infrastructure to deal with that, and
changes the powerpc gas usage info so that "-a64" is omitted when
unsupported.
I've been meaning to break up the usage message for a long time;
While doing so causes translators some work now, it should make it
easier next time a new powerpc option is added.
* config/tc-ppc.c (is_ppc64_target): New function.
(md_show_usage): Split up usage message. Don't show -a64 when
unsupported.
testsuite/gas/ppc/ppc.exp (supports_ppc64): New.
(prefix-reloc): Only run for ppc64.
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|
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
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opcodes/
* ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
(insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
(extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
(powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
XTOP>): Define and add entries.
(P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
(prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
gas/
* config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that
are 32-bits or smaller.
* messages.c (as_internal_value_out_of_range): Do not truncate
variables and use BFD_VMA_FMT to print them.
* testsuite/gas/ppc/prefix-pcrel.s,
* testsuite/gas/ppc/prefix-pcrel.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
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This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
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GOT and PLT relocs shouldn't have their symbols replaced with a
section symbol plus added. Nor should the HIGHA TLS relocations,
which failed to be caught by the range test in ppc_fix_adjustable.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
gas/
* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
relocs, and VLE sdarel relocs.
* testsuite/gas/ppc/power4.d: Adjust.
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Fixes non-ELF powerpc build failure:
tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used
* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
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The syntax we ended up with for -m32 -fPIC calls to __tls_get_addr is
rather weird.
bl __tls_get_addr+0x8000(gd0@tlsgd)@plt
This came about by accident, probably due to requiring the arg reloc
before the call reloc.
Of course the @plt really belongs with __tls_get_addr since it affects
the call rather than the call arg, and it isn't a great deal of
trouble to ensure the relocs are emitted in the correct order. This
patch supports a newer syntax, like so:
bl __tls_get_addr+0x8000@plt(gd0@tlsgd)
gas/
* config/tc-ppc.c (parse_tls_arg): New function, extracted..
(md_assembler): ..from here. Call it after parsing other
suffix modifiers too.
ld/
* testsuite/ld-powerpc/tls32.s: Test new @plt syntax.
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This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields. That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
e_li r3, IV_table@l+0x00
which was being assembled to
8: 70 60 00 00 e_li r3,0
a: R_PPC_ADDR16_LO IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.
Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation. In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant. Thus @l should only produce a 16-bit
value, I think. So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.
include/
* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
mask and shift value.
(ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li
specially.
gas/
* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
TLS tweaks. Handle e_li. Warn on unexpected operand field
for lo16/hi16/ha16 relocs.
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We support source like the following
.data
.quad x-.
.space 8
x:
where at the time the .quad line is assembled, x is unknown so a fixup
is emitted for later evaluation. This is supported for data even when
the target may not have relocations for the expression, for example,
32-bit powerpc targets lack a 64-bit reloc. As long as the fixup
resolves at assembly time, gas is happy.
The idea of this patch is to support fixups that resolve at assembly
time for instructions too, even when the target might lack the
necessary relocations (and thus no howto).
* config/tc-ppc.c (fixup_size): New function.
(md_assemble): Use it to derive size and pcrel directly
from fixup reloc type.
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The instruction mask bits should never overlap any of the operands,
nor should operand bits overlap, but some operands weren't checked.
This patch arranges to check the omitted operands, using a mask
returned by the operand->insert function. Some tweaking of various
insert functions is needed to support this: The error case must set
field bits.
Since I was looking at the insert functions, I tidied some dead code
and simplified some of the powerpc_operands entries.
gas/
* config/tc-ppc.c (insn_validate): Don't ignore mask in
PPC_OPSHIFT_INV case. Call the insert function to calculate
a mask.
opcodes/
* ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
(insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
(insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
(insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
Don't return zero on error, insert mask bits instead.
(insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
(insert_sh6, extract_sh6): Delete dead code.
(insert_sprbat, insert_sprg): Use unsigned comparisions.
(powerpc_operands <OIMM>): Set shift count rather than using
PPC_OPSHIFT_INV.
<SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
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This adds another check that might have saved me a little time
recently if it had been present.
* config/tc-ppc.c (insn_validate): Check that optional operands
are not followed by non-optional operands.
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Fix a build error:
cc1: warnings being treated as errors
.../gas/config/tc-ppc.c: In function 'ppc_dwsect':
.../gas/config/tc-ppc.c:4091: warning: comparison between signed and unsigned
make[4]: *** [config/tc-ppc.o] Error 1
observed with GCC 4.1.2 with the `powerpc-beos' target.
Here `flag' identifies the type of a DWARF section, as used with the the
first operand to the `.dwsect' pseudo-op, and has no notion of a sign,
or for that matter being arithmetic in the first place[1]. We already
handle this correctly with the `flag' member of the `xcoff_dwsect_name'
structure, however not in the local variable used in GAS to hold the
parsed value of said `.dwsect' pseudo-op's operand.
Use an unsigned data type in GAS then too, observing that both `offsetT'
and `valueT' have the same width, as they correspond to `bfd_signed_vma'
and `bfd_vma' respectively.
References:
[1] "AIX Version 7.2: Assembler Language Reference", IBM Corporation
2015, 2018, Section ".dwsect pseudo-op", pp. 531-532
gas/
* config/tc-ppc.c (ppc_dwsect): Use `valueT' rather than
`offsetT' as the type of `flag'.
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There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
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Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
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R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the
linker that linkage stubs for PLT calls or long branches can't use r2
for pic addressing. Instead, new stubs that generate pc-relative
addresses are used. One complication is that pc-relative offsets to
the PLT may need to be 64-bit in large programs, in contrast to the
toc-relative addressing used by older PLT linkage stubs where a 32-bit
offset is sufficient until the PLT itself exceeds 2G in size.
.eh_frame info to cover the _notoc stubs is yet to be implemented.
bfd/
* elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12),
(ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0),
(SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define.
(ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC.
(ppc_stub_type): Add ppc_stub_long_branch_notoc,
ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc,
ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and
ppc_stub_plt_call_both.
(is_branch_reloc): Add R_PPC64_REL24_NOTOC.
(build_offset, size_offset): New functions.
(plt_stub_size): Support plt_call_notoc and plt_call_both.
(ppc_build_one_stub, ppc_size_one_stub): Support new stubs.
(toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC.
(ppc64_elf_size_stubs): Likewise, and new stubs.
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise.
* reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @notoc.
(ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC.
ld/
* testsuite/ld-powerpc/ext.d,
* testsuite/ld-powerpc/ext.s,
* testsuite/ld-powerpc/ext.lnk,
* testsuite/ld-powerpc/notoc.d,
* testsuite/ld-powerpc/notoc.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
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This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors. Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs. The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl. I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of
simplified mnemonics for special purpose register access. Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.
gas/
* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* testsuite/gas/ppc/broadway.d,
* testsuite/gas/ppc/broadway.s: New test for broadway.
* testsuite/gas/ppc/ppc.exp: Run new test.
include/
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
support disjointed BAT.
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
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This adds support for ".localentry 1", a new st_other
STO_PPC64_LOCAL_MASK encoding that signifies a function with a single
entry point like ".localentry 0", but unlike a ".localentry 0"
function does not preserve r2.
include/
* elf/ppc64.h: Specify byte offset to local entry for values
of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return
value for such functions when entering via global entry point.
Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
bfd/
* elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off
for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1.
gas/
* config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values
of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits.
ld/testsuite/
* ld-powerpc/elfv2.s: Add .localentry f5,1 testcase.
* ld-powerpc/elfv2exe.d: Update.
* ld-powerpc/elfv2so.d: Update.
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opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
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include/
* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
(vle_num_opcodes): Likewise.
(spe2_num_opcodes): Likewise.
opcodes/
* ppc-opc.c (powerpc_num_opcodes): Likewise.
(vle_num_opcodes): Likewise.
(spe2_num_opcodes): Likewise.
* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
initialization loop.
(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
only once.
gas/
* config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code
to dump the entire opcode table.
(ppc_setup_opcodes) <spe2_opcodes>: Likewise.
(ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of
opcode index.
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gas/
PR binutils/23013
* config/tc-ppc.c (ppc_set_cpu): Select appropriate cpu when ppc_obj64
and little endian.
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Oops, not tested well enough. -mpower9 sets all the PPC_OPCODE_POWERn
for n <= 9.
* config/tc-ppc.c (ppc_handle_align): Correct last patch. Really
don't emit a group terminating nop for power9. Simplify cpu
tests.
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Power9 doesn't have a group terminating nop, so we may as well emit a
normal nop for power9. Not that it matters a great deal, I believe
ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware.
* config/tc-ppc.c (ppc_handle_align): Don't emit a group
terminating nop for power9.
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Checks for insn alignment were hopelessly confused when misaligned
data starts a new frag. The real-world testcase happened to run out
of frag space in the middle of emitting a trace-back table via
something like:
.byte 0 /* VERSION=0 */
.byte 9 /* LANG=C++ */
.byte 34 /* Bits on: has_tboff, fp_present */
.byte 64 /* Bits on: name_present */
.byte 128 /* Bits on: stores_bc, FP_SAVED=0 */
.byte 0 /* Bits on: GP_SAVED=0 */
.byte 2 /* FIXEDPARMS=2 */
.byte 1 /* FLOATPARMS=0, parmsonstk */
.long 0
.long 768 /* tb_offset: 0x300 */
.hword 45 /* Function name length: 45 */
.long 0x334e5a5f
.long 0x31766f70
.long 0x65744932
.long 0x69746172
.long 0x7a5f6e6f
.long 0x64504533
.long 0x5f534e50
.long 0x72463431
.long 0x61746361
.long 0x74535f6c
.long 0x74637572
.byte 0x45
.byte 0
The trigger being those misaligned .long's output for the function
name. A most horrible way to output a string, especially considering
endian issues..
PR 22819
* config/tc-ppc.c (md_assemble): Rewrite insn alignment checking.
(ppc_frag_check): Likewise.
* testsuite/gas/ppc/misalign.d,
* testsuite/gas/ppc/misalign.l,
* testsuite/gas/ppc/misalign.s: New test.
* testsuite/gas/ppc/misalign2.d,
* testsuite/gas/ppc/misalign2.s: New test.
* testsuite/gas/ppc/ppc.exp: Run them.
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It's obviously wrong to mask SPRs to 8 bits.
PR 21118
* config/tc-ppc.c (md_assemble): Don't mask register number.
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include/
* opcode/ppc.h (PPC_INT_FMT): Define.
(struct powerpc_opcode) <opcode>: Update type.
(struct powerpc_opcode) <mask>: Likewise.
(struct powerpc_opcode) <bitm>: Likewise.
(struct powerpc_opcode) <insert>: Likewise.
(struct powerpc_opcode) <extract>: Likewise.
(ppc_optional_operand_value): Likewise.
gas/
* config/tc-ppc.c (last_insn): Update type.
(insn_validate) <omask, mask>: Likewise.
(ppc_setup_opcodes) <mask, right_bit>: Likewise.
<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
(ppc_insert_operand): Update return and argument types and remove
unneeded type casts.
<min, max, right, tmp>: Update type.
(md_assemble): Remove unneeded type casts.
<insn, val, tmp_insn>: Update type.
opcodes/
* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
(operand_value_powerpc): Update return and argument type.
<value, top>: Update type.
(skip_optional_operands): Update argument type.
(lookup_powerpc): Likewise.
(lookup_vle): Likewise.
<table_opcd, table_mask, insn2>: Update type.
(lookup_spe2): Update argument type.
<table_opcd, table_mask, insn2>: Update type.
(print_insn_powerpc) <insn, value>: Update type.
Use PPC_INT_FMT for printing instructions and operands.
* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
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include/
* elf/ppc.h (R_PPC_VLE_ADDR20): New relocation.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20.
(ppc_elf_check_relocs): Handle it.
(ppc_elf_vle_split20): New function.
(ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20.
binutils/
* readelf.c (get_elf_section_flags): Add VLE.
(process_section_headers): Add VLE key to details.
gas/
* config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag.
(ppc_elf_section_letter): New function.
* config/tc-ppc.h (md_elf_section_letter): New.
* testsuite/gas/elf/section10.d: Adjust for VLE.
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include/
* opcode/ppc.h:
(spe2_opcodes, spe2_num_opcodes): New.
(PPC_OPCODE_SPE2): New define.
(PPC_OPCODE_EFS2): Likewise.
(SPE2_XOP): Likewise.
(SPE2_XOP_TO_SEG): Likewise.
opcodes/
* ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
PPC_OPCODE_EFS2 flag to "e200z4" entry.
New entries efs2 and spe2.
Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
(SPE2_OPCD_SEGS): New macro.
(spe2_opcd_indices): New.
(disassemble_init_powerpc): Handle SPE2 opcodes.
(lookup_spe2): New function.
(print_insn_powerpc): call lookup_spe2.
* ppc-opc.c (insert_evuimm1_ex0): New function.
(extract_evuimm1_ex0): Likewise.
(insert_evuimm_lt8): Likewise.
(extract_evuimm_lt8): Likewise.
(insert_off_spe2): Likewise.
(extract_off_spe2): Likewise.
(insert_Ddd): Likewise.
(extract_Ddd): Likewise.
(DD): New operand.
(EVUIMM_LT8): Likewise.
(EVUIMM_LT16): Adjust.
(MMMM): New operand.
(EVUIMM_1): Likewise.
(EVUIMM_1_EX0): Likewise.
(EVUIMM_2): Adjust.
(NNN): New operand.
(VX_OFF_SPE2): Likewise.
(BBB): Likewise.
(DDD): Likewise.
(VX_MASK_DDD): New mask.
(HH): New operand.
(VX_RA_CONST): New macro.
(VX_RA_CONST_MASK): Likewise.
(VX_RB_CONST): Likewise.
(VX_RB_CONST_MASK): Likewise.
(VX_OFF_SPE2_MASK): Likewise.
(VX_SPE_CRFD): Likewise.
(VX_SPE_CRFD_MASK VX): Likewise.
(VX_SPE2_CLR): Likewise.
(VX_SPE2_CLR_MASK): Likewise.
(VX_SPE2_SPLATB): Likewise.
(VX_SPE2_SPLATB_MASK): Likewise.
(VX_SPE2_OCTET): Likewise.
(VX_SPE2_OCTET_MASK): Likewise.
(VX_SPE2_DDHH): Likewise.
(VX_SPE2_DDHH_MASK): Likewise.
(VX_SPE2_HH): Likewise.
(VX_SPE2_HH_MASK): Likewise.
(VX_SPE2_EVMAR): Likewise.
(VX_SPE2_EVMAR_MASK): Likewise.
(PPCSPE2): Likewise.
(PPCEFS2): Likewise.
(vle_opcodes): Add EFS2 and some missing SPE opcodes.
(powerpc_macros): Map old SPE instructions have new names
with the same opcodes. Add SPE2 instructions which just are
mapped to SPE2.
(spe2_opcodes): Add SPE2 opcodes.
gas/
* config/tc-ppc.c:
(md_parse_option): Add mspe2 switch.
(md_show_usage): Document -mspe2.
(ppc_setup_opcodes): Handle spe2_opcodes.
* doc/as.texinfo: Document -mspe2.
* doc/c-ppc.texi: Likewise.
* testsuite/gas/ppc/efs.d: New file.
* testsuite/gas/ppc/efs.s: Likewise.
* testsuite/gas/ppc/efs2.d: Likewise.
* testsuite/gas/ppc/efs2.s: Likewise.
* testsuite/gas/ppc/ppc.exp: Run new tests.
* testsuite/gas/ppc/spe.d: New file.
* testsuite/gas/ppc/spe.s: Likewise.
* testsuite/gas/ppc/spe2-checks.d: Likewise.
* testsuite/gas/ppc/spe2-checks.l: Likewise.
* testsuite/gas/ppc/spe2-checks.s: Likewise.
* testsuite/gas/ppc/spe2.d: Likewise.
* testsuite/gas/ppc/spe2.s: Likewise.
* testsuite/gas/ppc/spe_ambiguous.d: Likewise.
* testsuite/gas/ppc/spe_ambiguous.s: Likewise.
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The -mhtm option is fairly useless too.
include/
* opcode/ppc.h (PPC_OPCODE_HTM): Delete.
gas/
* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
* testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm".
* ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.
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This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases. For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.
binutils/
* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
"raw" option.
(lookup_powerpc): Don't special case -1 dialect. Handle
PPC_OPCODE_RAW.
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
lookup_powerpc call, pass it on second.
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This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA. They ought to both be -4. The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
/* Make it pc-relative. If the back-end code has not
selected a pc-relative reloc, cancel the adjustment
we do later on all pc-relative relocs. */
*not* cancelling the pc-relative adjustment. So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust. Having the new internal reloc also makes it easy to
support
addpcis rx,sym@ha
as an equivalent to
addpcis rx,(sym-0f)@ha
0:
The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.
Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.
include/
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
(ppc64_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
ld/
* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
limits of addpcis range.
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