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path: root/gas/config/tc-i386.c
AgeCommit message (Expand)AuthorFilesLines
2018-03-08x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCHJan Beulich1-6/+0
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich1-1/+5
2018-03-08x86: drop FloatDJan Beulich1-7/+7
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich1-12/+13
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-10/+37
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu1-145/+135
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-2/+7
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-2/+234
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+27
2018-02-17Add .nop assembler directiveH.J. Lu1-106/+166
2018-02-13x86-64: Generate branch with PLT32 relocationH.J. Lu1-1/+48
2018-02-13Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton1-1/+1
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+2
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+2
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-3/+7
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-38/+43
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-77/+80
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-11/+8
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-130/+115
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu1-0/+6
2017-12-15x86: correct operand type checksJan Beulich1-4/+4
2017-12-15x86: correct abort checkJan Beulich1-2/+2
2017-11-30x86: drop Vec_Disp8Jan Beulich1-54/+16
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich1-3/+9
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-5/+1
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-2/+2
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-7/+1
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-1/+1
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-1/+2
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich1-5/+17
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu1-1/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu1-0/+2
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-0/+20
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-40/+19
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-7/+2
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-17/+58
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-44/+114
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+2
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-8/+8
2017-01-20Fix potential array overrun in x86 assembler.Nick Clifton1-1/+1
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+3
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+3
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+22
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