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AgeCommit message (Expand)AuthorFilesLines
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks1-0/+15
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson1-0/+10
2019-07-24Update the Swedish translation for the gas sub-directory.Nick Clifton1-0/+4
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-0/+4
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra1-0/+6
2019-07-24Define ELF_OSABI for visiumAlan Modra1-0/+6
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov1-0/+6
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra1-0/+15
2019-07-23gas "mbind sections" testAlan Modra1-0/+4
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks1-0/+12
2019-07-19x86: Pass -O0 to assembler in noextreg.dH.J. Lu1-0/+4
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi1-0/+8
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi1-0/+6
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-0/+10
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-0/+8
2019-07-18gas: .lcomm gets an alignment argument in eBPFJose E. Marchesi1-0/+6
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+9
2019-07-17x86: replace "anymem" checks where possibleJan Beulich1-0/+8
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-0/+7
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+14
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-0/+9
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi1-0/+7
2019-07-09Re: gas/ELF: don't accumulate .type settingsAlan Modra1-0/+9
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-0/+19
2019-07-04x86: correct "-Q" option handlingJan Beulich1-0/+6
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich1-0/+11
2019-07-03Fix assembler tests to work with toolchains that have been configured with --...Nick Clifton1-0/+96
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect structural...Barnaby Wilks1-0/+8
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford1-0/+5
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford1-0/+7
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford1-0/+7
2019-07-01Fix bug when generating REL type relocs for assembler generated build notes.Nick Clifton1-0/+9
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-0/+13
2019-07-01Document the .value directive supported by the x86 and x86_64 assemblers.Nick Clifton1-0/+6
2019-07-01Correct a typo in the description of the Align and P2align directives.Nick Clifton1-0/+7
2019-07-01Fix spelling error in assembler documentation.Nick Clifton1-0/+5
2019-07-01x86: drop Vec_Imm4Jan Beulich1-0/+8
2019-07-01x86: limit ImmExt abuseJan Beulich1-0/+7
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+14
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+20
2019-07-01x86: StaticRounding implies SAEJan Beulich1-0/+5
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-0/+29
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+23
2019-07-01x86: use encoding_length() also elsewhereJan Beulich1-0/+4
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich1-0/+10
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-0/+9
2019-06-27This fixes a bug in the ARm assembler where an immediate operand larger than ...Barnaby Wilk s1-0/+14
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-0/+18
2019-06-26Fix a few non-dash safe xstormy16 shell scripts.Jim Wilson1-0/+6
2019-06-26i386: Document memory size reference in assemblerLili Cui1-0/+6