aboutsummaryrefslogtreecommitdiff
path: root/gas/ChangeLog
AgeCommit message (Collapse)AuthorFilesLines
2011-03-24gas: blackfin: reject invalid register destinations for vector add/subMike Frysinger1-0/+7
The destination registers with vector add/sub insns must be different, so make sure gas rejects attempt to write these. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24gas: blackfin: catch invalid dest dregs in dsp mult insnsMike Frysinger1-0/+6
While we were catching a few mismatches in vectorized dsp mult insns, the error we displayed was misleading. Once we fix that up, we can convert previously dead code into proper checking for destination dreg matching. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24gas: blackfin: catch invalid register combinations with SEARCH/BITMUXMike Frysinger1-0/+6
The destination registers for SEARCH cannot be the same. Same rule for the source registers for BITMUX. Signed-off-by: Mike Frsyinger <vapier@gentoo.org>
2011-03-232011-03-23 Eric B. Weddington <eric.weddington@atmel.com>Eric B. Weddington1-0/+6
* config/tc-avr.c (mcu_types): Add new xmega devices: atxmega64a1u, atxmega128a1u, atxmega16x1, atxmega32x1, atxmega128b1, atxmega256a3bu. * doc/c-avr.texi: Document new device names.
2011-03-22/bfd:Eric B. Weddington1-0/+12
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * archures.c: Add AVR XMEGA architecture information. * cpu-avr.c (arch_info_struct): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. (elf32_avr_object_p): Likewise. /gas: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (struct avr_opcodes_s): Add opcode field. (AVR_INSN): Change definition to match. (avr_opcodes): Likewise, change to match. (mcu_types): Add XMEGA architecture names and new XMEGA device names. (md_show_usage): Add XMEGA architecture names. (avr_operand): Add 'E' constraint for DES instruction of XMEGA devices. Add support for SPM Z+ instruction. * doc/c-avr.texi: Add documentation for XMEGA architectures and devices. /include/opcode: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): New instruction set flags. (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. /ld: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures. (eavrxmega?.c): Likewise. * configure.tgt (targ_extra_emuls): Likewise. * emulparams/avrxmega1.sh: New file. * emulparams/avrxmega2.sh: Likewise. * emulparams/avrxmega3.sh: Likewise. * emulparams/avrxmega4.sh: Likewise. * emulparams/avrxmega5.sh: Likewise. * emulparams/avrxmega6.sh: Likewise. * emulparams/avrxmega7.sh: Likewise. * emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation): Add avrxmega6, avrxmega7 to list of architectures for no stubs. /opcodes: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr-dis.c (avr_operand): Add opcode_str parameter. Check for post-increment to support LPM Z+ instruction. Add support for 'E' constraint for DES instruction. (print_insn_avr): Adjust calls to avr_operand. Rename variable.
2011-03-212011-03-21 Eric B. Weddington <eric.weddington@atmel.com>Eric B. Weddington1-0/+4
* config/tc-avr.c (md_show_usage): Add "Assembler" text to output.
2011-03-18 * config/obj-elf.c (elf_frob_symbol): Report S_SET_SIZE symbolAlan Modra1-0/+5
on .size expression errors rather than symbols in the size expression.
2011-03-18gas/Alan Modra1-0/+7
* input-scrub.c (line_numberT): Delete. (input_scrub_close): Reset line counters. * messages.c (as_show_where): Don't print invalid line number. (as_warn_internal, as_bad_internal): Likewise. gas/testsuite/ * gas/elf/bad-size.err: Adjust expected error. * gas/i386/bad-size.warn: Likewise. * gas/i386/inval-equ-2.l: Likewise. * gas/symver/symver2.l: Likewise.
2011-03-18 * read.c (read_a_source_file): Remove md_after_pass_hook.Alan Modra1-0/+9
Move "quit" label before set of dot_symbol. * config/tc-d10v.h (md_after_pass_hook): Don't define. * config/tc-d30v.h (md_after_pass_hook): Likewise. * config/tc-m32r.h (md_after_pass_hook): Likewise. (md_cleanup): Define to call m32r_fill_insn.
2011-03-182011-03-18 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel1-0/+5
* config/tc-s390.c (md_parse_option): Add -march=all option which switches to the highest available CPU.
2011-03-17 PR 12569Alan Modra1-0/+8
* expr.c (operand): Correct passing of "mode" to expr. * read.c (do_org): Allow expr_section. (get_known_segmented_expression): Don't assert anything about the segment.
2011-03-16Add --size-check=[error|warning].H.J. Lu1-0/+12
gas/ 2011-03-16 H.J. Lu <hongjiu.lu@intel.com> * as.c (show_usage): Add --size-check=. (parse_args): Add and handle OPTION_SIZE_CHECK. * as.h (flag_size_check): New. * config/obj-elf.c (elf_frob_symbol): Use as_bad to report bad .size directive only for --size-check=error. * doc/as.texinfo: Document --size-check=. gas/testsuite/ 2011-03-16 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/bad-size.d: New. * gas/i386/bad-size.s: Likewise. * gas/i386/bad-size.warn: Likewise. * gas/i386/i386.exp: Run bad-size for ELF targets.
2011-03-15gas: blackfin: add support for bf54x-0.4Mike Frysinger1-0/+5
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-14include/elf/Richard Sandiford1-0/+6
* arm.h (R_ARM_IRELATIVE): New relocation. bfd/ * reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation. * bfd-in2.h: Regenerate. * elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE entry. (elf32_arm_howto_from_type): Update accordingly. (elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE. (elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3. (arm_plt_info): New structure, split out from elf32_arm_link_hash_entry with an extra noncall_refcount field. (arm_local_iplt_info): New structure. (elf_arm_obj_tdata): Add local_iplt. (elf32_arm_local_iplt): New accessor macro. (elf32_arm_link_hash_entry): Replace plt_thumb_refcount, plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info. Change tls_type to a bitfield and add is_iplt. (elf32_arm_link_hash_newfunc): Update accordingly. (elf32_arm_allocate_local_sym_info): New function. (elf32_arm_create_local_iplt): Likewise. (elf32_arm_get_plt_info): Likewise. (elf32_arm_plt_needs_thumb_stub_p): Likewise. (elf32_arm_get_local_dynreloc_list): Likewise. (create_ifunc_sections): Likewise. (elf32_arm_copy_indirect_symbol): Update after the changes to elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set. (arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info to get PLT information. Assert that all STT_GNU_IFUNC references are turned into PLT references. (arm_build_one_stub): Pass the symbol type to elf32_arm_final_link_relocate. (elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub. (elf32_arm_allocate_irelocs): New function. (elf32_arm_add_dynreloc): In static objects, use .rel.iplt for all R_ARM_IRELATIVE. (elf32_arm_allocate_plt_entry): New function. (elf32_arm_populate_plt_entry): Likewise. (elf32_arm_final_link_relocate): Add an st_type parameter. Set srelgot to null for static objects. Use separate variables to record which st_value and st_type should be used when generating a dynamic relocation. Use elf32_arm_get_plt_info to find the symbol's PLT information, setting has_iplt_entry, splt, plt_offset and gotplt_offset accordingly. Check whether STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change the relocation target accordingly. Broaden assert to include .iplts. Don't set sreloc for static relocations. Assert that we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32 and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC symbol. Pass the symbol type to arm_type_of_stub. Conditionally resolve GOT references to the .igot.plt entry. (elf32_arm_relocate_section): Update the call to elf32_arm_final_link_relocate. (elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_check_relocs): Always create ifunc sections. Set isym at the same time as setting h. Use elf32_arm_allocate_local_sym_info to allocate local symbol information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Record PLT information for local STT_GNU_IFUNC functions as well as global functions. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols. Don't remove STT_GNU_IFUNC PLTs unless all references have been removed. Update after the changes to elf32_arm_link_hash_entry. (allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT entries should live in .plt or .iplt. Check whether the .igot.plt and .got entries can be combined. Use elf32_arm_allocate_plt_entry to allocate .plt and .(i)got.plt entries. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Likewise other non-.got dynamic relocations. (elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt and dynamic relocations for local STT_GNU_IFUNC symbols. Check whether the .igot.plt and .got entries can be combined. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Use stashed section pointers intead of strcmp checks. Handle iplt and igotplt. (elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry to fill in .plt, .got.plt and .rel(a).plt entries. Point STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations resolve to it. (elf32_arm_output_plt_map_1): New function, split out from elf32_arm_output_plt_map. Handle .iplt entries. Use elf32_arm_plt_needs_thumb_stub_p. (elf32_arm_output_plt_map): Call it. (elf32_arm_output_arch_local_syms): Add mapping symbols for local .iplt entries. (elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols. (elf32_arm_swap_symbol_out): Likewise. (elf32_arm_add_symbol_hook): New function. (elf_backend_add_symbol_hook): Define for all targets. opcodes/ * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. gas/ * config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to determine whether a relocation is needed. (md_apply_fix, arm_apply_sym_value): Likewise. ld/testsuite/ * ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd, ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd, ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s, ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd, ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd, ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd, ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s, ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd, ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd, ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd, ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s, ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd, ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd, ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd, ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s, ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd, ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd, ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd, ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s, ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd, ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd, ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld, ld-arm/ifunc-static.ld: New tests. * ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d, ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update for new stub hashes. * ld-arm/arm-elf.exp: Run them.
2011-03-14include/elf/Richard Sandiford1-0/+5
* internal.h (elf_internal_sym): Add st_target_internal. * arm.h (arm_st_branch_type): New enum. (ARM_SYM_BRANCH_TYPE): New macro. bfd/ * elf-bfd.h (elf_link_hash_entry): Add target_internal. * elf.c (swap_out_syms): Set st_target_internal for each Elf_Internal_Sym. * elfcode.h (elf_swap_symbol_in): Likewise. * elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise. * elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise. * elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elflink.c (elf_link_output_extsym): Likewise. (bfd_elf_final_link): Likewise. (elf_link_add_object_symbols): Copy st_target_internal to the hash table if we see a definition. (_bfd_elf_copy_link_hash_symbol_type): Copy target_internal. * elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with a branch_type field. (a8_erratum_fix, a8_erratum_reloc): Likewise. (arm_type_of_stub): Replace actual_st_type with an actual_branch_type parameter. (arm_build_one_stub): Use branch types rather than st_types to determine the type of branch. (cortex_a8_erratum_scan): Likewise. (elf32_arm_size_stubs): Likewise. (bfd_elf32_arm_process_before_allocation): Likewise. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_sections): Likewise. (elf32_arm_final_link_relocate): Replace sym_flags parameter with a branch_type parameter. (elf32_arm_relocate_section): Update call accordingly. (elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC. (elf32_arm_output_map_sym): Initialize st_target_internal. (elf32_arm_output_stub_sym): Likewise. (elf32_arm_symbol_processing): Delete. (elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs. Use st_target_internal to record the branch type. (elf32_arm_swap_symbol_out): Use st_target_internal to test for Thumb functions. (elf32_arm_is_function_type): Delete. (elf_backend_symbol_processing): Likewise. (elf_backend_is_function_type): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Set the branch type for Thumb symbols. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check eh->target_internal. opcodes/ * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. Use branch types instead. (print_insn): Likewise.
2011-03-11 * remap.c (remap_debug_filename): Always allocate a buffer for theNick Clifton1-0/+7
returned pointer. * stabs.c (stabs_generate_asm_file): Free the pointer returned by remap_debug_filename.
2011-03-102011-03-10 Michael Snyder <msnyder@vmware.com>Michael Snyder1-2/+8
Revert the following change: * dwarf2dbg.c (out_file_list): Free malloced 'dir'. (out_debug_info): Free malloced 'dirname' and 'comp_dir'.
2011-03-10 * gas/config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS,Alan Modra1-0/+6
TARGET_SYMBOL_FIELDS): Don't define. * gas/config/tc-arc.c (arc_common): Use correct symbol "local" field.
2011-03-102011-03-09 Michael Snyder <msnyder@vmware.com>Michael Snyder1-0/+7
* dwarf2dbg.c (out_file_list): Free malloced 'dir'. (out_debug_info): Free malloced 'dirname' and 'comp_dir'. (emit_fixed_inc_line_addr): Assign instead of conditional in assert.
2011-03-06Mention symbol name in non-constant .size expression.H.J. Lu1-0/+5
gas/ 2011-03-05 H.J. Lu <hongjiu.lu@intel.com> * config/obj-elf.c (elf_frob_symbol): Mention symbol name in non-constant .size expression. gas/testsuite/ 2011-03-05 H.J. Lu <hongjiu.lu@intel.com> * gas/elf/bad-size.err: Updated.
2011-03-05Revert the last change.H.J. Lu1-9/+0
2011-03-05Set x86_cie_data_alignment to -4 for x32.H.J. Lu1-0/+9
gas/ 2011-03-04 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (x86_cie_stack_alignment): New. (md_begin): Set x86_cie_data_alignment if it isn't set. Set x86_cie_stack_alignment. (i386_target_format): Set x86_cie_data_alignment to -4 for x32. (tc_x86_frame_initial_instructions): Use x86_cie_stack_alignment instead of x86_cie_data_alignment on SP and RA. gas/testsuite/ 2011-03-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/cfi/cfi-x86_64.d: Updated.
2011-03-02 * ecoff.c: Incldue filenames.hNick Clifton1-0/+4
2011-02-28ChangeLog binutils/Kai Tietz1-0/+13
2011-02-28 Kai Tietz <kai.tietz@onevision.com> * debug.c (debug_start_source): Use filename_(n)cmp. * ieee.c (ieee_finish_compilation_unit): Likewise. (ieee_lineno): Likewise. * nlmconv.c (main): Likewise. * objcopy.c (strip_main): Likewise. (copy_main): Likewise. * objdump.c (show_line): Likewise. (dump_reloc_set): Likewise. * srconv.c (main): Likewise. * wrstabs.c (stab_lineno): Likewise. ChangeLog gas/ 2011-02-28 Kai Tietz <kai.tietz@onevision.com> * depend.c (register_dependency): Use filename_(n)cmp. * dwarf2dbg.c (get_filenum): Likewise. * ecoff.c (add_file): Likewise. (ecoff_generate_asm_lineno): Likewise. * input-scrub.c (new_logical_line_flags): Likewise. * listing.c (file_info): Likewise. (listing_newline): Likewise. * remap.c (remap_debug_filename): Likewise. * stabs.c (generate_asm_file): Likewise. (stabs_generate_asm_lineno): Likewise.
2011-02-28 gas/Maciej W. Rozycki1-0/+5
* config/tc-mips.c (append_insn): Disable branch relaxation for DSP instructions. gas/testsuite/ * gas/mips/relax-bposge.l: New test for DSP branch relaxation. * gas/mips/relax-bposge.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
2011-02-28 gas/Maciej W. Rozycki1-0/+4
* config/tc-mips.c (macro): Handle M_PREF_AB. include/opcode/ * mips.h (M_PREF_AB): New enum value. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
2011-02-28 gas/Maciej W. Rozycki1-0/+15
* config/tc-mips.c (RELAX_BRANCH_ENCODE): Encode the temporary register to use. (RELAX_BRANCH_UNCOND): Adjust accordingly. (RELAX_BRANCH_LIKELY): Likewise. (RELAX_BRANCH_LINK): Likewise. (RELAX_BRANCH_TOOFAR): Likewise. (RELAX_BRANCH_AT): New macro. (append_insn): Encode the temporary register to use in standard MIPS branch relaxation. (relaxed_branch_length): Update according to changes to RELAX_BRANCH_ENCODE. (md_convert_frag): Use the encoded register as the temporary. gas/testsuite/ * gas/mips/relax-at.d: New test for branch relaxation with .set at. * gas/mips/relax.s: Update to support the new test. * gas/mips/relax.l: Update accordingly. * gas/mips/relax.d: Update for multi-arch invocation. * gas/mips/mips.exp: Run the new test. Adjust to run "relax" across all applicable architectures.
2011-02-28 gas/Maciej W. Rozycki1-0/+5
* config/tc-mips.c (mips_fix_adjustable): On REL targets also reject PC-relative relocations. gas/testsuite/ * gas/mips/branch-misc-2.d: Adjust for relocation change. * gas/mips/branch-misc-2pic.d: Likewise. * gas/mips/branch-misc-4.d: New test for PC-relative relocation overflow. * gas/mips/branch-misc-4-64.d: Likewise. * gas/mips/branch-misc-4.s: Source for the new tests. * testsuite/gas/mips/mips.exp: Run the new tests.
2011-02-28 gas/Maciej W. Rozycki1-0/+5
* config/tc-mips.c (md_convert_frag): Correct message capitalization. gas/testsuite/ * gas/mips/relax-swap1.l: Adjust for message capitalization correction. * gas/mips/relax-swap2.l: Likewise. * gas/mips/relax.l: Likewise.
2011-02-28 * symbols.c (report_op_error): Remove unnecessary forward declaration.Alan Modra1-0/+8
Add "op" parameter. Report operator and operand segments in error message, not operand symbols. (resolve_symbol_value): Always set segment for equated symbols, not just when finalizing. Adjust report_op_error calls.
2011-02-25Update ChangeLog entry.H.J. Lu1-2/+2
2011-02-25Don't sign-checking 4-byte relocations for x32.H.J. Lu1-0/+5
gas/ 2011-02-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (reloc): Don't sign-checking 4-byte relocations if 64bit relocations aren't allowed. gas/testsuite/ 2011-02-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/ilp32.exp: Run reloc64. * gas/i386/ilp32/reloc64.s: Allow TLS relocations with 32bit register destinations. * gas/i386/ilp32/reloc64.d: Updated. * gas/i386/ilp32/reloc64.l: New.
2011-02-25 PR gas/12519Alan Modra1-0/+5
* config/obj-elf.c (elf_frob_symbol): Properly handle size expression. * ld-mn10300/i135409-3.s: Correct .size label reference. * ld-sh/sh64/stolib.s: Likewise.
2011-02-21 * config/tc-mips.c (mips_ip) <'o'>: Remove duplicateMaciej W. Rozycki1-0/+5
initialization of offset_reloc.
2011-02-15 * dw2gencfi.c (dot_cfi_dummy): New.Richard Henderson1-0/+6
(cfi_pseudo_table) [!TARGET_USE_CFIPOP]: New. * read.c (pobegin): Unconditionally call cfi_pop_insert.
2011-02-13Remove freebsd1 from libtool.m4 macros and config.rpath.Ralf Wildenhues1-0/+4
/: Import from Libtool and gnulib: 2011-01-27 Gerald Pfeifer <gerald@pfeifer.com> Prepare for supporting FreeBSD 10. * config.rpath: Remove handling of freebsd1* which soon would match FreeBSD 10.0. 2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change) Remove support for FreeBSD 1.x. * libtool.m4 (_LT_LINKER_SHLIBS) (_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which soon would incorrectly match FreeBSD 10.0. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.
2011-02-13gas/opcodes: blackfin: punt BYTEOP2M insn supportMike Frysinger1-0/+6
The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12gas/opcodes: blackfin: move dsp mac func defines to common headerMike Frysinger1-0/+5
The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-11gas: blackfin: docs: typo fixes and fill out directive infoMike Frysinger1-0/+8
A bunch of Blackfin-specific directives were lacking info on what they actually do, so fill in the blanks. Further, the byte2/byte4 descriptions were swapped. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-11gas: blackfin: reject FP/SP with TESTSETMike Frysinger1-0/+4
The TESTSET insn does not work with the FP/SP Pregs, so reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-10 * doc/c-ppc.texi (PowerPC-Opts <-nops>): Clarify.Alan Modra1-0/+4
2011-02-10 * doc/as.texinfo (Overview): Add missing markup around BlackfinAlan Modra1-0/+5
and PowerPC options.
2011-02-10 * config/tc-ppc.c (md_show_usage): Remove -l and -b. Add -K PIC.Alan Modra1-0/+7
* doc/as.texinfo: Refer to and include c-ppc.texi for PowerPC options. (Overview <Target PowerPC options>): Add a number of missing options. * doc/c-ppc.texi: Likewise. Add markup for use in manpage generation.
2011-02-08Use f32_patt in i386_align_code when tuning for i686.H.J. Lu1-0/+6
gas/ 2011-02-08 H.J. Lu <hongjiu.lu@intel.com> PR gas/6957 * config/tc-i386.c (i386_align_code): Use f32_patt when tuning for i686. gas/testsuite/ 2011-02-08 H.J. Lu <hongjiu.lu@intel.com> PR gas/6957 * gas/i386/nops-1-i686.d: Updated. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4-i686.d: Likewise.
2011-02-08Also update cpu_arch_isa_flags for ISA extensions.H.J. Lu1-0/+6
gas/ 2011-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_cpu_arch): Also update cpu_arch_isa_flags for ISA extensions. (md_parse_option): Likewise. gas/testsuite/ 2011-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops-4a-i686 and nops-6. * gas/i386/nops-4a-i686.d: New. * gas/i386/nops-6.d: Likewise. * gas/i386/nops-6.s: Likewise.
2011-02-03 gas/Bernd Schmidt1-0/+16
* doc/as.texinfo (Target TIC6X options): Don't mention "-matomic". * doc/c-tic6x.texi (TIC6X Directives): Don't mention ".atomic". (TIC6X Options): Don't mention "-matomic". * config/tc-tic6x.c (OPTION_MATOMIC, OPTION_MNO_ATOMIC): Delete. (md_longopts): Remove corresponding entries. (md_parse_option): Don't handle them. (md_show_usage): Don't document them. (tic6x_atomic): Delete variable. (tic6x_update_features): Always copy tic6x_arch_enable to tic6x_features. (tic6x_arch_enable): Remove references to TIC6X_INSN_ATOMIC. (s_tic6x_atomic, s_tic6x_noatomic): Remove functions. (md_pseudo_table): Remove ".atomic" and ".noatomic". gas/testsuite/ * gas/tic6x/dir-junk.l: Remove tests for .atomic and .noatomic. * gas/tic6x/dir-junk.s: Likewise. * gas/tic6x/insns-c674x-bad.d: Remove test. * gas/tic6x/insns-c674x-bad.l: Likewise. * gas/tic6x/insns-atomic.d: Remove "-matomic" switch. include/opcode/ * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
2011-01-31 * write.c (write_contents): Include output file name and bfd errorNick Clifton1-0/+7
value when reporting the inability to write to the output file. * config/tc-rx.c (rx_handle_align): Do not insert NOPs into align frag that has a non-zero fill value. * gas/all/align.d: Skip for the RX. * gas/elf/group1a.d: Likewise. * gas/elf/groupautoa.d: Likewise. * gas/elf/elf.exp: Do not run section5 test for the RX port. * gas/elf/section4.d: Likewise. * gas/elf/section7.d: Likewise. * gas/macros/semi.s: Fill with a non-zero pattern. * gas/macros/semi.d: Expect non-zero fill value. * gas/rx/bcnd.d: Update expected disassembly. * gas/rx/bra.d: Likewise. * gas/rx/macros.inc: Add reg1 macro. * gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP instruction. * gas/rx/mov.sm: Likewise. * gas/rx/max.d: Update expected disassembly. * gas/rx/mov.d: Likewise. * gas/rx/rx-asm-good.s: Use Renesas section names. * gas/rx/rx-asm-good.d: Update expected disassembly.
2011-01-27* config/tc-rx.c (md_convert_frag): If we can't compute the targetDJ Delorie1-0/+6
address, zero out the values stored in the object file to make objdump's output consistent.
2011-01-262011-01-26 Kai Tietz <kai.tietz@onevision.com>Kai Tietz1-0/+5
* config/tc-i386.c (md_begin): Set for x64 windows COFF target x86_dwarf2_return_column to 32.
2011-01-20 PR gas/12384Nick Clifton1-0/+6
* config/tc-h8300.c (constant_fits_width_p): Use correct type for comparison.
generated by cgit v1.1 at 2025-01-08 07:02:02 +0000