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2018-01-13Update pot filesNick Clifton1-0/+4
2018-01-13Bump version number to 2.30.51Nick Clifton1-0/+4
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+1
2018-01-13Add 2.30 markers to NEWS files.Nick Clifton1-0/+4
2018-01-12Fix compile time warning building aout targeted architectures.Gunther Nikl1-0/+6
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-0/+20
2018-01-11gas tc-arm.c warning fixAlan Modra1-0/+5
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-0/+18
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-0/+10
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-0/+5
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh1-0/+10
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-0/+5
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-0/+9
2018-01-08Add a description of the X86_64 assembler's .largcomm pseudo-op.Nick Clifton1-0/+6
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson1-0/+5
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2018-01-03ChangeLog rotationAlan Modra1-4407/+2
2018-01-02Fix typo in do_mrs function in ARM assembler.Nick Clifton1-0/+6
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson1-0/+4
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-0/+15
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+6
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+8
2017-12-18Resolve PR 22493 - the encoding to be used when pushing the stack pointer ont...Nick Clifton1-0/+6
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-0/+9
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-0/+18
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-0/+10
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-0/+20
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu1-0/+9
2017-12-15x86: correct operand type checksJan Beulich1-0/+5
2017-12-15x86: correct abort checkJan Beulich1-0/+5
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton1-0/+10
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson1-0/+5
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov1-0/+6
2017-12-12Don't mask X_add_number containing a register numberAlan Modra1-0/+5
2017-12-08gas: xtensa: fix comparison of trampoline chain symbolsMax Filippov1-0/+6
2017-12-04Documentation fixAlan Modra1-0/+5
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra1-0/+21
2017-12-03Fix for texinfo 4.8.Jim Wilson1-0/+5
2017-12-01Update and clean up RISC-V gas documentation.Jim Wilson1-0/+11
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner1-0/+12
2017-11-30x86: drop Vec_Disp8Jan Beulich1-0/+12
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich1-0/+12
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich1-13/+0
2017-11-29Give Palmer co-credit for last patch.Jim Wilson1-0/+1
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson1-0/+7
2017-11-29In x86 -n docs, mention that you need an explicit nop fill byte.Jim Wilson1-0/+5
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li1-0/+6
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe1-0/+6
2017-11-29Use the record_alignment function when creating a .note section, in case the ...Nick Clifton1-1/+6
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson1-0/+13