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The logic is same as a71d87680110 ("aarch64: Add DT_RELR support").
As LoongArch does not have -z dynamic-undefined-weak, we don't need to
consider UNDEFWEAK_NO_DYNAMIC_RELOC.
The linker relaxation adds another layer of complexity. When we delete
bytes in a section during relaxation, we need to fix up the offset in
the to-be-packed relative relocations against this section.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols
as preemptible. See the comment above LARCH_REF_LOCAL for detailed
explanation.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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With a simple test case:
.globl ifunc
.globl ifunc_hidden
.hidden ifunc_hidden
.type ifunc, %gnu_indirect_function
.type ifunc_hidden, %gnu_indirect_function
.text
.align 2
ifunc: ret
ifunc_hidden: ret
test:
bl ifunc
bl ifunc_hidden
"ld -shared" produces a shared object with one R_LARCH_NONE (instead of
R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc".
It's because the indices in .plt and .rela.plt mismatches for
STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a
STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of
loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt
so the indices no longer mismatch.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64:
$ cat t.s
.data
x:
.4byte x
.4byte 0xdeadbeef
$ as/as-new t.s -o t.o
$ ld/ld-new -shared t.o
$ objdump -R
a.out: file format elf64-loongarch
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8
But this is just wrong: at runtime the dynamic linker will run
*(uintptr *)&x += load_address, clobbering the next 4 bytes of data
("0xdeadbeef" in the example).
If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected
by the Glibc dynamic linker anyway. And it does not make too much sense
to modify Glibc to support it. So we can just reject it like x86_64:
relocation R_X86_64_32 against `.data' can not be used when making a
shared object; recompile with -fPIC
or RISC-V:
relocation R_RISCV_32 against non-absolute symbol `a local symbol'
can not be used in RV64 when making a shared object
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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It's that tiny bit nicer to have the "len" expression in order of
the components in the buffer.
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Some more error tweaks. Report a zero entry as "invalid entry.."
rather than "unknown type..", and allow a section to be mentioned
twice in a group.
* elf.c (process_sht_group_entries): Tweak error messages, and
allow a duplicate index in a group without reporting an error.
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old object files
R_LARCH_SOP_PUSH_ABSOLUTE with -fPIC was heavily used in the era of gas-2.38.
We do not check this relocation to prevent broken links with old object
files.
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Allow to add implicit extensions by using the syntax of `.option arch, +-', so
that the table is shrinked and more readable.
bfd/
* elfxx-riscv.c (check_implicit_always): Removed the unused IMPLICIT
parameter.
(check_implicit_for_i): Likewise.
(riscv_implicit_subsets): Shrink the table by allowing the syntax of
`.option arch, +-' for implicit extensions.
(riscv_update_subset1): New function, called from riscv_update_subset
or riscv_parse_add_implicit_subsets. It basically does the same thing
as riscv_update_subset function before.
(riscv_parse_add_implicit_subsets): Updated.
(riscv_update_subset): Updated.
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When pcrel access overflow, the riscv_zero_pcrel_hi_reloc may convert pcrel
relocation to absolutly access if possible at the relocate stage. We used to
encode the target address into r_sym of R_RISCV_HI20 if it is converted from
R_RISCV_PCREL_HI20. But that may cause segfault if --emit-relocs is set,
since r_sym becomes an address rather than a symbol index. Although the
relocate result is correct, it does not meet the definition, so may cause
unexpected behaviors.
This patch encodes the target address into r_addend, rather than r_sym, if
riscv_zero_pcrel_hi_reloc converts the relocation. Besdies, since the
corresponding pcrel_lo relocation are also changed to absolutly access,
we should also update them to R_RISCV_LO12_I/S.
bfd/
PR 27180
* elfnn-riscv.c (riscv_pcrel_hi_reloc): New boolean `absolute', to
inform corresponding pcrel_lo that the pcrel_hi relocation was already
converted to hi20 relocation.
(riscv_record_pcrel_hi_reloc): Likewise, record `absolute'.
(riscv_pcrel_lo_reloc): Removed `const' for Elf_Internal_Rela *reloc,
since we may need to convert it from pcrel_lo to lo relocation.
(riscv_record_pcrel_lo_reloc): Likewise. Convert pcrel_lo to lo
relocation if corresponding pcrel_hi was converted to hi relocation.
(riscv_zero_pcrel_hi_reloc): Encode target absolute address into
r_addend rather than r_sym. Clear the `addr' to avoid duplicate
relocate in the perform_relocation.
(riscv_elf_relocate_section): Updated.
ld/
PR 27180
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a-emit-relocs.d: New testcase.
Segfault without applying this patch.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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This patch update the cas instruction in Zabha extension [1],
when both Zabha and Zacas extension enabled.
[1] https://github.com/riscv/riscv-zabha/tags
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension case.
gas/ChangeLog:
* testsuite/gas/riscv/zabha-32.d: New instructions.
* testsuite/gas/riscv/zabha.d: Ditto.
* testsuite/gas/riscv/zabha.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes.
(MASK_AMOCAS_B): Ditto.
(MATCH_AMOCAS_H): Ditto.
(MASK_AMOCAS_H): Ditto.
(DECLARE_INSN): New instructions.
* opcode/riscv.h (enum riscv_insn_class): New class case.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
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There is no need to loop over the headers twice. Remove that leftover
from the previous scheme. Also, the previous scheme silently ignored
a section being mentioned in two or more SHT_GROUP sections.
* elf.c (process_sht_group_entries): Prevent sections from
belonging to two groups.
(_bfd_elf_setup_sections): Process groups in a single loop
over headers.
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This patch delays setting up elf_next_in_group, elf_sec_group and
elf_group_name when reading ELF object files until after all ELF
sections have been processed by bfd_section_from_shdr. This is simpler
and more robust than the current scheme of driving the whole process
on detecting a section with SHF_GROUP set.
* elf-bfd.h (struct elf_obj_tdata): Delete group_sect_ptr,
num_group and group_search_offset.
* elf.c (Elf_Internal_Group): Delete.
(setup_group): Delete function.
(IS_VALID_GROUP_SECTION_HEADER): Delete macro.
(is_valid_group_section_header),
(process_sht_group_entries): New functions.
(_bfd_elf_setup_sections): Handle group sections here..
(_bfd_elf_make_section_from_shdr): ..rather than here.
(bfd_section_from_shdr): Don't check SHT_GROUP validity here.
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DST__K_RECBEG type debug symbol for the VMS Alpha port.
PR 31873
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Extend the 64bit DT_RELR support to work on 32bit ELF too. For this
only a few changes were needed in the sizing and creation of the
relr relocations.
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Accroding to the Crypto spec, the Zvkned,Zvknhb,Zvkb and Zvkt are
included in the Zvkn. So the Zvknha should be removed from Zvkn.
bfd/ChangeLog:
* elfxx-riscv.c: Remove zvknha from zvkn.
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This reverts commit e874cbd3879843a83e4bcc4b54cd7107387b1df6.
The patch was wrong. LIBINTL_DEP is needed with an in-tree gettext.
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The intl directory in the source no longer exists. LIBINTL_DEP is
thus always empty. Remove references to it.
config/
* gettext-sister.m4: Don't AC_SUBST LIBINTL_DEP.
bfd/
* Makefile.in: Regenerate.
* configure: Regenerate.
binutils/
* Makefile.am (*_DEPENDENCIES): Remove LIBINTL_DEP.
* Makefile.in: Regenerate.
* configure: Regenerate.
gas/
* Makefile.am (as_new_DEPENDENCIES): Remove LIBINTL_DEP.
* Makefile.in: Regenerate.
* configure: Regenerate.
gdb/
* Makefile.in (INTL_DEPS): Don't set or reference.
* configure: Regenerate.
gdbserver/
* Makefile.in (INTL_DEPS): Don't set or reference.
gdbsupport/
* Makefile.in: Regenerate.
* configure: Regenerate.
gold/
* Makefile.am (deps_var): Remove LIBINTL_DEP.
(incremental_dump_DEPENDENCIES, dwp_DEPENDENCIES): Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* testsuite/Makefile.am (DEPENDENCIES): Remove LIBINTL_DEP.
* testsuite/Makefile.in: Regenerate.
gprof/
* Makefile.am (gprof_DEPENDENCIES): Remove LIBINTL_DEP.
* Makefile.in: Regenerate.
* configure: Regenerate.
ld/
* Makefile.am (ld_new_DEPENDENCIES): Remove LIBINTL_DEP.
* Makefile.in: Regenerate.
* configure: Regenerate.
libctf/
* Makefile.in: Regenerate.
* configure: Regenerate.
opcodes/
* configure.ac (BUILD_LIBS): Remove LIBINTL.
(BUILD_LIB_DEPS): Remove LIBINTL_DEP.
* Makefile.in: Regenerate.
* configure: Regenerate.
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As the comment in the code says, TLS_IE needs only one dynamic reloc.
But commit b67a17aa7c0c ("LoongArch: Fix the issue of excessive
relocation generated by GD and IE") has incorrectly allocated the space
for two dynamic relocs, causing libc.so to contain 8 R_LARCH_NONE.
Adjust tlsdesc-dso.d for the offset changes and add two tests to ensure
there are no R_LARCH_NONE with TLS.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Fixed type from smscrind to
smcsrind.
gas/
* testsuite/gas/riscv/march-imply-smcsrind.d: New testcase. It fails
without applying this patch.
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Add SiFive cease extension,
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
This aligns LLVM:
* https://llvm.org/docs/RISCVUsage.html
* https://github.com/llvm/llvm-project/pull/83896
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for
'xsfcease'.
(riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
(riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.
gas/ChangeLog:
* doc/c-riscv.texi: Updated.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
* testsuite/gas/riscv/sifive-insns.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and
mask encoding for 'sf.cease'.
* opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for
'xsfcease'.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
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https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0
The Zacas extension introduce compare-and-swap instructions to operate
on 32-bit, 64-bit and 128-bit (RV64 only) data values.
It introduces three new instructions:
- amocas.w (32-bit CAS)
- amocas.d (64-bit CAS)
- amocas.q (128-bit CAS, RV64 only)
Like other AMOs in the A extension, Zacas instructions have '.aq',
'.rl' and '.aqrl' variations.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'.
(riscv_supported_std_z_ext): Add 'Zacas' extension.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext):
Handle INSN_CLASS_ZACAS case.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zacas-32.d: New test (RV32).
* testsuite/gas/riscv/zacas-fail-32.d: Likewise.
* testsuite/gas/riscv/zacas-64.d: New test (RV64).
* testsuite/gas/riscv/zacas-fail-64.d: Likewise.
* testsuite/gas/riscv/zacas.s: New test source.
* testsuite/gas/riscv/zacas-fail.s: Likewise.
* testsuite/gas/riscv/zacas-fail-32.l: New file.
* testsuite/gas/riscv/zacas-fail-64.l: Likewise.
include/ChangeLog:
* include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition.
* include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W)
(MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q):
Likewise.
(amocas_w, amocas_d, amocas_q): Declare instructions.
opcodes/ChangeLog:
* riscv-opc.c (match_rs2_rd_even): New function.
(amocas_w, amocas_d, amocas_q, amocas_w.aq)
(amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl)
(amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
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Error/warning messages are only printed for the target that
successfully matched, which makes sense for warnings, but not so much
for errors where the errors cause no target to match. I noticed this
when looking at the pr20520 testcase again with objdump, which just
reports "file format not recognized" omitting the five "SHT_GROUP
section [index n] has no SHF_GROUP sections" messages. They are
omitted because multiple ELF targets match the object file. This is
going to be true for all ELF objects due to at least the proper ELF
target and the generic ELF target matching.
* format.c (print_and_clear_messages): Print messages if all
targets with messages have exactly the same set of messages.
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Add -z isa-level-report=[none|all|needed|used] to the x86 ELF linker to
report needed and used x86-64 ISA levels.
bfd/
PR ld/31868
* elf-linker-x86.h (elf_x86_isa_level_report): New.
(elf_linker_x86_params): Add isa_level_report.
* elfxx-x86.c (report_isa_level): New.
(_bfd_x86_elf_link_setup_gnu_properties): Check
-z isa-level-report=[none|all|needed|used] to report needed and
used x86-64 ISA level.
ld/
PR ld/31868
* NEWS: Mention -z isa-level-report=[none|all|needed|used].
* ld.texi: Document -z isa-level-report=[none|all|needed|used].
* emulparams/elf32_x86_64.sh: Source x86-64-level-report.sh.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Likewise.
* emulparams/x86-64-level-report.sh: New file.
* testsuite/ld-i386/pr31868a.d: Likewise.
* testsuite/ld-i386/pr31868b.d: Likewise.
* testsuite/ld-i386/pr31868c.d: Likewise.
* testsuite/ld-x86-64/pr31868a-x32.d: Likewise.
* testsuite/ld-x86-64/pr31868a.d: Likewise.
* testsuite/ld-x86-64/pr31868a.l: Likewise.
* testsuite/ld-x86-64/pr31868a.s: Likewise.
* testsuite/ld-x86-64/pr31868b-x32.d: Likewise.
* testsuite/ld-x86-64/pr31868b.d: Likewise.
* testsuite/ld-x86-64/pr31868b.l: Likewise.
* testsuite/ld-x86-64/pr31868b.s: Likewise.
* testsuite/ld-x86-64/pr31868c-x32.d: Likewise.
* testsuite/ld-x86-64/pr31868c.d: Likewise.
* testsuite/ld-x86-64/pr31868c.l: Likewise.
* testsuite/ld-i386/i386.exp: Run PR ld/31868 tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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generating two read-only segments.
PR 30907
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