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2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang5-6/+42
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
2023-12-18Automatic date update in version.inGDB Administrator1-1/+1
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2023-12-15Fix segmentation fault in bfd/elf32-hppa.cJohn David Anglin1-1/+3
2023-12-15 John David Anglin <danglin@gcc.gnu.org> PR ld/31148 bfd/ChangeLog: * elf32-hppa.c (elf32_hppa_finish_dynamic_symbol): Output relative reloc only when eh->root.type is bfd_link_hash_defined or bfd_link_hash_defweak.
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+1
Hi, This patch adds support for the Cortex-X3 CPU to binutils. Gas regression testing for aarch64-none-linux-gnu target and found no regressions. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu.
2023-12-15PR31145, potential memory leak in binutils/ldAlan Modra4-6/+14
PR 31145 * bfd.c (BFD_IN_MEMORY): Mention that bim is malloc'd. * format.c (io_reinit): Free BFD_IN_MEMORY iostream. * opncls.c (_bfd_delete_bfd): Likewise. (bfd_make_readable): Delete unnecessary code. * bfd-in2.h: Regenerate.
2023-12-15RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'Xiao Zeng1-0/+4
This commit adds support for ratified extensions: 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'. This is based on: <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf> bfd/ChangeLog: * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'. (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
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2023-12-11bfd_find_nearest_line leaks dwarf_rnglists_bufferKonstantin Isakov1-0/+1
* dwarf2.c (_bfd_dwarf2_cleanup_debug_info): Free dwarf_rnglists_buffer.
2023-12-11regen bfd POTFILESAlan Modra2-0/+2
2023-12-11R_MICROMIPS_GPREL7_S2Alan Modra1-19/+24
This reloc is meant for the 16-bit LWGP instruction, 0x6400/0xfc00 match/mask encoding in `micromips_opcodes'. It is correctly specified to operate on a half-word by the howtos in elf32-mips.c, elfn32-mips.c and elf64-mips.c, but is incorrectly subject to shuffle/unshuffle in code like _bfd_mips_elf32_gprel16_reloc. Current behaviour when applying the reloc to .byte 0x11,0x22,0x33,0x44 is to apply the reloc to byte 0x22 when big-endian, and to byte 0x33 when little-endian. Big-endian behaviour is unchanged after this patch and little-endian correctly applies the reloc to byte 0x11. The patch also corrects REL addend extraction from section contents, and overflow checking. gold had all of the bfd problems with this reloc and additionally did not apply the rightshift by two. bfd/ * elfxx-mips.c (micromips_reloc_shuffle_p): Return false for R_MICROMIPS_GPREL7_S2. (mips_elf_calculate_relocation): Correct sign extension and overflow calculation for R_MICROMIPS_GPREL7_S2. (_bfd_mips_elf_relocate_section): Update small-data overflow message. gold/ * mips.cc (Mips_relocate_functions::should_shuffle_micromips_reloc): Return false for R_MICROMIPS_GPREL7_S2. (Mips_relocate_functions::mips_reloc_unshuffle): Update comment. (Mips_relocate_functions::relgprel): Remove R_MICROMIPS_GPREL7_S2 handling. (Mips_relocate_functions::relgprel7): New function. (Target_mips::Relocate::relocate): Adjust to suit. ld/ * testsuite/ld-mips-elf/reloc-4.d: Adjust expected error. * testsuite/ld-mips-elf/reloc-5.d: Likewise.
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2023-12-07RISC-V: Fix "withand" in LEB128 error messagesPalmer Dabbelt1-2/+2
This was split over multiple lines and ended up missing a space. Reported-by: David Abdurachmanov <davidlt@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-07Automatic date update in version.inGDB Administrator1-1/+1
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2023-12-05Fix: strip --strip-debug breaks relocationsNick Clifton2-1/+14
PR 31106 * elfcode.h (elf_write_relocs): Do not convert a relocation against a zero-value absolute symbol into a relocation without a symbol if the symbol is being used for a complex relocation.
2023-12-05Add basic support for RISC-V 64-bit EFI objectsAndreas Schwab14-30/+329
This adds a new PEI target pei-riscv64-little. Only objdump and objcopy are supported. bfd: * .gitignore: Add pe-riscv64igen.c. * Makefile.am (BFD64_BACKENDS): Add pei-riscv64.lo, pe-riscv64igen.lo. (BFD64_BACKENDS_CFILES): Add pei-riscv64.c. (BUILD_CFILES): Add pe-riscv64igen.c. (pe-riscv64igen.c): New rule. * Makefile.in: Regenerate. * bfd.c (bfd_get_sign_extend_vma): Add pei-riscv64-little. * coff-riscv64.c: New file. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags) (coff_write_object_contents): Add riscv64 (riscv64_pei_vec) support. * config.bfd (targ_selvecs): Add riscv64_pei_vec to all riscv* targets. * configure.ac: Handle riscv64_pei_vec. * configure: Regenerate. * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE) (GET_OPTHDR_SIZE_OF_STACK_RESERVE) (PUT_OPTHDR_SIZE_OF_STACK_RESERVE) (GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT) (GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE) (GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT) (GET_PDATA_ENTRY, _bfd_XX_bfd_copy_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XX_get_symbol_info, _bfd_XX_only_swap_filehdr_out) (_bfd_XX_print_private_bfd_data_common) (_bfd_XXi_final_link_postscript, _bfd_XXi_only_swap_filehdr_out) (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out) (_bfd_XXi_swap_lineno_in, _bfd_XXi_swap_lineno_out) (_bfd_XXi_swap_scnhdr_out, _bfd_XXi_swap_sym_in) (_bfd_XXi_swap_sym_out, _bfd_XXi_swap_debugdir_in) (_bfd_XXi_swap_debugdir_out, _bfd_XXi_write_codeview_record) (_bfd_XXi_slurp_codeview_record) [COFF_WITH_peRiscV64]: Define. (_bfd_peRiscV64_print_ce_compressed_pdata): Declare. * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_scnhdr_out, pe_print_pdata) (_bfd_XX_print_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XXi_final_link_postscript): Support COFF_WITH_peRiscV64. * pei-riscv64.c: New file. * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd) (pe_ILF_object_p): Support COFF_WITH_peRiscV64. (jtab): Add dummy entry that traps. * targets.c (_bfd_target_vector): Add riscv64_pei_vec. binutils: * testsuite/binutils-all/riscv/pei-riscv64.d: New. * testsuite/binutils-all/riscv/pei-riscv64.s: New. include: * coff/riscv64.h: New file. * coff/pe.h (IMAGE_FILE_MACHINE_RISCV32) (IMAGE_FILE_MACHINE_RISCV64): Define.
2023-12-05alpha_ecoff_get_relocated_section_contents buffer overflowAlan Modra1-238/+242
This is aimed at fixing holes in two alpha-ecoff relocation functions that access section contents without first bounds checking offsets. I've also rewritten ALPHA_R_OP_STORE handling to support writing to the bytes near the end of the section. * coff-alpha.c (alpha_ecoff_get_relocated_section_contents): Don't bother checking ALPHA_R_LITERAL insn. Range check before reading contents for ALPHA_R_GPDISP, and simplify handling. Rewrite ALPHA_R_OP_STORE handling. Correct error callback args. (alpha_relocate_section): Similarly. Don't abort, report errors.
2023-12-05Don't use free_contents in _bfd_elf_slurp_version_tablesAlan Modra1-6/+4
In commit 7ac6d0c38c36 I made more use of free_contents in _bfd_elf_slurp_version_tables, a variable added to tag the case where raw verneed and verdefs have been read locally by the function, and thus should be freed before returning. In retrospect it may have been better to do without the extra variable entirely. It's easy to infer when "contents" should be freed, costing a little extra on an error path but costing less elsewhere. * elf.c (_bfd_elf_slurp_version_tables): Don't use free_contents.
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2023-12-01RISC-V: Make riscv_is_mapping_symbol stricterPatrick O'Neill1-2/+3
riscv_is_mapping_symbol currently accepts any symbol that starts with $x or $d. This patch makes the check more strict, requiring exactly $x, $d, or $xrv. It also makes use of this stricter mapping in riscv_is_valid_mapping_symbol. ChangeLog: * bfd/cpu-riscv.c (riscv_elf_is_mapping_symbols): Match only strings that are exactly $x, $d, or $xrv. * opcodes/riscv-dis.c (riscv_is_valid_mapping_symbol): Use riscv_elf_is_mapping_symbols. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+5
SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner1-2/+8
Back then when the support for the RISC-V vector crypto extensions was merged, the specification was frozen, but not ratified. A frozen specification is allowed to change within tight bounds before ratification and this has happend with the vector crypto extensions. The following changes were applied: * A new extension Zvkb was defined, which is a strict subset of Zvbb. * Zvkn and Zvks include now Zvkb instead of Zvbb. This patch implements these changes between the frozen and the ratified specification. Note, that this technically an incompatible change of Zvkn and Zvks, but I am not aware of any project that depends on the currently implemented behaviour of Zvkn and Zvks. So this patch should be fine. Reported-By: Jerry Shih <jerry.shih@sifive.com> Reported-By: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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2023-11-30MIPS: Set r6 as default arch if vendor is imgYunQiang Su1-1/+1
This behavior is used by downstream toolchain since 2014, and has been in GCC since the same year. We don't support mips64*-img* due to GCC doesn't support it, and we believe that the multilib should be used for this case.
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2023-11-24RISC-V: Update 'Zfa' extension versionzengxiao1-1/+1
Because the 'Zfa' extension has a version number of 1.0 (not 0.1). This commit updates the number. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Update the version number of the 'Zfa' extension since it's ratified.
2023-11-24Automatic date update in version.inGDB Administrator1-1/+1
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvamo" for the "XTheadVector" extension, and it provides AMO instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvamo" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-zvamo.d: New test. * testsuite/gas/riscv/x-thead-vector-zvamo.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+12
T-Head has a range of vendor-specific instructions ([2]). Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 [2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class):
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2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai1-3/+0
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2023-11-21Fix: symbols eliminated by --gc-sections still trigger warnings for ↵Nick Clifton2-0/+15
gnu.warning.SYM PR 31067 * linker.c (_bfd_generic_link_add_one_symbol): When issuing a warning message, also display a message about the warning not being affected by garbage colleciton. * ld.texi (Special Sections): New entry in the linker manual. Describes how the .gnu.warning and .gnu.warning.SYM sections behave.
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