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2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-23RISC-V: Relax the order checking for the architecture stringNelson Chu1-135/+75
* riscv-toolchain-conventions, PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11 * Refer to the commit afc41ffb, RISC-V: Reorder the prefixed extensions which are out of order. In the past we only allow to reorder the prefixed extensions. But according to the PR 14 in the riscv-toolchain-convention, we can also relax the order checking to allow the whole extensions be written out of orders, including the single standard extensions and the prefixed multi-letter extensions. Just that we still need to follow the following rules as usual, 1. prefixed extensions need to be seperated with `_'. 2. prefixed extensions need complete <major>.<minor> version if set. Please see the details in the march-ok-reorder gas testcase. Passed the riscv-gnu-toolchain regressions. bfd/ * elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN to RV_ISA_CLASS_SINGLE, since everything that does not belong to the multi-keyword will possible be a single extension for the current parser. (parse_config): Likewise. (riscv_get_prefix_class): Likewise. (riscv_compare_subsets): Likewise. (riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext into riscv_parse_extensions. (riscv_parse_prefixed_ext): Likewise. (riscv_parse_subset): Only need to call riscv_parse_extensions to parse both single standard and prefixed extensions. gas/ * testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed order checking. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-z-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-ok-reorder.d: New testcase.
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner1-0/+4
This commit adds the AIA extensions (Smaia and Ssaia) CSRs. bfd/ChangeLog: * elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list of known standard extensions. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): (riscv_csr_address): Add CSR classes for Smaia/Ssaia. * testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MISELECT): New CSR macro. (CSR_MIREG): Likewise. (CSR_MTOPEI): Likewise. (CSR_MTOPI): Likewise. (CSR_MVIEN): Likewise. (CSR_MVIP): Likewise. (CSR_MIDELEGH): Likewise. (CSR_MIEH): Likewise. (CSR_MVIENH): Likewise. (CSR_MVIPH): Likewise. (CSR_MIPH): Likewise. (CSR_SISELECT): Likewise. (CSR_SIREG): Likewise. (CSR_STOPEI): Likewise. (CSR_STOPI): Likewise. (CSR_SIEH): Likewise. (CSR_SIPH): Likewise. (CSR_HVIEN): Likewise. (CSR_HVICTL): Likewise. (CSR_HVIPRIO1): Likewise. (CSR_HVIPRIO2): Likewise. (CSR_VSISELECT): Likewise. (CSR_VSIREG): Likewise. (CSR_VSTOPEI): Likewise. (CSR_VSTOPI): Likewise. (CSR_HIDELEGH): Likewise. (CSR_HVIENH): Likewise. (CSR_HVIPH): Likewise. (CSR_HVIPRIO1H): Likewise. (CSR_HVIPRIO2H): Likewise. (CSR_VSIEH): Likewise. (CSR_VSIPH): Likewise. (DECLARE_CSR): Add CSRs for Smaia and Ssaia. Changes for v3: - Imply ssaia for smaia - Imply zicsr for ssaia (and transitively smaia) - Move hypervisor CSRs to Ssaia+H - Rebase on upstream/master Changes for v2: - Add hypervisor and VS CSRs - Fix whitespace issue Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-23RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standardXiao Zeng1-0/+4
According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant bits are valid, but since binutils implementation, we usually get 8 bits field for it. That means, the high 2 bits could be other field and have different purpose. Therefore, we should filter the 8 bits to 6 bits before calculate, and then only encode the valid 6 bits back. By the way, we also need the out-of-range check for R_RISCV_SUB6, and the overflow checks for all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches. Passing riscv-gnu-toolchain regressions. bfd/ChangeLog: * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6 lower 6 bits as the significant bit. * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI1-1/+3
This commit adds 'Ssstateen' extension, which is a supervisor-visible view of the 'Smstateen' extension. It means, this extension implements sstateen* and hstateen* CSRs of the 'Smstateen' extension. Note that 'Smstateen' extension itself is unchanged but due to implementation simplicity, it is implemented so that 'Smstateen' implies 'Ssstateen' (just like 'M' implies 'Zmmul'). This is based on the latest version of RISC-V Profiles (version 0.9-draft, Frozen): <https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Update implication rules. (riscv_supported_std_s_ext) Add 'Ssstateen' extension. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Rename CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_... Add CSR_CLASS_SSSTATEEN. (riscv_csr_address): Support new/renamed CSR classes. * testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment. * testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to error messages. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that supervisor/hypervisor part of 'Smstateen' CSRs are accessible from 'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested in ssstateen-csr.d. include/ChangeLog: * opcode/riscv-opc.h: Update DECLARE_CSR declarations with new CSR classes.
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner1-0/+5
This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner1-0/+5
This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-07RISC-V: Remove RV32EF conflictTsukasa OI1-7/+0
Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later versions beginning with the version 20190608-Base-Ratified removed this restriction. Because the 'E' extension is still a draft, the author chose to *just* remove the conflict (not checking the ISA version). Note that, because RV32E is only used with a soft-float calling convention, there's no valid official ABI for RV32EF. It means, even if we can assemble a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept in an unmanaged state (outside ABI management). The purpose of this commit is to suppress unnecessary errors while parsing an ISA string and/or disassembling, not to allow hard-float with RVE. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF because only older specifications disallowed it. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly prohibited. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+7
RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
2022-10-14RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()Jan Beulich1-0/+6
The lack thereof did caused gas to issue "internal: unreachable INSN_CLASS_*" errors when trying to assemble respective insns without the feature(s) enabled via e.g. ".option arch, ...". Of course a proper hint towards the missing extension then wasn't given either.
2022-10-14RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI1-0/+5
'H', 'Smstateen', 'Sscofpmf' and 'Sstc' are four privileged extensions with their CSR definitions and 'Smepmp' is a privileged extension with additional CSR bits. Volume II: Privileged Architecture of the RISC-V ISA Manual states that the privileged architecture requires the 'Zicsr' extension. However, current GNU Binutils has no direct way whether the program has dependency to the privileged architecture itself. As a workaround, we should add implications from privileged extensions that either add new CSRs, extend existing CSRs or depends on using CSRs. This commit adds such implications for existing privileged extensions that satisfy this condition. gas/ChangeLog: * testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications for privileged extensions 'H', 'Smstateen', 'Sscofpmf', 'Sstc' and 'Smepmp'.
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-15/+14
Just added suffix _INX for those INSN_CLASS should be enough to represent their fpr can be replaced by gpr.
2022-09-30RISC-V: Add privileged extensions without instructions/CSRsTsukasa OI1-0/+3
Currently, GNU Binutils does not support following privileged extensions: - 'Smepmp' - 'Svnapot' - 'Svpbmt' as they do not provide new CSRs or new instructions ('Smepmp' extends the privileged architecture CSRs but does not define the CSR itself). However, adding them might be useful as we no longer have to "filter" ISA strings just for toolchains (if full ISA string is given by a vendor, we can straightly use it). And there's a fact that supports this theory: there's already an (unprivileged) extension which does not provide CSRs or instructions (but only an architectural guarantee): 'Zkt' (constant timing guarantee for certain subset of RISC-V instructions). This simple commit simply adds three privileged extensions listed above. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smepmp', 'Svnapot' and 'Svpbmt' extensions.
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+5
This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemPair extension, a collection of T-Head specific two-GP-register memory operations. The 'th' prefix and the "XTheadMemPair" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemIdx extension, a collection of T-Head specific GPR memory access instructions. The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 44 instructions (BU,HU,WU only for loads (zero-extend instead of sign-extend)): * {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2 * {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 * {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMac extension, a collection of T-Head-specific multiply-accumulate instructions. The 'th' prefix and the "XTheadMac" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCondMov extension, a collection of T-Head-specific conditional move instructions. The 'th' prefix and the "XTheadCondMov" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+15
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of T-Head-specific bitmanipulation instructions. The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadSync extension, a collection of T-Head-specific multi-processor synchronization instructions. The 'th' prefix and the "XTheadSync" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCmo extension, a collection of T-Head specific cache management operations. The 'th' prefix and the "XTheadCmo" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 21 instructions: * DCACHE.{C,CI,I}ALL * DCACHE.{C,CI,I}{PA,VA,SW} rs1 * DCACHE.C{PAL1,VAL1} rs1 * ICACHE.I{ALL,ALLS} * ICACHE.I{PA,VA} rs1 * L2CACHE.{C,CI,I}ALL Contrary to Zicbom, the XTheadCmo instructions don't have a constant displacement, therefore we have a different syntax for the arguments. To clarify this is intended behaviour, there is a set of negative test for Zicbom-style arguments in x-thead-cmo-fail.s. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 v2: - Add missing DECLARE_INSN() list - Fix ordering Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add generic support for vendor extensionsChristoph Müllner1-2/+7
This patch introduces changes that allow the integration of vendor ISA extensions: * Define a list of vendor extensions (riscv_supported_vendor_x_ext) where vendor extensions can be added * Introduce a section with a table in the documentation where vendor extensions can be added To add a vendor extension that consists of instructions only, the following things need to be done: * Add the extension to the riscv_supported_vendor_x_ext list * Add lookup entry in riscv_multi_subset_supports * Documenting the extension in c-riscv.texti * Add test cases for all instructions * Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions * Add new instruction class to enum riscv_insn_class * Define the instructions in riscv_opcodes * Additional changes if necessary (depending on the instructions) Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+1
This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of, https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. * elfxx-riscv.c: Add Ztso's arch. binutils\ChangeLog: * readelf.c (get_machine_flags): Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (riscv_set_tso): Ditto. (riscv_set_arch): Ditto. * testsuite/gas/riscv/ztso.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu1-1/+1
bfd/ * elfxx-riscv.c (riscv_implicit_subset): Moved entry of m after g, so that g can imply zmmul. gas/ * testsuite/gas/riscv/attribute-01.d: Updated. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/march-imply-g.d: Likewise. * testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-0/+6
Three-part patch set from Tsukasa OI to support zmmul in assembler. The 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M' which has multiply and divide instructions). bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'. (riscv_supported_std_z_ext): Add 'Zmmul' extension. (riscv_multi_subset_supports): Add handling for new instruction class. gas/ * testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/m-ext.s: New test. * testsuite/gas/riscv/m-ext-32.d: New test (RV32). * testsuite/gas/riscv/m-ext-64.d: New test (RV64). * testsuite/gas/riscv/zmmul-32.d: New expected output. * testsuite/gas/riscv/zmmul-64.d: Likewise. * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure by using RV64-only instructions in RV32). * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test (RV32 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test (RV64 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise. * testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test (no Zmmul or M). * testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise. include/ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in these testcases, so just replaced m by a. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed. opcodes/ * riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-10RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRYFangrui Song1-29/+3
They were legacy relocation types copied from other ports. The related -fvtable-gc was removed from GCC in 2003. The associated assembler directives (.vtable_inherit and .vtable_entry) have never been supported by the RISC-V port. Remove related ld code. Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-45/+52
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask.
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-5/+25
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx. fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate on INSN_CLASS_{D,Q}_AND_ZFH_INX. (riscv_multi_subset_supports_ext): Fix feature gate diagnostics on INSN_CLASS_{D,Q}_AND_ZFH_INX. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march for proper testing.
2022-07-04RISC-V: Update Zihintpause extension versionTsukasa OI1-1/+1
Because ratified Zihintpause extension has a version number of 2.0 (not 1.0), we should update the number. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Update version number of Zihintpause extension.
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+1
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+1
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+1
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu1-23/+0
This patch has been pending for almost a year... However, I noticed that llvm can already re-order the extensions, even if they are out of orders. Not really sure if they can also re-order the single letter extensions, but at least we can do this for the multi-letter extensions in binutils. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are used to check the prefixed extension orders. gas/ * testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help tp reorder the prefixed extensions for now. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.d: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu1-11/+5
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22RISC-V: Add 'H' to canonical extension orderingTsukasa OI1-1/+1
This commit adds 'H' to canonical extension ordering based on current consensus (not officially ratified as a new ISA specification manual but discussion for software compatibility is made). bfd/ChangeLog * elfxx-riscv.c (riscv_ext_canonical_order): Add 'H' for canonical extension ordering based on current consensus.
2022-06-22RISC-V: Prepare i18n for required ISA extensionsTsukasa OI1-13/+14
Some strings returned by the riscv_multi_subset_supports_ext function contain not just extension names but words like "and" and "or". This commit wraps such strings with the gettext macro (_) for internationalization in the future. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports_ext): Wrap some strings with the gettext macro to prepare future i18n.
2022-06-08Revert reloc howto nitsAlan Modra1-1/+1
The "HOWTO size encoding" patch put 1 as the HOWTO size arg for numerous howtos that are unused, describe dynamic relocs, are markers, or otherwise are special purpose reloc howtos that don't care about the size. The idea was to ensure no howto changed by inspecting object files. Revert those changes, making them zero size. * coff-alpha.c: Give special purpose reloc howtos a size of zero. * coff-mcore.c, * elf-hppa.h, * elf-m10300.c, * elf32-arm.c, * elf32-csky.c, * elf32-m32c.c, * elf32-m68k.c, * elf32-mep.c, * elf32-mips.c, * elf32-ppc.c, * elf32-rx.c, * elf32-s390.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, *elf32-vax.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-mips.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elfn32-mips.c, * elfxx-loongarch.c, * elfxx-riscv.c, * elfxx-sparc.c, * elfxx-tilegx.c, * som.c, * vms-alpha.c: Likewise.
2022-06-08HOWTO size encodingAlan Modra1-55/+55
This changes the HOWTO macro to encode the howto.size field from a value given in bytes. This of course requires editing all target uses of HOWTO, a major pain, but makes it a little nicer to specify new target HOWTOs. Object files before/after this patch are unchanged in .data and .rodata. bfd/ * reloc.c (HOWTO_RSIZE): Encode size in bytes. (EMPTY_HOWTO): Adjust to keep it all zero. * aout-ns32k.c, * aoutx.h, * coff-alpha.c, * coff-arm.c, * coff-i386.c, * coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c, * coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c, * elf-hppa.h, * elf-m10200.c, * elf-m10300.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c, * elf32-h8300.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh-relocs.h, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c, * elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-gen.c, * elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c, * elf64-s390.c, * elf64-x86-64.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfxx-ia64.c, * elfxx-loongarch.c, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-sparc.c, * elfxx-tilegx.c, * mach-o-aarch64.c, * mach-o-arm.c, * mach-o-i386.c, * mach-o-x86-64.c, * pdp11.c, * reloc.c, * som.c, * vms-alpha.c: Adjust all uses of HOWTO. * bfd-in2.h: Regenerate. include/ * elf/arc-reloc.def: Adjust all uses of HOWTO.
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-4/+20
The zhinx extension is a sub-extension in zfinx, corresponding to zfh extension but use GPRs instead of FPRs. This patch expanded the zfh insn class define, since zfh and zhinx use the same opcodes, thanks for Nelson's works. changelog in V2: Add missing classes of 'zfh' and 'zhinx' in "riscv_multi_subset_supports_ext". bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): New extensions. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: New test. * testsuite/gas/riscv/fp-zhinx-insns.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): New INSN classes. opcodes/ChangeLog: * riscv-opc.c: Modify INSN_CLASS.
2022-05-25RISC-V: Fix RV32Q conflictTsukasa OI1-2/+3
This commit makes RV32 + 'Q' extension (version 2.2 or later) not conflicting since this combination is no longer prohibited by the specification. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict detection that prohibits RV32Q on 'Q' version 2.2 or later. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32iq.d: Removed. * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test showing RV32IQ fails on 'Q' extension version 2.0. * testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test showing RV32IQ fails on ISA specification version 2.2. * testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test showing RV32IQ succesds on 'Q' extension version 2.2. * testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test showing RV32IQ succesds on ISA specification 20190608.
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-0/+1
Update zfinx implement with zicsr, fix missing fcsr use by zfinx. add zicsr imply by zfinx. bfd/ChangeLog: * elfxx-riscv.c: New imply. gas/ChangeLog: * testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test. opcodes/ChangeLog: * riscv-opc.c: Update insn class.
2022-05-19RISC-V: Fix canonical extension order (K and J)Tsukasa OI1-1/+1
This commit fixes canonical extension order to follow the RISC-V ISA Manual draft-20210402-1271737 or later. bfd/ChangeLog: * elfxx-riscv.c (riscv_recognized_prefixed_ext): Fix "K" extension prefix to be placed before "J".
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu1-0/+11
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added implicit f and zicsr for zfh. (riscv_supported_std_z_ext): Added default v1.0 version for zfh. (riscv_multi_subset_supports): Handle INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH. gas/ * config/tc-riscv.c (FLT_CHARS): Added "hH". (macro): Expand Pseudo M_FLH and M_FSH. (riscv_pseudo_table): Added .float16 directive. * testsuite/gas/riscv/float16-be.d: New testcase for .float16. * testsuite/gas/riscv/float16-le.d: Likewise. * testsuite/gas/riscv/float16.s: Likewise. * testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh. * testsuite/gas/riscv/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh. * opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh. opcodes/ * riscv-opc.c (riscv_opcodes): Added zfh instructions.
2022-03-18RISC-V: Cache management instructionsTsukasa OI1-0/+6
This commit adds 'Zicbom' / 'Zicboz' instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions.
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+3
This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
2022-02-25RISC-V: Remove a loop in the ISA parserTsukasa OI1-7/+4
Since commit e601909a3287bf541c6a7d82214bb387d2c76d82 ("RISC-V: Support to parse the multi-letter prefix in the architecture string.") changed so that all prefixed extensions are parsed in single riscv_parse_prefixed_ext call, a "while" loop on riscv_parse_subset is no longer required. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_subset): Remove unnecessary loop.
2022-02-23RISC-V: PR28733, add missing extension info to 'unrecognized opcode' errorPatrick O'Neill1-0/+94
Currently we report errors as "unrecognized opcode `fence.i'" when the opcode isn't part of the selected extensions. This patch expands that error message to include the missing extension information. For example, now the error message would be "unrecognized opcode `fence.i', extension `zifencei' required". If the opcode is not a part of any extension, the error message reverts to "unrecognized opcode `<op statement>'". Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> bfd/ pr 28733 * elfxx-riscv.c (riscv_multi_subset_supports_ext): New function, used to return the extension string for each INSN_CLASS_*. * elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext. gas/ pr 28733 * config/tc-riscv.c (struct riscv_ip_error): New structure, contains information about errors that occur within the riscv_ip. (riscv_ip): Use struct riscv_ip_error to report more detailed errors. * testsuite/gas/riscv/c-fld-fsd-fail.l: Updated. * testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
2022-02-22RISC-V: Maintain a string to hold the canonical orderKito Cheng1-17/+5
Using dummy entry in riscv_supported_std_ext cause confusing and wrongly support `b` and `k` extensions. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Drop unsupported extensions. (riscv_ext_canonical_order): New. (riscv_init_ext_order): Use riscv_ext_canonical_order rather than riscv_supported_std_ext to compute canonical order. V2 Changes: - Use `*ext` rather than `*ext != NULL` for checking is reach end of string.
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu1-1/+3
Update the default ISA spec from 2.2 to 20191213 will change the default version of i from 2.0 to 2.1. Since zicsr and zifencei are separated from i 2.1, users need to add them in the architecture string if they need fence.i and csr instructions. Besides, we also allow old ISA spec can recognize zicsr and zifencei, but we won't output them since they are already included in the i extension when i's version is less than 2.1. bfd/ * elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can recognize zicsr and zifencei. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213. * testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since the default version of i is 2.1. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1. * testsuite/gas/riscv/option-arch-03.s: Likewise. ld/ * testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since the default version of i is 2.1. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei into Tag_RISCV_arch since it is added implied when i's version is larger than 2.1.
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