riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-10-08	RISC-V: Fix implicit dependency of Zabha and Zacas	Xiao Zeng	1	-2/+2
2024-09-25	RISC-V: Add Smrnmi extension csrs.	Jiawei	1	-0/+1
2024-09-03	RISC-V: Add support for XCVsimd extension in CV32E40P	Mary Bennett	1	-0/+5
2024-08-06	RISC-V: Add support for XCvBitmanip extension in CV32E40P	Mary Bennett	1	-10/+15
2024-08-06	RISC-V: Add support for Zcmop extension	Xiao Zeng	1	-0/+6
2024-08-06	RISC-V: Add support for Zimop extension	Xiao Zeng	1	-0/+5
2024-07-24	RISC-V: PR32001, Untranslated "internal:" prefix for error message.	Nelson Chu	1	-1/+1
2024-07-11	RISC-V: Add platform property/capability extensions	Tsukasa OI	1	-0/+33
2024-06-28	RISC-V: Shrink the riscv_implicit_subsets table.	Nelson Chu	1	-165/+149
2024-06-28	RISC-V: Add Zabha extension CAS instructions.	Jiawei	1	-0/+3
2024-06-21	RISC-V: Remove implicit enablement of Zvknha from Zvkn.	Feng Wang	1	-1/+0
2024-06-18	RISC-V: Fixed typo from smscrind to smcsrind in riscv_implicit_subsets.	Nelson Chu	1	-1/+1
2024-06-18	RISC-V: Add SiFive cease extension v1.0	Hau Hsu	1	-1/+6
2024-06-18	RISC-V: Support Zacas extension.	Gianluca Guida	1	-0/+6
2024-06-12	RISC-V: Support S[sm]csrind extension csrs.	Jiawei	1	-0/+4
2024-06-06	RISC-V: Add support for Zvfbfwma extension	Xiao Zeng	1	-0/+7
2024-06-06	RISC-V: Add support for Zvfbfmin extension	Xiao Zeng	1	-0/+6
2024-06-06	RISC-V: Add support for Zfbfmin extension	Xiao Zeng	1	-0/+6
2024-06-05	RISC-V: Add support for XCVmem extension in CV32E40P	Mary Bennett	1	-0/+5
2024-06-05	RISC-V: Add support for XCVbi extension in CV32E40P	Mary Bennett	1	-0/+5
2024-06-05	RISC-V: Add support for XCVelw extension in CV32E40P	Mary Bennett	1	-0/+5
2024-05-08	RISC-V: Support B, Zaamo and Zalrsc extensions.	Nelson Chu	1	-4/+16
2024-04-09	RISC-V: Support Zcmp push/pop instructions.	Jiawei	1	-0/+13
2024-03-13	RISC-V: Add -march=help for gas	Hau Hsu	1	-0/+46
2024-03-08	RISC-V: Support Zabha extension.	Jiawei	1	-0/+6
2024-02-29	RISC-V: Add TLSDESC reloc definitions.	Tatsuyuki Ishi	1	-1/+74
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2023-12-15	RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'	Xiao Zeng	1	-0/+4
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	1	-0/+5
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner	1	-2/+8
2023-11-24	RISC-V: Update 'Zfa' extension version	zengxiao	1	-1/+1
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	1	-0/+5
2023-11-23	RISC-V: Add T-Head VECTOR vendor extension.	Jin Ma	1	-0/+12
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	1	-0/+5
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	1	-0/+5
2023-11-06	RISC-V: Moved out linker internal relocations after R_RISCV_max.	Nelson Chu	1	-85/+93
2023-10-16	RISC-V: Remove RV64E conflict	Tsukasa OI	1	-7/+0
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu	1	-1/+0
2023-09-05	RISC-V: Add stub support for the 'Svadu' extension	Tsukasa OI	1	-0/+2
2023-09-05	RISC-V: Add 'Smcntrpmf' extension and its CSRs	Tsukasa OI	1	-0/+2
2023-09-05	RISC-V: Prohibit combination of 'E' and 'H'	Tsukasa OI	1	-0/+7
2023-08-18	RISC-V: Report "c or zca" for INSN_CLASS_C when error reporting.	Nelson Chu	1	-1/+1
2023-08-15	RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'	Tsukasa OI	1	-0/+15
2023-08-15	RISC-V: Add support for the 'Zihintntl' extension	Tsukasa OI	1	-0/+20
2023-08-11	RISC-V: Remove support for non-existing 'Zve32d'	Tsukasa OI	1	-1/+0
2023-08-08	RISC-V: Update ratified 'Ztso' extension version	Tsukasa OI	1	-1/+1
2023-08-03	RISC-V: Add support for 'Zvfh' and 'Zvfhmin'	Tsukasa OI	1	-0/+5
2023-08-03	RISC-V: Imply 'Zicsr' from 'Zve32x'	Tsukasa OI	1	-0/+1
2023-08-02	Revert "2.41 Release sources"	Sam James	1	-23/+61
2023-08-02	2.41 Release sourcesbinutils-2_41-release	Nick Clifton	1	-61/+23