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2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab8-1580/+1700
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>] where T is 4h or 8h gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_ELEMENT_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the vector indexed element group. Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab8-1238/+1650
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX. The general form for these instructions is <OP> <Hd>, <Hs> or <OP> <Hd>, <Hs>, #0.0 Tested the series for aarch64-none-linux-gnu with cross-compiled check-binutils and check-gas. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_FCMP_H_0): new. (QL_S_2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe, frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu, fcvtzu and frsqrte to the scalar two register misc. group. Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab9-1776/+2377
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS, FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of frintn, frintm, fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp, frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte and fsqrt to the vector register misc. group. Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab8-1081/+1268
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FRECPS and FRSQRTS. The general form for these instructions is <OP> <Hd>, <Hs>, <Hm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt to the scalar three same group. Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab8-1363/+1907
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA, FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: New. * gas/aarch64/advsimd-fp16.s: New. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V3SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd, fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts, fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd, fcmgt, facgt and fminp to the vector three same group. Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2-0/+8
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch set adds the 16-bit Adv.SIMD vector and scalar instructions to binutils, making them available when both +simd and +fp16 architecture extensions are enabled. The series also adds support for a new vector type, 2H, used by the FP16 scalar pairwise instructions. The patches in this series: - Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding routines. - Add FP16 instructions in the group Vector Three Register Same. - Add FP16 instructions in the group Scalar Three Register Same. - Add FP16 instructions in the group Vector Two Register Misc. - Add FP16 instructions in the group Scalar Two Register Misc. - Add FP16 instructions in the group Vector Indexed Element. - Add FP16 instructions in the group Scalar Indexed Element. - Add FP16 instructions in the group Adv.SIMD Across Lanes. - Add FP16 instructions in the group Adv.SIMD Modified Immediate. - Rework some code for handling vector types to weaken its assumptions about available vector-types. - Add support for the 2H vector type. - Add FP16 instructions in the group Adv.SIMD Scalar Pairwise. - Add FP16 instructions in the group Adv.SIMD Shift By Immediate. - Add a FP16 instructions in the group Adv.SIMD Scalar Shift By Immediate. This patch adds the feature macro SIMD_F16 to the AArch64 encoding/decoding routines. It is used to decide when the new instructions are available to the assembler and is true when both +simd and +fp16 are selected. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-tbl.h (aarch64_feature_simd_f16): New. (SIMD_F16): New. Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab2-6/+15
A mistake with rebasing the ARMv8.2 AT instruction patch left this part + /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ + if ((reg->value == CPENS (0, C7, C9, 0) + || reg->value == CPENS (0, C7, C9, 1)) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) + return FALSE; in aarch64_pstatefield_supported_p rather than in aarch64_sys_ins_reg_supported_p, where it was supposed to be. The patch adding support for id_aa64mmfr2_el1, also had the effect of removing a conditional branch in aarch64_sys_reg_supported_p. The effect of both of these is to suppress an error if some ARMv8.2 system registers are used with the wrong -march settings. This patch fixes these mistakes. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly removed statement. (aarch64_pstatefield_supported_p): Move feature checks for AT registers .. (aarch64_sys_ins_reg_supported_p): .. to here. Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4
2015-12-14gdb: Use TYPE_LENGTH macroAndrew Burgess3-8/+16
Fixes a couple of places where we access the length field of the type structure directly, rather than using the TYPE_LENGTH macro. gdb/ChangeLog: * i386-tdep.c (i386_mpx_info_bounds): Use TYPE_LENGTH. (i386_mpx_set_bounds): Likewise. * solib-darwin.c (darwin_load_image_infos): Likewise. (darwin_solib_read_all_image_info_addr): Likewise.
2015-12-14gas: free allocated symbol name in .cfi_label handlingJan Beulich2-0/+5
I've just noticed this further oversights of the original commit.
2015-12-14nm: basic COFF symbol type support for SysV-style symbol table dumpingJan Beulich2-4/+63
2015-12-14Automatic date update in version.inGDB Administrator1-1/+1
2015-12-13Remove const from return type of get_output_view.Cary Coutant3-8/+15
gold/ * object.h (Object::get_output_view): remove const from return type. (Object::do_get_output_view): Likewise. (Sized_relobj_file::do_get_output_view): Likewise. * reloc.cc (Sized_relobj_file::do_get_output_view): Likewise.
2015-12-13Automatic date update in version.inGDB Administrator1-1/+1
2015-12-12Fix SH gas testsuite invalid assembly exposed by ec9ab52cAlan Modra3-2/+7
* gas/sh/tlsd.s: Use .tdata not .tbss. * gas/sh/tlsnopic.s: Likewise.
2015-12-12Enable 2 operand form of powerpc mfcr with -manyAlan Modra2-3/+8
This is a workaround for a gcc bug. PR 19359 * ppc-opc.c (insert_fxm): Remove "ignored" from error message. (powerpc_opcodes): Remove single-operand mfcr.
2015-12-12Automatic date update in version.inGDB Administrator1-1/+1
2015-12-11gdb: Extend help text for 'list' command.Andrew Burgess2-2/+11
Reference the 'listsize' setting in the help text for the 'list' command to help users find this setting. gdb/ChangeLog: * cli/cli-cmds.c (_initialize_cli_cmds): Extend help text for 'list' command.
2015-12-11gdb: Add an error when 'list -' reaches the start of a file.Andrew Burgess4-4/+33
When a a user uses 'list +' to list forward through a source file they eventually reach the end of the source file. Subsequent uses of 'list +' result in an error message like this, that let the user know they are at the end of the source file: Line number XXX out of range; FILENAME has YYY lines. Compare this to the current behaviour of 'list -' which lists backwards through a source file. When the user reaches the beginning of the source file, subsequent uses of 'list -' result in the command silently returning. This can be confusing if the previous uses of 'list -' have scrolled off the users display, the user receives no reminder that the have already seen the start of the file. After this commit a use of 'list -' when the user has already seen the start of a file will receive the following error: Already at the start of FILENAME. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Add an error when trying to use '-' to scan read off the start of the source file. gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list_forward): Add end of file error test. (test_repeat_list_command): Add end of file error test. (test_list_backwards): Add beginning of file error test.
2015-12-11gdb: 'list' command, tweak handling of +/- arguments.Andrew Burgess4-3/+32
There is an inconsistency with the handling of the special +/- arguments to the list command. For the very first time that list is used (after the inferior has changed locations) then only the first character of the argument string is checked, so 'list +BLAH' will operate as 'list +' and 'list -----FOO' will operate as 'list -'. This compares to each subsequent use of list, where the whole argument string is checked, so 'list +BLAH' will try to list lines of code around the function '+BLAH'. This commit unifies the behaviour so that the whole argument string is checked, in order to list the next 10, or previous 10 lines from a file only 'list +' and 'list -' are now valid. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Check that the argument string is a single character, either '+' or '-'. gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list_invalid_args): New function, defined, and called.
2015-12-11gdb: Make test names unique in list.exp.Andrew Burgess2-2/+10
gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list): Make test names unique.
2015-12-11gdb: Small code restructure for list_command.Andrew Burgess2-17/+16
Move handling of special +/- arguments to the list_command function inside a single if block, this helps group all related functionality together. There should be no user visible changes after this commit. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Move all handling of +/- arguments into a single if block.
2015-12-11gdb: Use NULL instead of 0 for pointer comparison.Andrew Burgess2-2/+7
Small code cleanup, use NULL instead of 0 when checking pointers. There should be no user visible changes after this commit. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Use NULL instead of 0 when checking pointers.
2015-12-11gdb: Make lines_to_list variable static.Andrew Burgess2-1/+5
Small clean up, make variable static. gdb/ChangeLog: * source.c (lines_to_list): Make static.
2015-12-11Pass relocations to Target::do_calls_non_split.Cary Coutant7-4/+32
gold/ * target.h (Target::calls_non_split): Add prelocs, reloc_count parameters. (Target::do_calls_non_split): Likewise. * target.cc (Target::do_calls_non_split): Likewise. * reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust call to Target::calls_non_split. * i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count parameters. * powerpc.cc (Target_powerpc::do_calls_non_split): Likewise. * x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.
2015-12-11Make output views accessible to Target during do_relocate().Cary Coutant4-1/+87
gold/ * object.cc (Sized_relobj_file::Sized_relobj_file): Initialize output_views_. * object.h (Object::get_output_view): New function. (Object::do_get_output_view): New function. (Sized_relobj_file::do_get_output_view): New function. (Sized_relobj_file::output_views_): New data member. * reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to output views in class object. (Sized_relobj_file::do_get_output_view): New function.
2015-12-11Remove gdb.base/coremaker2.cYao Qi2-75/+4
I happen to find that coremaker2.c isn't used in the testsuite (if I don't miss anything). I don't believe it until I see this ChangeLog entry, 1999-11-18 Fred Fish <fnf@cygnus.com> * gdb.base/coremaker2.c: Add sample program for generating cores that is more self contained than coremaker.c. Eventually I'll add more code to this and tie it into the testsuite. looks Fred didn't "tie it into testsuite" later. gdb/testsuite: 2015-12-11 Yao Qi <yao.qi@linaro.org> * gdb.base/coremaker2.c: Remove.
2015-12-11Understand arm breakpoints in aarch64_breakpoint_atYao Qi2-6/+16
AArch64 GDBserver can debug ARM program, and it should recognize various arm breakpoint instructions. This patch should be included in 17b1509a. gdb/gdbserver: 2015-12-11 Yao Qi <yao.qi@linaro.org> * linux-aarch64-low.c (aarch64_breakpoint_at): Call arm_breakpoint_at if the process is 32-bit.
2015-12-11Use arm_eabi_breakpoint on aarch32Yao Qi2-3/+8
Nowdays, GDBserver chooses arm breakpoint instructions by checking macro __ARM_EABI__. When aarch64 GDBserver debugs arm program, arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined in aarch64 compiler. This causes GDBserver chooses the wrong breakpoint instruction for arm program. This patch fixes it. gdb/gdbserver: 2015-12-11 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint arm breakpoint.
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab13-28/+135
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab10-4/+75
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds support for aliases of HINT which take an operand, adding a table to store operand names and their matching hint number as well as encoding and decoding functions for such operands. Parsing and printing the operands are deferred to any support added for aliases with such operands. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_hint_options): Declare. (aarch64_opnd_info): Add field hint_option. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm.c (aarch64_ins_hint): New. * aarch64-asm.h (aarch64_ins_hint): Declare. * aarch64-dis.c (aarch64_ext_hint): New. * aarch64-dis.h (aarch64_ext_hint): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): New. * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
2015-12-11[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.Matthew Wahab2-2/+6
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. The HINT instruction currently has 8 aliases, which is the maximum number allowed. This patch raises to 16 the limit on the number of aliases an instruction can have. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16. Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab5-2/+91
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers. This patch adds the registers to binutils, making them available when the architecture extension "+profile" is enabled. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and pmscr_el2. (aarch64_sys_reg_supported_p): Add architecture feature tests for the new registers. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling system registers. * gas/aarch64/sysreg-2.d: Enable the statistical profiling extension and update the expected output. Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
2015-12-11[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.Matthew Wahab5-0/+13
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers and a new instruction. This patch set adds support for the extension to binutils, enabled when -march=armv8.2-a+profile is given. The patches in this series: - Add the new command line option and feature flags. - Add the new system registers. - Adjust the maximum number of aliases permitted for an instruction. - Add support for HINT aliases which take operands. - Add the new instruction, an alias of the HINT instruction. This patch adds the option "profile" to the permitted architecture extensions, disabling it by default. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "profile". * doc/c-aarch64.texi (AArch64 Extensions): Add "profile". include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PROFILE): New. Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-11Automatic date update in version.inGDB Administrator1-1/+1
2015-12-10ld -r doesn't need plugin for slim lto objectH.J. Lu6-1/+39
Plugin isn't required on slim lto object for relocatable link. bfd/ PR ld/19317 * linker.c (_bfd_generic_link_add_one_symbol): Don't complain plugin needed to handle slim lto object for relocatable link. ld/testsuite/ PR ld/19317 * ld-plugin/lto.exp (lto_no_fat): New. (lto_link_tests): Add a test for PR ld/19317. (lto_run_tests): Likewise. (run_ld_link_tests): Likewise.
2015-12-10Fix regression revealed by corethreads.expAntoine Tremblay2-1/+5
This patch fixes a regression introduced by: https://sourceware.org/ml/gdb-patches/2015-12/msg00192.html We can't use thread_from_lwp with core files. As mentioned in a comment, td_ta_map_lwp2thr uses ps_get_thread_area, but we can't use that currently on core targets, as it uses ptrace directly. Use directly record_thread instead. This fixes : PASS -> FAIL: gdb.threads/corethreads.exp: thread0 found PASS -> FAIL: gdb.threads/corethreads.exp: thread1 found gdb/ChangeLog: * linux-thread-db.c (find_new_threads_callback): Use record_thread.
2015-12-10ld -r doesn't need plugin for slim lto objectH.J. Lu2-1/+8
Plugin isn't required on slim lto object for relocatable link. PR ld/19317 * symtab.cc (Symbol_table::add_from_relobj): Don't complain plugin needed to handle slim lto object for relocatable link.
2015-12-10[gdb/doc] Explain that there's always a threadPedro Alves2-18/+9
This warning is a few years out of date -- there's always a thread nowadays. gdb/doc/ChangeLog: * gdb.texinfo (Threads): Replace warning with explanation about single-threaded programs.
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab5-0/+27
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This patch adds support for the instructions, making them available when -march=armv8.2-a is selected. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and AT S1E1WP. * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register feature test for "s1e1rp" and "s1e1wp". Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
2015-12-10[gdb/doc] Remove references to no-longer-supported systemsPedro Alves2-40/+33
HP-UX and SGI/IRIX are no longer supported. Remove references throughout. AFAICS from the sources, "catch fork" seems to be supported in multiple Unix systems -- just remove the "only works on xxx" remarks. Update the list of supported shared library types. gdb/doc/ChangeLog: * gdb.texinfo (Threads): Remove mention of SGI. (Forks): Remove mention of HP-UX. (Breakpoints): Remove mention of HP-UX. (Set Watchpoints) <hardware watchpoints>: Don't mention HP-UX. Reword in terms of architectures. (Set Catchpoints) <catch exec, catch fork, catch vfork>: Don't mention supported systems. (Convenience Vars): Don't mention HP-UX. (Jumping): Remove mention of HP-UX in comment. (Files) <shared libraries>: Update supported shared library types list. Remove mention of HP-UX. (Native): Remove HP-UX subsection. (SVR4 Process Information): Remove mention of HP-UX.
2015-12-10Remove "spaces" references from gdb.multi/base.expPedro Alves2-4/+8
I think these references to "spaces" came from the original multi-exec submission that exposed "symbol spaces" to the user and had a different UI, and then survived a global find/replace. gdb/testsuite/ChangeLog: 2015-12-10 Pedro Alves <palves@redhat.com> * gdb.multi/base.exp: Remove stale "spaces" references.
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab9-0/+51
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab5-48/+82
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds support for this instruction to binutils, enabled when -march=armv8.2-a is selected. The AArch64 binutils record of some system registers uses a boolean value to hold the single flag currently supported for them. To allow these registers to be limited to specific architectures, the first patch in this series replaces the boolean flag with a bitset and feature test. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Likewise. (F_HASXT): New. (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. (aarch64_sys_regs_dc): Likewise. (aarch64_sys_regs_at): Likewise. (aarch64_sys_regs_tlbi): Likewise. (aarch64_sys_ins_reg_has_xt): New. Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
2015-12-10Stop using nowarnings in gdb/testsuite/gdb.multi/Pedro Alves8-8/+23
Several of the gdb.multi tests use the "nowarnings" option to suppress warnings. The warnings in question all come from missing headers, like e.g.: src/gdb/testsuite/gdb.multi/multi-arch-exec.c:28:3: warning: incompatible implicit declaration of built-in function 'exit' [enabled by default] exit (1); ^ There's no point in trying to avoid to include standard headers. In gdb.base/hangout.c's case, it's even dangerous, as that file calls printf. In order to compile a call to a variatic function correctly, a declaration must be visible. gdb/testsuite/ChangeLog: 2015-12-10 Pedro Alves <palves@redhat.com> * gdb.multi/base.exp: Don't use nowarnings. * gdb.multi/bkpt-multi-exec.exp: Don't use nowarnings. * gdb.multi/hangout.c: Include stdio.h. * gdb.multi/hello.c: Include stdlib.h. * gdb.multi/multi-arch-exec.c: Include stdlib.h. * gdb.multi/multi-arch-exec.exp: Don't use nowarnings. * gdb.multi/multi-arch.exp: Don't use nowarnings.
2015-12-10ld: Fix LTO for MinGW targetsKwok Cheung Yeung2-2/+11
When creating a dummy BFD for an IR file, the output BFD is used as a template for the new BFD, when it needs to be the input BFD passed into the function when not dealing with a BFD plugin. On most targets this is not an issue as the input and output formats are the same anyway, but on MinGW targets, there are two variant formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are similar but not interchangeable here. PR ld/18199 * plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the template when calling bfd_create if it does not use the BFD plugin target vector.
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab6-0/+84
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for this bit to binutils, following the same basic pattern as for PSTATE.PAN. The new control bit is only available when -march=armv8.2-a is specified. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/uao-directive.d: New. * gas/aarch64/uao.d: New. * gas/aarch64/uao.s: New. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "uao". (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". (aarch64_pstatefields): Add "uao". (aarch64_pstatefield_supported_p): Add checks for "uao". Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
2015-12-10gas: documentation for the SPARC %dN and %qN fp registers notationJose E. Marchesi2-0/+13
gas/ChangeLog: 2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation for floating-point registers.
2015-12-10Remove support for thread events without PTRACE_EVENT_CLONE in GDBAntoine Tremblay6-587/+46
Before, on systems that did not support PTRACE_EVENT_CLONE, both GDB and GDBServer coordinated with libthread_db.so to insert breakpoints at magic locations in libpthread.so, in order to break at thread creation and thread death. Support for thread events was removed from GDBServer as patch: https://sourceware.org/ml/gdb-patches/2015-11/msg00466.html This patch removes support for thread events in GDB. No regressions found on Ubuntu 14.04 x86_64. gdb/ChangeLog: * breakpoint.c (remove_thread_event_breakpoints): Remove. * breakpoint.h (remove_thread_event_breakpoints): Remove declaration. * linux-nat.c (in_pid_list_p): Remove. (lin_lwp_attach_lwp): Remove. * linux-nat.h (lin_lwp_attach_lwp): Remove declaration. * linux-thread-db.c (thread_db_use_events): Remove. (struct thread_db_info) <td_create_bp_addr>: Remove. <td_death_bp_addr>: Likewise. <td_ta_event_addr_p>: Likewise. <td_ta_set_event_p>: Likewise. <td_ta_clear_event_p>: Likewise. <td_ta_event_getmsg_p>: Likewise. <td_thr_event_enable_p>: Likewise. (attach_thread): Likewise. (detach_thread): Likewise. (have_threads_callback): Likewise. (have_threads): Likewise. (enable_thread_event): Likewise. (enable_thread_event_reporting): Likewise. (try_thread_db_load_1): Remove td_ta_event_addr, td_ta_set_event, td_ta_clear_event, td_ta_event_getmsg, td_thr_event_enable initializations. (try_thread_db_load_1): Remove enable_thread_event_reporting call. (disable_thread_event_reporting): Remove. (record_thread): Adapt to thread_db_use_event removal. (detach_thread): Remove. (thread_db_detach): Adapt to thread_db_use_event removal. (check_event): Remove. (thread_db_wait): Adapt to thread events support removal. (thread_db_mourn_inferior): Likewise. (find_new_threads_callback): Likewise. (find_new_threads_once): Likewise. (thread_db_update_thread_list): Likewise.
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab5-0/+86
The ARMv8.2 RAS extension adds a number of new registers. This patch adds the registers and makes them available whenever the RAS extension is enabled, as it is when -march=armv8.2-a is selected. The new registers are: erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1, erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and vdisr_el2. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for new registers. * gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with tabs. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". (aarch64_sys_reg_supported_p): Add architecture feature tests for new registers. Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab10-25/+68
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias and the preferred form of HINT 16. This patch adds an architectural feature flag for the RAS extension and includes it in the features selected enabled by -march=armv8.2-a. It also adds the ESB instruction, making it available whenever the RAS feature is enabled. Because ESB is the preferred form and because the target architecture isn't available to the disassembler, HINT 16 will be disassembled as ESB even when the target has no support for the RAS extension. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_RAS): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (aarch64_feature_ras): New. (RAS): New. (aarch64_opcode_table): Add "esb". Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
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