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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 16:58:51 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-12-10 17:00:27 +0000 |
| commit | 22a5455c6ccaf6157095863f9e6da33a81541acf (patch) | |
| tree | 094e7d4ffe83b699729c2e30e1c5024b85cefe8c | |
| parent | b1236ac35aaad56d76a5670a5a22cc2be124a736 (diff) | |
| download | gdb-22a5455c6ccaf6157095863f9e6da33a81541acf.zip gdb-22a5455c6ccaf6157095863f9e6da33a81541acf.tar.gz gdb-22a5455c6ccaf6157095863f9e6da33a81541acf.tar.bz2 | |
[Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-2.s | 5 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 8 |
5 files changed, 27 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1a2f004..4027a7c 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and + AT S1E1WP. + * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP. + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d index dffe08f..f73412f 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.d +++ b/gas/testsuite/gas/aarch64/sysreg-2.d @@ -30,3 +30,5 @@ Disassembly of section .text: [0-9a-f]+: d50b7a20 dc cvac, x0 [0-9a-f]+: d50b7b21 dc cvau, x1 [0-9a-f]+: d50b7c22 dc cvap, x2 + [0-9a-f]+: d5087900 at s1e1rp, x0 + [0-9a-f]+: d5087921 at s1e1wp, x1 diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s index 62b3a5e..f89d057 100644 --- a/gas/testsuite/gas/aarch64/sysreg-2.s +++ b/gas/testsuite/gas/aarch64/sysreg-2.s @@ -36,3 +36,8 @@ dc cvac, x0 dc cvau, x1 dc cvap, x2 + + /* AT. */ + + at s1e1rp, x0 + at s1e1wp, x1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3d84fbe..aec423b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". + (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register + feature test for "s1e1rp" and "s1e1wp". + +2015-12-10 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 86aeae0..b2f772e 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3245,6 +3245,12 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) return FALSE; + /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ + if ((reg->value == CPENS (0, C7, C9, 0) + || reg->value == CPENS (0, C7, C9, 1)) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) + return FALSE; + return TRUE; } @@ -3284,6 +3290,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] = { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT }, { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT }, { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT }, + { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT }, + { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT }, { 0, CPENS(0,0,0,0), 0 } }; |