| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
gracefully.
|
|
There is no need to loop over the headers twice. Remove that leftover
from the previous scheme. Also, the previous scheme silently ignored
a section being mentioned in two or more SHT_GROUP sections.
* elf.c (process_sht_group_entries): Prevent sections from
belonging to two groups.
(_bfd_elf_setup_sections): Process groups in a single loop
over headers.
|
|
|
|
This patch delays setting up elf_next_in_group, elf_sec_group and
elf_group_name when reading ELF object files until after all ELF
sections have been processed by bfd_section_from_shdr. This is simpler
and more robust than the current scheme of driving the whole process
on detecting a section with SHF_GROUP set.
* elf-bfd.h (struct elf_obj_tdata): Delete group_sect_ptr,
num_group and group_search_offset.
* elf.c (Elf_Internal_Group): Delete.
(setup_group): Delete function.
(IS_VALID_GROUP_SECTION_HEADER): Delete macro.
(is_valid_group_section_header),
(process_sht_group_entries): New functions.
(_bfd_elf_setup_sections): Handle group sections here..
(_bfd_elf_make_section_from_shdr): ..rather than here.
(bfd_section_from_shdr): Don't check SHT_GROUP validity here.
|
|
PR 20814
|
|
Simplify a gdb_test_multiple in test-case gdb.base/bg-execution-repeat.exp
using "gdb_test -no-prompt-anchor".
Suggested-By: Guinevere Larsen <blarsen@redhat.com>
Tested on x86_64-linux.
|
|
I ran into the following test failure with test-case
gdb.base/bg-execution-repeat.exp:
...
(gdb) PASS: gdb.base/bg-execution-repeat.exp: c&: repeat bg command
^M
Breakpoint 2, foo () at bg-execution-repeat.c:23^M
23 return 0; /* set break here */^M
print 1^M
$1 = 1^M
(gdb) PASS: gdb.base/bg-execution-repeat.exp: c&: input still accepted
FAIL: gdb.base/bg-execution-repeat.exp: c&: breakpoint hit 2 (timeout)
...
The failure can be easily reproduced by adding a sleep 5 here:
...
+ sleep 5
gdb_test "print 1" " = 1" "input still accepted"
...
There's a race in the test-case, between:
- the command handled in the foreground: the "print 1" command, and
- the command handled in the background: the continue command.
The current way of dealing with this is by putting the inferior to sleep for 5
seconds:
...
foo ();
sleep (5);
foo ();
...
with the aim that the "print 1" command will win the race.
This method is both slow and unreliable.
Fix this by making the inferior wait till the "print 1" command is done.
This reduces running time from ~11s to ~1s.
I also verified that the test-case still triggers on the original problem by
applying this gdb/infcmd.c patch:
...
-strip_bg_char (const char *args, int *bg_char_p)
+strip_bg_char (const char *_args, int *bg_char_p)
{
- const char *p;
+ char *args = const_cast<char *>(_args);
+ char *p;
if (args == nullptr || *args == '\0')
{
@@ -210,6 +211,7 @@ strip_bg_char (const char *args, int *bg_char_p)
p--;
while (p > args && isspace (p[-1]))
p--;
+ *p = '\0';
...
Tested on x86_64-linux, with make-check-all.sh.
PR testsuite/31794
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31794
Reviewed-By: Guinevere Larsen <blarsen@redhat.com>
|
|
Update some of the content to make the specification document hopefully
clearer:
- Fix some typos.
- Use Title case consistently for headings.
- Update text around detection of foreign endianness.
- Split the structure field "Name" in each table to two separate
colunms for additional attention: "Type" and "Name".
- Rename "SFrame endianness" section to "SFrame magic number and
endianness"
- Update text around provisions for extending SFrame for future
ABIs/architectures. Make it clear by tagging all provisions with an
explicit index item "Provisions for future ABIs".
- Add a paragraph on sort order of SFrame FDEs.
- Add a statement for SFRAME_F_FRAME_POINTER flag.
- Add a statement to assert that SFrame version 1 is now obsolete and
should not be used.
libsframe/
* doc/sframe-spec.texi: Small improvements for readability.
|
|
|
|
Following feedback received shortly after the initial commit of the
aarch64 instructions for scaling and converting fp8 instructions, this
patch addresses the issues raised in the relevant feedback.
This includes the following changes:
* Standardize all FP8 qualifier-set names. This has resulted in the
renaming of QL_V2FP8B8H to QL_V2_HB_LOWER and, likewise, QL_V28H16B
to QL_V2_HB_FULL.
* Update `FP8_INSN' aarch64_opcode_table[] entries to reflect the new
standardized qualifier-set names mentioned above and, in the case of
the "fcvtn" entries, also add a leading 0 to their opcode values so
they are given as 8 hexadecimal digits in length to ensure
consistency in formatting relative to other entries in the table.
* Revise the added test-cases so that when checking operand fields in
the disassembled binaries, all bits for these fields get tested to
ensure they can be toggled on/off by the relevant operand arguments.
|
|
We have recently updated the interface for raising exceptions to use
long [1] and updated mach_port_t to be "unsigned int". This patches fixes
those problems and will help us port GDB to Hurd x86_64.
Tested on Hurd i686 and x86_64.
[1] https://git.savannah.gnu.org/cgit/hurd/gnumach.git/tree/include/mach/exc.defs
Approved-By: Simon Marchi <simon.marchi@efficios.com>
|
|
The AArch64 instruction table (aarch64-tbl.h) defines the operand
ADDR_SIMPLE as "address with base register (no offset)". During assembly
it is correctly encoded as address with base register (addr.base_regno)
in parse_operands. In warn_unpredictable_ldst it is erroneously treated
as register number (reg.regno).
This resolves the assembler test case "Diagnostics Quality" to
erroneously fail when changing the union in struct aarch64_opnd_info
from union to struct for debugging purposes.
gas/
* config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with
base register.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
|
|
The AArch64 instruction table (aarch64-tbl.h) defines the operand
Rt_IN_SYS_ALIASES as register number. During assembly it is correctly
encoded as register number (reg.regno) in parse_operands. During
disassembly it is first correctly decoded as register number (reg.regno)
in aarch64_ext_regno called by aarch64_extract_operand, but then
erroneously treated as immediate value (imm.value) in
aarch64_print_operand.
This resolves the assembler test case "gas/aarch64/brbe-brb-inst" to
erroneously fail on s390. On AArch64 - being little-endian - the struct
aarch64_opnd_info union fields reg.regno and imm.value share their
least-significant bits. On s390 - being big-endian - they do not.
opcodes/
PR binutils/31919
* aarch64-opc.c: Treat operand Rt_IN_SYS_ALIASES as register
number.
Bug: https://sourceware.org/PR31919
Fixes: 72476aca8f58 ("aarch64: add Branch Record Buffer extension instructions")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
|
|
I noticed that the 'all-doc' build target doesn't build all the doc
formats, 'man' and 'html' are missing.
This commit updates 'all-doc' so that all formats are built.
This doesn't change the default 'all' target, which is the default
target used when building GDB itself, the 'all' target continues to
just build the 'info' docs.
There should be no difference in the actual generated output after
this commit, I'm just changing what gets built.
Approved-By: Tom Tromey <tom@tromey.com>
|
|
After this commit:
commit 0700386f142f0b0d3d0021995970a1b41c36cc92 (gdb-tmp-c)
Date: Wed May 8 19:12:57 2024 +0100
gdb/doc: fix parallel build of pdf and dvi files
When building the dvi or pdf targets you'd get errors like this:
mkdir: cannot create directory ‘texi2dvi_tmpdir/gdb_dvi’: No such file or directory
mkdir: cannot create directory ‘texi2dvi_tmpdir/gdb_pdf’: No such file or directory
fixed by ensuring the directory is created before calling texi2dvi.
|
|
|
|
This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.
The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.*
to maintain consistency in the testsuite.
The bfloat16-1-invalid.* tests are modified so that "selected
processor does not support" is generated by the assembler, since
+b16b16 is not passed in the command line.
The bfloat16-2-invalid.* testcase includes the wrong operands
bfloat16 tests.
|
|
This patch adds some extra tests for the sve2p1 "addqv, andqv, smaxqv,
sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and
fminqv" instructions.
The patch also adds couple of negative testcases, sve2p1-1-bad.d testcase
without "+sve2p1" option and sve2p1-2-bad.d testcase with wrong operands
for sve2p1 instructions.
|
|
The current implementation for the following SVE2p1 instructions add a
constraint in aarch64_opcode_table[] array, so that these instruction
might be immediately preceded in program order by a MOVPRFX instruction.
As per the spec these instruction does not immediately preceded in
program order by a MOVPRFX instruction and to fix this issue, SVE2p1_INSNC
macro is replaced with SVE2p1_INSN macro for the entries of these
instructions in aarch64_opcode_table[] array.
List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv,
eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv.
|
|
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
as mentioned below, for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html
1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
predicated instructions and this issue is fixed in this patch by replacing
"SVE2p1_INSNC" with "SVE2p1_INSN" macro.
2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
by replacing "SVE_Zt" with "SVE_ZtxN".
3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
this patch.
4) In ld1q/st1q the index in the second argument is optional and if index
is xzr and is skipped in the assembly, the index field is ignored by the
disassembler.
Fixing above mentioned issues helps with following:
1) ld1q and st1q first register operand accepts enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
sequence of vector registers.
For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.
I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than two registers in the list, and the register
numbers are monotonically increasing in increments of one.
|
|
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction. Also removed the unused operand
AARCH64_OPND_SVE_Zm_imm4.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
|
|
This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way
2nd operand does the encoding and decoding using the [<imm>] value.
dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index
inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter)
and aarch64_ext_sve_index_imm (extractor) is removed in this patch.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
|
|
This patch fixes the mandatory feature bits in v9.4-a architectures,
by enabling FEAT_SVE2p1 for Armv9.4-A architecture by default.
|
|
PR 20880
|
|
DST__K_RECBEG type debug symbol for the VMS Alpha port.
PR 31873
|
|
In case a DIE contains a linkage name which cannot be demangled and
a source language name (DW_AT_NAME) exists then we want to display this name
instead of the non-demangeable linkage name.
dwarf2_physname returns the linkage name in case the linkage name
cannot be demangled. Before this patch we always set the returned physname
as demangled name. This patch changes this by comparing the value
of physname with the linkage name. Now after this change in case it is equals
to the linkage name and if DW_AT_NAME exists then this is set as the demangled
name otherwise like before still linkage name is used.
For the reproducer, using the test source file added in this change:
"gdb/testsuite/gdb.dwarf2/dw2-wrong-mangled-name.c"
Here is an example of the DWARF where wrong linkage name is emitted by the
compiler for the "func_demangled_test" function:
subprogram {
{MACRO_AT_range {func_demangled_test}}
{linkage_name "_FUNC_WRONG_MANGLED__"}
{name "func_demangled_test"}
{external 1 flag}
}
subprogram {
{MACRO_AT_range {main}}
{external 1 flag}
{name main}
{main_subprogram 1 flag}
}
Before this change for a function having both DIEs DW_AT_name and
DW_AT_LINKAGENAME but with the wrong linkage name info, the backtrace
command shows following:
(gdb) b func_demangled_test
(gdb) r
Breakpoint 1, 0x0000555555555131 in _FUNC_WRONG_MANGLED__ ()
(gdb) backtrace
\#0 0x0000555555555131 in _FUNC_WRONG_MANGLED__ ()
\#1 0x000055555555514a in main ()
After the change now GDB shows the name emitted by DW_AT_NAME:
(gdb) b func_demangled_test
(gdb) r
Breakpoint 1, 0x0000555555555131 in func_demangled_test ()
(gdb) backtrace
\#0 0x0000555555555131 in func_demangled_test ()
\#1 0x000055555555514a in main ()
A new test is added to verify this change.
Approved-By: Tom Tromey <tom@tromey.com>
|
|
|
|
Extend the 64bit DT_RELR support to work on 32bit ELF too. For this
only a few changes were needed in the sizing and creation of the
relr relocations.
|
|
In parse_macro_definition, there's a loop:
...
for (p = body; *p; p++)
if (*p == ' ' || *p == '(')
break;
...
whose post-condition is:
...
gdb_assert (*p == ' ' || *p == '(' || *p == '\0');
...
Consequently, in the following:
...
if (*p == ' ' || *p == '\0')
<BODY1>
else if (*p == '(')
<BODY2>
else
<BODY3>
...
BODY3 is dead code.
Remove it, and get rid of unnecessary indentation by using an early-exit:
....
if (*p == ' ' || *p == '\0')
{
<BODY1>
return;
}
gdb_assert (*p == '(');
<BODY2>
...
Tested on aarch64-linux.
Reviewed-By: Alexandra Petlanova Hajkova <ahajkova@redhat.com>
Approved-By: Tom Tromey <tom@tromey.com>
|
|
|
|
LoongArch defines hardware watchpoint functions for fetch operations.
After the software configures the watchpoints for fetch, the processor
hardware will monitor the access addresses of the fetch operations and
trigger a watchpoint exception when the watchpoint setting conditions
are met.
Hardware watchpoints for fetch operations is used to implement hardware
breakpoint function on LoongArch. Refer to the following document for
hardware breakpoint.
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints
A simple test is as follows:
lihui@bogon:~$ cat test.c
#include <stdio.h>
int a = 0;
int main()
{
printf("start test\n");
a = 1;
printf("a = %d\n", a);
printf("end test\n");
return 0;
}
lihui@bogon:~$ gcc -g test.c -o test
without this patch:
lihui@bogon:~$ gdb test
...
(gdb) start
...
Temporary breakpoint 1, main () at test.c:5
5 printf("start test\n");
(gdb) hbreak 8
No hardware breakpoint support in the target.
with this patch:
lihui@bogon:~$ gdb test
...
(gdb) start
...
Temporary breakpoint 1, main () at test.c:5
5 printf("start test\n");
(gdb) hbreak 8
Hardware assisted breakpoint 2 at 0x1200006ec: file test.c, line 8.
(gdb) c
Continuing.
start test
a = 1
Breakpoint 2, main () at test.c:8
8 printf("end test\n");
(gdb) c
Continuing.
end test
[Inferior 1 (process 25378) exited normally]
Signed-off-by: Hui Li <lihui@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
|
|
LoongArch defines hardware watchpoint functions for load/store
operations. After the software configures the watchpoints for
load/store, the processor hardware will monitor the access
addresses of the load/store operations and trigger watchpoint
exception when the watchpoint setting conditions are met.
After this patch, watch/rwatch/awatch command are supported. Refer to the
following document for hardware watchpoint.
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints
A simple test is as follows:
lihui@bogon:~$ cat test.c
#include <stdio.h>
int a = 0;
int main()
{
printf("start test\n");
a = 1;
printf("a = %d\n", a);
printf("end test\n");
return 0;
}
lihui@bogon:~$ gcc -g test.c -o test
without this patch:
lihui@bogon:~$ gdb test
...
(gdb) start
...
Temporary breakpoint 1, main () at test.c:5
5 printf("start test\n");
(gdb) awatch a
Target does not support this type of hardware watchpoint.
...
with this patch:
lihui@bogon:~$ gdb test
...
(gdb) start
...
Temporary breakpoint 1, main () at test.c:5
5 printf("start test\n");
(gdb) awatch a
Hardware access (read/write) watchpoint 2: a
(gdb) c
Continuing.
start test
Hardware access (read/write) watchpoint 2: a
Old value = 0
New value = 1
main () at test.c:7
7 printf("a = %d\n", a);
(gdb) c
Continuing.
Hardware access (read/write) watchpoint 2: a
Value = 1
0x00000001200006e0 in main () at test.c:7
7 printf("a = %d\n", a);
(gdb) c
Continuing.
a = 1
end test
[Inferior 1 (process 22250) exited normally]
Signed-off-by: Hui Li <lihui@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
|
|
Looking for a type defined locally in a function doesn't work
any more since the introduction of TYPE_DOMAIN:
```
(gdb) python print (gdb.lookup_type ('main()::Local'))
Python Exception <class 'gdb.error'>: No type named main()::Local.
Error occurred in Python: No type named main()::Local.
```
cp_search_static_and_baseclasses was simply missing a check for
SEARCH_TYPE_DOMAIN, now it works again:
```
(gdb) python print (gdb.lookup_type ('main()::Local'))
Local
```
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31922
Approved-By: Tom Tromey <tom@tromey.com>
|
|
This includes:
- FEAT_SME_F8F32 (+sme-f8f32)
- FEAT_SME_F8F16 (+sme-f8f16)
The FP16 addition/subtraction instructions originally added by
FEAT_SME_F16F16 haven't been added to Binutils yet. They are also
required to be enabled if FEAT_SME_F8F16 is present, so they are
included in this patch.
|
|
This includes all the instructions under the following features:
- FEAT_FP8FMA (+fp8fma)
- FEAT_FP8DOT4 (+fp8dot4)
- FEAT_FP8DOT2 (+fp8dot2)
- FEAT_SSVE_FP8FMA (+ssve-fp8fma)
- FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
- FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
|
|
These features will be used to gate instructions that can be enabled by
either of two (or more) different sets of command line feature flags.
This patch add a postprocessing step to the feature parsing code to
set the value of the virtual bits.
|
|
|
|
A few spots in gdb were using htab_traverse. IMO this is almost never
useful and htab_traverse_noresize should be preferred.
|
|
I think that hashtabs should never be obstack-allocated. In the past
this was convenient sometimes, because any new data structure needed a
corresponding cleanup. However, with the switch to C++, resource
management has become much simpler; for example, a local variable can
simply be of type htab_up rather than hashtab_t, and the problem is
solved.
This patch removes hashtab_obstack_allocate to try to prevent this
anti-pattern from being used again.
|
|
The call site hash table is the last hash table using obstack
allocation. In one large (non-public) test case, these hash tables
take a substiantial amount of memory. Some of this memory is wasted
-- whenever the hash table is resized, the old table is not freed.
This patch fixes the problem by changing this hash table to be
heap-allocated. This means that resizing will no longer "leak"
memory.
|
|
It seemed cleaner to me for compunit_symtab to have a
forget_cached_source_info method, then for the objfile to know how to
do this.
|
|
This rearranges symtab so that the private members appear at the end,
and then adds the "private" keyword.
|
|
This renames symtab::fullname to m_fullname and adds new accessor
methods.
|
|
The CU dependency hash table is obstack-allocated, but there's no need
to do this.
|
|
The DIE hash table is currently allocated on an obstack. There's no
need to do this, and I think it's better to simply heap-allocate the
hash table.
This patch implements this. I also removed store_in_ref_table as
well, inlining it into its sole caller, as I think this is clearer.
|
|
PR ld/31906
* libdep_plugin.c (str2vec): Fix bug where null byte was not copied on memmove during quote handling and escaping, causing repeat of the last character in the last argument.
Fix buffer overflow in **res when arguments were separated by `\t` instead of ` `.
Remove handling of the escape character `\`, as it made it impossible to specify paths containing `\`
-- the implementation merely dropped `\`, and was affected by the memmove bug, so this should not be breaking; just single and double quotes are sufficient to deal with white space and quote characters, there is no need for escaping.
Handle syntax errors on unterminated quotes.
Make the parser linear time instead of quadratic.
|
|
|
|
PR 31761
|
|
Introduces instructions for the SME2 lutv2 extension for AArch64. They
are documented in the following document:
* ARM DDI0602
For both luti4 instructions, we introduced an operand called
SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list
for parsing but modified that function so that it can accept operands
without qualifiers and rejects instructions that have operands with
qualifiers but are not supposed to have operands with qualifiers.
For disassembly, we modified print_register_list so that it could
accept register lists without qualifiers.
For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is
similar to SME_Ztx4_STRIDED and we could use existing code for parsing,
encoding, and disassembly.
For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12.
This is a ZT0 register with a bit index encoded in [13:12]. It is
similar to SME_ZT0_INDEX.
We also introduced an iclass named sme_size_12_b so that we can encode
size bits [13:12] correctly when only 'b' is allowed as qualifier.
|
|
Compiling on FreeBSD 13.2 with the default clang version 14.0.5 and top level
configure options --with-python=/usr/local/bin/python3.9 gives this error:
CXX ada-exp.o
./../binutils-gdb/gdb/ada-exp.y:100:8: error: no template named 'unordered_map' in namespace 'std'
std::unordered_map<std::string, std::vector<ada_index_var_operation *>>
~~~~~^
1 error generated.
This change fixes it.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31918
Approved-By: Tom Tromey <tom@tromey.com>
|
