diff options
| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-06-21 19:31:34 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-06-24 16:50:28 +0100 |
| commit | 59b78ab1c16356c2b5a9a1cba40c4029f84ed409 (patch) | |
| tree | 1d3f3d5321777f0aa1337bd64c19cf026b11bd1c | |
| parent | 05f15256d0274b8321eec4cad4273340e1a8521f (diff) | |
| download | gdb-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.zip gdb-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.tar.gz gdb-59b78ab1c16356c2b5a9a1cba40c4029f84ed409.tar.bz2 | |
aarch64: Add FP8 Neon and SVE multiplication instructions
This includes all the instructions under the following features:
- FEAT_FP8FMA (+fp8fma)
- FEAT_FP8DOT4 (+fp8dot4)
- FEAT_FP8DOT2 (+fp8dot2)
- FEAT_SSVE_FP8FMA (+ssve-fp8fma)
- FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
- FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
30 files changed, 1423 insertions, 378 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2bd87d1..88e0e6e 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -820,6 +820,10 @@ vectype_to_qualifier (const struct vector_type_el *vectype) if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH)) { + /* Special case S_2B. */ + if (vectype->type == NT_b && vectype->width == 2) + return AARCH64_OPND_QLF_S_2B; + /* Special case S_4B. */ if (vectype->type == NT_b && vectype->width == 4) return AARCH64_OPND_QLF_S_4B; @@ -1010,7 +1014,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier) succeeds; otherwise return FALSE. Accept only one occurrence of: - 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d + 2b 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d b h s d q */ static bool parse_vector_type_for_operand (aarch64_reg_type reg_type, @@ -1074,6 +1078,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type, if (width != 0 && width * element_size != 64 && width * element_size != 128 && !(width == 2 && element_size == 16) + && !(width == 2 && element_size == 8) && !(width == 4 && element_size == 8)) { first_error_fmt (_ @@ -6334,6 +6339,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: operand->reglane.regno = default_value; break; @@ -6855,6 +6861,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: @@ -6880,6 +6887,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: reg_type = REG_TYPE_V; vector_reg_index: @@ -10681,6 +10689,15 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)}, {"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES}, {"sme-lutv2", AARCH64_FEATURE (SME_LUTv2), AARCH64_FEATURE (SME2)}, + {"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)}, + {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)}, + {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)}, + {"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA), + AARCH64_FEATURES (2, FP8, SME2)}, + {"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4), + AARCH64_FEATURE (SSVE_FP8FMA)}, + {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2), + AARCH64_FEATURE (SSVE_FP8DOT4)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; @@ -10693,7 +10710,12 @@ struct aarch64_virtual_dependency_table }; static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = { - {AARCH64_NO_FEATURES, AARCH64_NO_FEATURES} + {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)}, + {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)}, + {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)}, + {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)}, + {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)}, + {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)}, }; static aarch64_feature_set diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 41a8d7e..a73b6c3 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -197,6 +197,12 @@ automatically cause those extensions to be disabled. @tab Enable floating-point extensions. @item @code{fp8} @tab @tab Enable the Floating Point 8 (FP8) extension. +@item @code{fp8dot2} @tab @code{fp8dot4} + @tab Enable the FP8 2-way dot product instructions. +@item @code{fp8dot4} @tab @code{fp8fma} + @tab Enable the FP8 4-way dot product instructions. +@item @code{fp8fma} @tab @code{fp8} + @tab Enable the FP8 FMA instructions. @item @code{fp16fml} @tab @code{fp16} @tab Enable Armv8.2 16-bit floating-point multiplication variant support. @item @code{fp16} @tab @code{fp} @@ -277,6 +283,12 @@ automatically cause those extensions to be disabled. @tab Enable SME2.1. @item @code{ssbs} @tab @tab Enable Speculative Store Bypassing Safe state read and write. +@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4} + @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}. +@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma} + @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}. +@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8} + @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}. @item @code{sve} @tab @code{fcma} @tab Enable the Scalable Vector Extension. @item @code{sve2} @tab @code{sve} diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d new file mode 100644 index 0000000..1dac59a --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+fp8dot2 +#error_output: fp8-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l new file mode 100644 index 0000000..155c24b --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l @@ -0,0 +1,24 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.4h,v0\.8b,v16\.2b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.4h,v0\.8b,v0\.2b\[8\]' +[^:]*:3: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.8h,v0\.16b,v16\.2b\[0\]' +[^:]*:4: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.8h,v0\.16b,v0\.2b\[8\]' +[^:]*:6: Error: operand mismatch -- `fmlalb v0\.4h,v0\.8b,v0\.8b' +[^:]*:6: Info: did you mean this\? +[^:]*:6: Info: \tfmlalb v0\.8h, v0\.16b, v0\.16b +[^:]*:8: Error: register number out of range 0 to 7 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:9: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:10: Error: register number out of range 0 to 7 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v0\.b\[16\]' +[^:]*:13: Error: operand mismatch -- `fmlallbb v0\.2s,v0\.8b,v0\.8b' +[^:]*:13: Info: did you mean this\? +[^:]*:13: Info: \tfmlallbb v0\.4s, v0\.16b, v0\.16b +[^:]*:15: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:16: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:17: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:18: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:19: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v0\.b\[16\]' +[^:]*:21: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v8\.b\[0\]' +[^:]*:22: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v0\.b\[16\]' + diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s new file mode 100644 index 0000000..1b75cb6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s @@ -0,0 +1,24 @@ +fdot v0.4h, v0.8b, v16.2b[0] +fdot v0.4h, v0.8b, v0.2b[8] +fdot v0.8h, v0.16b, v16.2b[0] +fdot v0.8h, v0.16b, v0.2b[8] + +fmlalb v0.4h, v0.8b, v0.8b + +fmlalb v0.8h, v0.16b, v8.b[0] +fmlalb v0.8h, v0.16b, v0.b[16] +fmlalt v0.8h, v0.16b, v8.b[0] +fmlalt v0.8h, v0.16b, v0.b[16] + +fmlallbb v0.2s, v0.8b, v0.8b + +fmlallbb v0.4s, v0.16b, v8.b[0] +fmlallbb v0.4s, v0.16b, v0.b[16] +fmlallbt v0.4s, v0.16b, v8.b[0] +fmlallbt v0.4s, v0.16b, v0.b[16] +fmlalltb v0.4s, v0.16b, v8.b[0] +fmlalltb v0.4s, v0.16b, v0.b[16] +fmlalltt v0.4s, v0.16b, v8.b[0] +fmlalltt v0.4s, v0.16b, v0.b[16] + + diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.d b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d new file mode 100644 index 0000000..7d740b7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d @@ -0,0 +1,25 @@ +#as: -march=armv8-a+fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e40fc00 fdot v0\.4h, v0\.8b, v0\.8b + *[0-9a-f]+: 0e5dff77 fdot v23\.4h, v27\.8b, v29\.8b + *[0-9a-f]+: 0e53feb9 fdot v25\.4h, v21\.8b, v19\.8b + *[0-9a-f]+: 4e40fc00 fdot v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dff77 fdot v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53feb9 fdot v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0f400000 fdot v0\.4h, v0\.8b, v0\.2b\[0\] + *[0-9a-f]+: 0f500000 fdot v0\.4h, v0\.8b, v0\.2b\[1\] + *[0-9a-f]+: 0f6e0377 fdot v23\.4h, v27\.8b, v14\.2b\[2\] + *[0-9a-f]+: 0f4d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[4\] + *[0-9a-f]+: 0f7d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[7\] + *[0-9a-f]+: 4f400000 fdot v0\.8h, v0\.16b, v0\.2b\[0\] + *[0-9a-f]+: 4f500000 fdot v0\.8h, v0\.16b, v0\.2b\[1\] + *[0-9a-f]+: 4f6e0377 fdot v23\.8h, v27\.16b, v14\.2b\[2\] + *[0-9a-f]+: 4f4d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[4\] + *[0-9a-f]+: 4f7d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.s b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s new file mode 100644 index 0000000..3fff78a --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s @@ -0,0 +1,19 @@ +fdot v0.4h, v0.8b, v0.8b +fdot v23.4h, v27.8b, v29.8b +fdot v25.4h, v21.8b, v19.8b + +fdot v0.8h, v0.16b, v0.16b +fdot v23.8h, v27.16b, v29.16b +fdot v25.8h, v21.16b, v19.16b + +fdot v0.4h, v0.8b, v0.2b[0] +fdot v0.4h, v0.8b, v0.2b[1] +fdot v23.4h, v27.8b, v14.2b[2] +fdot v25.4h, v21.8b, v13.2b[4] +fdot v25.4h, v21.8b, v13.2b[7] + +fdot v0.8h, v0.16b, v0.2b[0] +fdot v0.8h, v0.16b, v0.2b[1] +fdot v23.8h, v27.16b, v14.2b[2] +fdot v25.8h, v21.16b, v13.2b[4] +fdot v25.8h, v21.16b, v13.2b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.d b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d new file mode 100644 index 0000000..bf4632c --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d @@ -0,0 +1,21 @@ +#as: -march=armv8-a+fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0e00fc00 fdot v0\.2s, v0\.8b, v0\.8b + *[0-9a-f]+: 0e1dff77 fdot v23\.2s, v27\.8b, v29\.8b + *[0-9a-f]+: 0e13feb9 fdot v25\.2s, v21\.8b, v19\.8b + *[0-9a-f]+: 4e00fc00 fdot v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dff77 fdot v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13feb9 fdot v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0f000000 fdot v0\.2s, v0\.8b, v0\.4b\[0\] + *[0-9a-f]+: 0f3d0377 fdot v23\.2s, v27\.8b, v29\.4b\[1\] + *[0-9a-f]+: 0f330ab9 fdot v25\.2s, v21\.8b, v19\.4b\[3\] + *[0-9a-f]+: 4f000000 fdot v0\.4s, v0\.16b, v0\.4b\[0\] + *[0-9a-f]+: 4f3d0377 fdot v23\.4s, v27\.16b, v29\.4b\[1\] + *[0-9a-f]+: 4f330ab9 fdot v25\.4s, v21\.16b, v19\.4b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.s b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s new file mode 100644 index 0000000..cfd7283 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s @@ -0,0 +1,15 @@ +fdot v0.2s, v0.8b, v0.8b +fdot v23.2s, v27.8b, v29.8b +fdot v25.2s, v21.8b, v19.8b + +fdot v0.4s, v0.16b, v0.16b +fdot v23.4s, v27.16b, v29.16b +fdot v25.4s, v21.16b, v19.16b + +fdot v0.2s, v0.8b, v0.4b[0] +fdot v23.2s, v27.8b, v29.4b[1] +fdot v25.2s, v21.8b, v19.4b[3] + +fdot v0.4s, v0.16b, v0.4b[0] +fdot v23.4s, v27.16b, v29.4b[1] +fdot v25.4s, v21.16b, v19.4b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.d b/gas/testsuite/gas/aarch64/fp8-simd-fma.d new file mode 100644 index 0000000..c9c8be6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.d @@ -0,0 +1,51 @@ +#as: -march=armv8-a+fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 0ec0fc00 fmlalb v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 0eddff77 fmlalb v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 0ed3feb9 fmlalb v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 4ec0fc00 fmlalt v0\.8h, v0\.16b, v0\.16b + *[0-9a-f]+: 4eddff77 fmlalt v23\.8h, v27\.16b, v29\.16b + *[0-9a-f]+: 4ed3feb9 fmlalt v25\.8h, v21\.16b, v19\.16b + *[0-9a-f]+: 0fc00000 fmlalb v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 0fdd0377 fmlalb v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 0fe702b9 fmlalb v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 0fc70ab9 fmlalb v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 4fc00000 fmlalt v0\.8h, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 4fdd0377 fmlalt v23\.8h, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 4fe702b9 fmlalt v25\.8h, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 4fc70ab9 fmlalt v25\.8h, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 0e00c400 fmlallbb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e1dc777 fmlallbb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e13c6b9 fmlallbb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 0e40c400 fmlallbt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 0e5dc777 fmlallbt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 0e53c6b9 fmlallbt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e00c400 fmlalltb v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e1dc777 fmlalltb v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e13c6b9 fmlalltb v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 4e40c400 fmlalltt v0\.4s, v0\.16b, v0\.16b + *[0-9a-f]+: 4e5dc777 fmlalltt v23\.4s, v27\.16b, v29\.16b + *[0-9a-f]+: 4e53c6b9 fmlalltt v25\.4s, v21\.16b, v19\.16b + *[0-9a-f]+: 2f008000 fmlallbb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f1d8377 fmlallbb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f2782b9 fmlallbb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f078ab9 fmlallbb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 2f408000 fmlallbt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 2f5d8377 fmlallbt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 2f6782b9 fmlallbt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 2f478ab9 fmlallbt v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f008000 fmlalltb v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f1d8377 fmlalltb v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f2782b9 fmlalltb v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f078ab9 fmlalltb v25\.4s, v21\.16b, v7\.b\[8\] + *[0-9a-f]+: 6f408000 fmlalltt v0\.4s, v0\.16b, v0\.b\[0\] + *[0-9a-f]+: 6f5d8377 fmlalltt v23\.4s, v27\.16b, v5\.b\[3\] + *[0-9a-f]+: 6f6782b9 fmlalltt v25\.4s, v21\.16b, v7\.b\[4\] + *[0-9a-f]+: 6f478ab9 fmlalltt v25\.4s, v21\.16b, v7\.b\[8\] diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.s b/gas/testsuite/gas/aarch64/fp8-simd-fma.s new file mode 100644 index 0000000..be79514 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.s @@ -0,0 +1,53 @@ +fmlalb v0.8h, v0.16b, v0.16b +fmlalb v23.8h, v27.16b, v29.16b +fmlalb v25.8h, v21.16b, v19.16b + +fmlalt v0.8h, v0.16b, v0.16b +fmlalt v23.8h, v27.16b, v29.16b +fmlalt v25.8h, v21.16b, v19.16b + +fmlalb v0.8h, v0.16b, v0.b[0] +fmlalb v23.8h, v27.16b, v5.b[3] +fmlalb v25.8h, v21.16b, v7.b[4] +fmlalb v25.8h, v21.16b, v7.b[8] + +fmlalt v0.8h, v0.16b, v0.b[0] +fmlalt v23.8h, v27.16b, v5.b[3] +fmlalt v25.8h, v21.16b, v7.b[4] +fmlalt v25.8h, v21.16b, v7.b[8] + +fmlallbb v0.4s, v0.16b, v0.16b +fmlallbb v23.4s, v27.16b, v29.16b +fmlallbb v25.4s, v21.16b, v19.16b + +fmlallbt v0.4s, v0.16b, v0.16b +fmlallbt v23.4s, v27.16b, v29.16b +fmlallbt v25.4s, v21.16b, v19.16b + +fmlalltb v0.4s, v0.16b, v0.16b +fmlalltb v23.4s, v27.16b, v29.16b +fmlalltb v25.4s, v21.16b, v19.16b + +fmlalltt v0.4s, v0.16b, v0.16b +fmlalltt v23.4s, v27.16b, v29.16b +fmlalltt v25.4s, v21.16b, v19.16b + +fmlallbb v0.4s, v0.16b, v0.b[0] +fmlallbb v23.4s, v27.16b, v5.b[3] +fmlallbb v25.4s, v21.16b, v7.b[4] +fmlallbb v25.4s, v21.16b, v7.b[8] + +fmlallbt v0.4s, v0.16b, v0.b[0] +fmlallbt v23.4s, v27.16b, v5.b[3] +fmlallbt v25.4s, v21.16b, v7.b[4] +fmlallbt v25.4s, v21.16b, v7.b[8] + +fmlalltb v0.4s, v0.16b, v0.b[0] +fmlalltb v23.4s, v27.16b, v5.b[3] +fmlalltb v25.4s, v21.16b, v7.b[4] +fmlalltb v25.4s, v21.16b, v7.b[8] + +fmlalltt v0.4s, v0.16b, v0.b[0] +fmlalltt v23.4s, v27.16b, v5.b[3] +fmlalltt v25.4s, v21.16b, v7.b[4] +fmlalltt v25.4s, v21.16b, v7.b[8] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.d b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d new file mode 100644 index 0000000..d2633aa --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#as: -march=armv8-a+ssve-fp8dot2 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64208400 fdot z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 643d8777 fdot z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643386b9 fdot z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64204400 fdot z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 642d4f77 fdot z23\.h, z27\.b, z5\.b\[3\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 643f4eb9 fdot z25\.h, z21\.b, z7\.b\[7\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.s b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s new file mode 100644 index 0000000..839222e --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s @@ -0,0 +1,9 @@ +fdot z0.h, z0.b, z0.b +fdot z23.h, z27.b, z29.b +movprfx z25, z31 +fdot z25.h, z21.b, z19.b + +fdot z0.h, z0.b, z0.b[0] +fdot z23.h, z27.b, z5.b[3] +movprfx z25, z31 +fdot z25.h, z21.b, z7.b[7] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.d b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d new file mode 100644 index 0000000..ffb8d4c --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d @@ -0,0 +1,18 @@ +#as: -march=armv8-a+sve2+fp8dot4 +#as: -march=armv8-a+ssve-fp8dot4 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64608400 fdot z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 647d8777 fdot z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647386b9 fdot z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64604400 fdot z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 646d4777 fdot z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 647f46b9 fdot z25\.s, z21\.b, z7\.b\[3\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.s b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s new file mode 100644 index 0000000..5cb8227 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s @@ -0,0 +1,9 @@ +fdot z0.s, z0.b, z0.b +fdot z23.s, z27.b, z29.b +movprfx z25, z31 +fdot z25.s, z21.b, z19.b + +fdot z0.s, z0.b, z0.b[0] +fdot z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fdot z25.s, z21.b, z7.b[3] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.d b/gas/testsuite/gas/aarch64/fp8-sve-fma.d new file mode 100644 index 0000000..97eae9e --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.d @@ -0,0 +1,64 @@ +#as: -march=armv8-a+sve2+fp8fma +#as: -march=armv8-a+ssve-fp8fma +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +0+ <\.text>: + *[0-9a-f]+: 64a08800 fmlalb z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd8b77 fmlalb z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b38ab9 fmlalb z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64205000 fmlalb z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64255777 fmlalb z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642f5ab9 fmlalb z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643f5eb9 fmlalb z25\.h, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64208800 fmlallbb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d8b77 fmlallbb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64338ab9 fmlallbb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6420c000 fmlallbb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6425c777 fmlallbb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 642fcab9 fmlallbb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 643fceb9 fmlallbb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64209800 fmlallbt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643d9b77 fmlallbt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64339ab9 fmlallbt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 6460c000 fmlallbt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 6465c777 fmlallbt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 646fcab9 fmlallbt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 647fceb9 fmlallbt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420a800 fmlalltb z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dab77 fmlalltb z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433aab9 fmlalltb z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64a0c000 fmlalltb z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a5c777 fmlalltb z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64afcab9 fmlalltb z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bfceb9 fmlalltb z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 6420b800 fmlalltt z0\.s, z0\.b, z0\.b + *[0-9a-f]+: 643dbb77 fmlalltt z23\.s, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 6433bab9 fmlalltt z25\.s, z21\.b, z19\.b + *[0-9a-f]+: 64e0c000 fmlalltt z0\.s, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64e5c777 fmlalltt z23\.s, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64efcab9 fmlalltt z25\.s, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64ffceb9 fmlalltt z25\.s, z21\.b, z7\.b\[15\] + *[0-9a-f]+: 64a09800 fmlalt z0\.h, z0\.b, z0\.b + *[0-9a-f]+: 64bd9b77 fmlalt z23\.h, z27\.b, z29\.b + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64b39ab9 fmlalt z25\.h, z21\.b, z19\.b + *[0-9a-f]+: 64a05000 fmlalt z0\.h, z0\.b, z0\.b\[0\] + *[0-9a-f]+: 64a55777 fmlalt z23\.h, z27\.b, z5\.b\[1\] + *[0-9a-f]+: 0420bff9 movprfx z25, z31 + *[0-9a-f]+: 64af5ab9 fmlalt z25\.h, z21\.b, z7\.b\[6\] + *[0-9a-f]+: 64bf5eb9 fmlalt z25\.h, z21\.b, z7\.b\[15\] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.s b/gas/testsuite/gas/aarch64/fp8-sve-fma.s new file mode 100644 index 0000000..368e8da --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.s @@ -0,0 +1,65 @@ +fmlalb z0.h, z0.b, z0.b +fmlalb z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalb z25.h, z21.b, z19.b + +fmlalb z0.h, z0.b, z0.b[0] +fmlalb z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalb z25.h, z21.b, z7.b[6] +fmlalb z25.h, z21.b, z7.b[15] + +fmlallbb z0.s, z0.b, z0.b +fmlallbb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbb z25.s, z21.b, z19.b + +fmlallbb z0.s, z0.b, z0.b[0] +fmlallbb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbb z25.s, z21.b, z7.b[6] +fmlallbb z25.s, z21.b, z7.b[15] + +fmlallbt z0.s, z0.b, z0.b +fmlallbt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlallbt z25.s, z21.b, z19.b + +fmlallbt z0.s, z0.b, z0.b[0] +fmlallbt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlallbt z25.s, z21.b, z7.b[6] +fmlallbt z25.s, z21.b, z7.b[15] + +fmlalltb z0.s, z0.b, z0.b +fmlalltb z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltb z25.s, z21.b, z19.b + +fmlalltb z0.s, z0.b, z0.b[0] +fmlalltb z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltb z25.s, z21.b, z7.b[6] +fmlalltb z25.s, z21.b, z7.b[15] + +fmlalltt z0.s, z0.b, z0.b +fmlalltt z23.s, z27.b, z29.b +movprfx z25, z31 +fmlalltt z25.s, z21.b, z19.b + +fmlalltt z0.s, z0.b, z0.b[0] +fmlalltt z23.s, z27.b, z5.b[1] +movprfx z25, z31 +fmlalltt z25.s, z21.b, z7.b[6] +fmlalltt z25.s, z21.b, z7.b[15] + +fmlalt z0.h, z0.b, z0.b +fmlalt z23.h, z27.b, z29.b +movprfx z25, z31 +fmlalt z25.h, z21.b, z19.b + +fmlalt z0.h, z0.b, z0.b[0] +fmlalt z23.h, z27.b, z5.b[1] +movprfx z25, z31 +fmlalt z25.h, z21.b, z7.b[6] +fmlalt z25.h, z21.b, z7.b[15] diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d new file mode 100644 index 0000000..f1d98ee --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d @@ -0,0 +1,2 @@ +#as: -march=armv8-a+sve2+fp8dot2 +#error_output: fp8-sve-mul-illegal.l diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l new file mode 100644 index 0000000..4f09c23 --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:2: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.b,z0\.b\[4\]' +[^:]*:4: Error: z0-z7 expected at operand 3 -- `fdot z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:5: Error: register element index out of range 0 to 7 at operand 3 -- `fdot z0\.h,z0\.b,z0\.b\[8\]' +[^:]*:7: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:8: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:10: Error: z0-z7 expected at operand 3 -- `fmlallbb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:13: Error: z0-z7 expected at operand 3 -- `fmlallbt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:16: Error: z0-z7 expected at operand 3 -- `fmlalltb z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:17: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:19: Error: z0-z7 expected at operand 3 -- `fmlalltt z0\.s,z0\.b,z8\.b\[0\]' +[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt z0\.s,z0\.b,z0\.b\[16\]' +[^:]*:22: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.h,z0\.b,z8\.b\[0\]' +[^:]*:23: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt z0\.h,z0\.b,z0\.b\[16\]' +[^:]*:26: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.s,z0\.b,z0\.b\[0\]' +[^:]*:29: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:32: Warning: predicated instruction expected after `movprfx' -- `fmlalb z25\.h,z0\.b,z0\.b\[0\]' +[^:]*:35: Warning: predicated instruction expected after `movprfx' -- `fmlallbb z25\.s,z0\.b,z0\.b\[0\]' diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s new file mode 100644 index 0000000..c8e3f9d --- /dev/null +++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s @@ -0,0 +1,35 @@ +fdot z0.s, z0.b, z8.b[0] +fdot z0.s, z0.b, z0.b[4] + +fdot z0.h, z0.b, z8.b[0] +fdot z0.h, z0.b, z0.b[8] + +fmlalb z0.h, z0.b, z8.b[0] +fmlalb z0.h, z0.b, z0.b[16] + +fmlallbb z0.s, z0.b, z8.b[0] +fmlallbb z0.s, z0.b, z0.b[16] + +fmlallbt z0.s, z0.b, z8.b[0] +fmlallbt z0.s, z0.b, z0.b[16] + +fmlalltb z0.s, z0.b, z8.b[0] +fmlalltb z0.s, z0.b, z0.b[16] + +fmlalltt z0.s, z0.b, z8.b[0] +fmlalltt z0.s, z0.b, z0.b[16] + +fmlalt z0.h, z0.b, z8.b[0] +fmlalt z0.h, z0.b, z0.b[16] + +movprfx z25.s, p0/m, z31.s +fdot z25.s, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fdot z25.h, z0.b, z0.b[0] + +movprfx z25.h, p0/z, z31.h +fmlalb z25.h, z0.b, z0.b[0] + +movprfx z25.s, p0/m, z31.s +fmlallbb z25.s, z0.b, z0.b[0] diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 20b7a5e..778c40d 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -419,11 +419,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d' @@ -432,11 +432,11 @@ [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]' [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]' -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]' [^ :]+:[0-9]+: Info: did you mean this\? [^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\] -[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h' [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 39d5067..4168082 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -242,6 +242,27 @@ enum aarch64_feature_bit { AARCH64_FEATURE_BRBE, /* SME LUTv2 instructions. */ AARCH64_FEATURE_SME_LUTv2, + /* FP8FMA instructions. */ + AARCH64_FEATURE_FP8FMA, + /* FP8DOT4 instructions. */ + AARCH64_FEATURE_FP8DOT4, + /* FP8DOT2 instructions. */ + AARCH64_FEATURE_FP8DOT2, + /* SSVE FP8FMA instructions. */ + AARCH64_FEATURE_SSVE_FP8FMA, + /* SSVE FP8DOT4 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT4, + /* SSVE FP8DOT2 instructions. */ + AARCH64_FEATURE_SSVE_FP8DOT2, + + /* Virtual features. These are used to gate instructions that are enabled + by either of two (or more) sets of command line flags. */ + /* +fp8fma+sve or +ssve-fp8fma */ + AARCH64_FEATURE_FP8FMA_SVE, + /* +fp8dot4+sve or +ssve-fp8dot4 */ + AARCH64_FEATURE_FP8DOT4_SVE, + /* +fp8dot2+sve or +ssve-fp8dot2 */ + AARCH64_FEATURE_FP8DOT2_SVE, AARCH64_NUM_FEATURES }; @@ -529,7 +550,9 @@ enum aarch64_opnd AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when - qualifier is S_H. */ + qualifier is S_H or S_2B. */ + AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7, + used only with qualifier S_B. */ AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */ AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */ AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */ @@ -751,6 +774,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */ AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ + AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ @@ -868,11 +892,12 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, - /* These type qualifiers have a special meaning in that they mean 4 x 1 byte - or 2 x 2 byte are selected by the instruction. Other than that they have - no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely - for syntactical reasons and is an exception from normal AArch64 - disassembly scheme. */ + /* These type qualifiers have a special meaning in that they mean 2 x 1 byte, + 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that + they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are + here purely for syntactical reasons and is an exception from normal + AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_2B, AARCH64_OPND_QLF_S_4B, AARCH64_OPND_QLF_S_2H, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 8bd9816..94e8218 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -651,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -668,30 +667,31 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 246: - case 254: - case 255: - case 262: - case 263: + case 227: + case 239: + case 243: + case 248: + case 256: + case 257: case 264: case 265: + case 266: + case 267: return aarch64_ins_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 297: - case 300: + case 120: + case 299: + case 302: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -705,18 +705,17 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 302: - return aarch64_ins_reglane (self, info, code, inst, errors); case 39: + case 304: + return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 266: - case 267: - case 282: - case 283: + case 229: + case 232: + case 268: + case 269: case 284: case 285: case 286: @@ -728,22 +727,23 @@ aarch64_insert_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ins_reglist (self, info, code, inst, errors); case 43: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 44: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ins_lut_reglist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -760,15 +760,15 @@ aarch64_insert_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 88: + case 77: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -776,103 +776,103 @@ aarch64_insert_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 268: - case 295: - case 296: + case 210: + case 270: + case 297: case 298: - case 299: + case 300: case 301: - case 306: - case 307: + case 303: + case 308: + case 309: return aarch64_ins_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: + case 56: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ins_limm (self, info, code, inst, errors); case 78: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ins_limm (self, info, code, inst, errors); case 79: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 80: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ins_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ins_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ins_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ins_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ins_barrier (self, info, code, inst, errors); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ins_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ins_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ins_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -887,8 +887,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -896,118 +896,120 @@ aarch64_insert_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 281: + case 202: + case 283: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ins_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ins_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 261: - case 308: - case 309: + case 244: + case 263: case 310: + case 311: + case 312: return aarch64_ins_sve_reglist (self, info, code, inst, errors); - case 243: - case 244: - case 247: - case 248: + case 245: + case 246: case 249: case 250: case 251: - case 260: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); - case 245: case 252: case 253: + case 262: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 247: + case 254: + case 255: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 256: case 258: - case 269: + case 260: + case 271: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 257: case 259: + case 261: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 270: - case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 279: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 280: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 281: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 282: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 303: - case 304: case 305: + case 306: + case 307: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 311: - case 312: case 313: case 314: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 315: + case 316: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 317: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 57fb861..e738bb4 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, { case AARCH64_OPND_QLF_S_4B: case AARCH64_OPND_QLF_S_2H: - /* L:H */ + /* H:L */ assert (reglane_index < 4); insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); break; + case AARCH64_OPND_QLF_S_2B: + /* H:L:M */ + assert (reglane_index < 8); + insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H); + break; default: return false; } @@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + assert (reglane_index < 16); + insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H); + break; case AARCH64_OPND_QLF_S_H: /* H:L:M */ assert (reglane_index < 8); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index fd19b2d..d327422 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -17285,11 +17285,33 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0001xxxxx010xxxxxxxxxxxxx - fdot. */ - return 2473; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x0xxxxxxxxxx + fdot. */ + return 2473; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x1xxxxxxxxxx + fdot. */ + return 3416; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0101xxxxxxxxxxxx + fmlalb. */ + return 3418; + } } else { @@ -17304,21 +17326,32 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx010xx0xxxxxxxxxx - fmlalb. */ - return 2146; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x0xxxxxxxxxx + fmlalb. */ + return 2146; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x1xxxxxxxxxx + fmlalt. */ + return 2148; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx010xx1xxxxxxxxxx + 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 2148; + return 3428; } } else @@ -17337,11 +17370,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0011xxxxx010xxxxxxxxxxxxx - bfdot. */ - return 3066; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx0xxxxxxxxxx + bfdot. */ + return 3066; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx1xxxxxxxxxx + fdot. */ + return 3414; + } } else { @@ -17391,31 +17435,108 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0001xxxxx1x0xxxxxxxxxxxxx - fdot. */ - return 2474; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100000xxxxxxxxxx + fdot. */ + return 2474; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100010xxxxxxxxxx + fmlallbb. */ + return 3419; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1000x1xxxxxxxxxx + fdot. */ + return 3415; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1100xxxxxxxxxxxx + fmlallbb. */ + return 3420; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1x01xxxxxxxxxxxx + fmlallbt. */ + return 3421; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx0xxxxxxxxxx - fmlalb. */ - return 2147; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100000xxxxxxxxxx + fmlalb. */ + return 2147; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100010xxxxxxxxxx + fmlalb. */ + return 3417; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1000x1xxxxxxxxxx + fmlalt. */ + return 2149; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1100xxxxxxxxxxxx + fmlalltb. */ + return 3424; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx1xxxxxxxxxx + 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 2149; + return 3427; } } else @@ -17432,31 +17553,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0011xxxxx1x0xxxxxxxxxxxxx - bfdot. */ - return 3065; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx0xxxxxxxxxx + bfdot. */ + return 3065; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx1xxxxxxxxxx + fdot. */ + return 3413; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx110xxxxxxxxxxxxx + fmlallbt. */ + return 3422; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx0xxxxxxxxxx - bfmlalb. */ - return 3071; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx0xxxxxxxxxx + bfmlalb. */ + return 3071; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx1xxxxxxxxxx + bfmlalt. */ + return 3070; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx1xxxxxxxxxx - bfmlalt. */ - return 3070; + 011001x0111xxxxx110xxxxxxxxxxxxx + fmlalltt. */ + return 3426; } } else @@ -17762,32 +17916,54 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 31) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx0xxxxxxxxxx - fmlslb. */ - return 2151; + x11001x0001xxxxx1010xxxxxxxxxxxx + fmlalltb. */ + return 3423; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx1xxxxxxxxxx - fmlslt. */ - return 2153; + x11001x0001xxxxx1011xxxxxxxxxxxx + fmlalltt. */ + return 3425; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x0x01xxxxx101xxxxxxxxxxxxx - st1h. */ - return 1954; + if (((word >> 31) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx0xxxxxxxxxx + fmlslb. */ + return 2151; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx1xxxxxxxxxx + fmlslt. */ + return 2153; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x0101xxxxx101xxxxxxxxxxxxx + st1h. */ + return 1954; + } } } else @@ -25976,31 +26152,75 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx0001xxxxxxxxxx - dup. */ - return 149; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx00001xxxxxxxxxx + dup. */ + return 149; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx00001xxxxxxxxxx + fmaxnm. */ + return 292; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx00001xxxxxxxxxx + fminnm. */ + return 308; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110010xxxxxxx0001xxxxxxxxxx - fmaxnm. */ - return 292; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x00xxxxxx10001xxxxxxxxxx + fmlallbb. */ + return 3405; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x00xxxxxx10001xxxxxxxxxx + fmlalltb. */ + return 3407; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx0001xxxxxxxxxx - fminnm. */ - return 308; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x10xxxxxx10001xxxxxxxxxx + fmlallbt. */ + return 3406; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x10xxxxxx10001xxxxxxxxxx + fmlalltt. */ + return 3408; + } } } } @@ -26209,31 +26429,75 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx1111xxxxxxxxxx - umov. */ - return 152; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx01111xxxxxxxxxx + umov. */ + return 152; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx01111xxxxxxxxxx + frecps. */ + return 304; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx01111xxxxxxxxxx + frsqrts. */ + return 316; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 0x001110010xxxxxxx1111xxxxxxxxxx - frecps. */ - return 304; + 0x001110x00xxxxxx11111xxxxxxxxxx + fdot. */ + return 3397; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx1111xxxxxxxxxx - frsqrts. */ - return 316; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx11111xxxxxxxxxx + fdot. */ + return 3399; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110110xxxxxx11111xxxxxxxxxx + fmlalb. */ + return 3401; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110110xxxxxx11111xxxxxxxxxx + fmlalt. */ + return 3402; + } + } } } } @@ -31672,21 +31936,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3013; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111100xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3398; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3013; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3017; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3017; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111101xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3400; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111111xxxxxx0000x0xxxxxxxxxx + fmlalb. */ + return 3403; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111111xxxxxx0000x0xxxxxxxxxx + fmlalt. */ + return 3404; + } + } } } else @@ -32216,21 +32524,65 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3015; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111100xxxxxx1000x0xxxxxxxxxx + fmlallbb. */ + return 3409; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111100xxxxxx1000x0xxxxxxxxxx + fmlalltb. */ + return 3411; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3015; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3019; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3019; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0101111x1xxxxxx1000x0xxxxxxxxxx + fmlallbt. */ + return 3410; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1101111x1xxxxxx1000x0xxxxxxxxxx + fmlalltt. */ + return 3412; + } } } } @@ -33681,10 +34033,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -33698,30 +34049,31 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 246: - case 254: - case 255: - case 262: - case 263: + case 227: + case 239: + case 243: + case 248: + case 256: + case 257: case 264: case 265: + case 266: + case 267: return aarch64_ext_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 297: - case 300: + case 120: + case 299: + case 302: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33740,18 +34092,17 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 302: - return aarch64_ext_reglane (self, info, code, inst, errors); case 39: + case 304: + return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 266: - case 267: - case 282: - case 283: + case 229: + case 232: + case 268: + case 269: case 284: case 285: case 286: @@ -33763,22 +34114,23 @@ aarch64_extract_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ext_reglist (self, info, code, inst, errors); case 43: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 44: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ext_lut_reglist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -33795,16 +34147,16 @@ aarch64_extract_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 87: + case 77: case 88: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -33812,105 +34164,105 @@ aarch64_extract_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 268: - case 295: - case 296: + case 210: + case 270: + case 297: case 298: - case 299: + case 300: case 301: - case 306: - case 307: + case 303: + case 308: + case 309: return aarch64_ext_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 56: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 57: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ext_limm (self, info, code, inst, errors); case 78: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ext_limm (self, info, code, inst, errors); case 79: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 80: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ext_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ext_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ext_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ext_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ext_barrier (self, info, code, inst, errors); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ext_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ext_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ext_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -33925,8 +34277,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -33934,119 +34286,121 @@ aarch64_extract_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 281: + case 202: + case 283: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ext_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ext_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 261: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); - case 243: case 244: - case 247: - case 248: + case 263: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); + case 245: + case 246: case 249: case 250: case 251: - case 260: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); - case 245: case 252: case 253: + case 262: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 247: + case 254: + case 255: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 256: case 258: - case 269: + case 260: + case 271: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 257: case 259: + case 261: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 270: - case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 279: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 280: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 281: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 282: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 303: - case 304: case 305: + case 306: + case 307: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 308: - case 309: case 310: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 311: case 312: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 313: case 314: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 315: + case 316: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 317: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 045af49..6098204 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; break; + case AARCH64_OPND_QLF_S_2B: + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + break; default: return false; } @@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return 0; switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, + FLD_imm3_19); + info->reglane.regno &= 0x7; + break; + case AARCH64_OPND_QLF_S_H: + case AARCH64_OPND_QLF_S_2B: if (info->type == AARCH64_OPND_Em16) { /* h:l:m */ @@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, } break; case AARCH64_OPND_QLF_S_S: + case AARCH64_OPND_QLF_S_4B: /* h:l */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 71f6824..5e1bd1c 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -63,6 +63,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, @@ -258,6 +259,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index b704673..b42b809 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -310,6 +310,7 @@ const aarch64_field fields[] = { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ + { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -367,6 +368,7 @@ const aarch64_field fields[] = { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ + { 19, 3 }, /* imm3_19: general immediate in bits [21:19]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ @@ -818,6 +820,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {4, 1, 0x2, "s", OQK_OPD_VARIANT}, {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, + {2, 1, 0x0, "2b", OQK_OPD_VARIANT}, {4, 1, 0x0, "4b", OQK_OPD_VARIANT}, {4, 1, 0x0, "2h", OQK_OPD_VARIANT}, @@ -1816,6 +1819,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); @@ -3234,12 +3238,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 01 0:Rm 10 M:Rm 11 RESERVED */ - if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H + if (type == AARCH64_OPND_Em16 + && (qualifier == AARCH64_OPND_QLF_S_H + || qualifier == AARCH64_OPND_QLF_S_2B) && !value_in_range_p (opnd->reglane.regno, 0, 15)) { set_regno_out_of_range_error (mismatch_detail, idx, 0, 15); return 0; } + if (type == AARCH64_OPND_Em8 + && !value_in_range_p (opnd->reglane.regno, 0, 7)) + { + set_regno_out_of_range_error (mismatch_detail, idx, 0, 7); + return 0; + } break; case AARCH64_OPND_CLASS_MODIFIED_REG: @@ -4127,6 +4139,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: snprintf (buf, size, "%s[%s]", style_reg (styler, "v%d.%s", opnd->reglane.regno, @@ -4254,6 +4267,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8804e7c..ba6b407 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -114,6 +114,7 @@ enum aarch64_field_kind FLD_SVE_i3h3, FLD_SVE_i3l, FLD_SVE_i3l2, + FLD_SVE_i4l2, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, @@ -171,6 +172,7 @@ enum aarch64_field_kind FLD_imm3_12, FLD_imm3_14, FLD_imm3_15, + FLD_imm3_19, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5876592..da17fa3 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2218,6 +2218,10 @@ { \ QLF3(S_S,S_B,S_B), \ } +#define OP_SVE_VVV_H_B \ +{ \ + QLF3(S_H,S_B,S_B), \ +} #define OP_SVE_VVV_Q_D \ { \ QLF3(S_Q,S_D,S_D), \ @@ -2467,6 +2471,20 @@ QLF3(V_4S, V_16B, S_4B),\ } +/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.8B. */ +#define QL_V3DOTH \ +{ \ + QLF3(V_4H, V_8B, V_8B), \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.2B[<index>]. */ +#define QL_V2DOTH \ +{ \ + QLF3(V_4H, V_8B, S_2B),\ + QLF3(V_8H, V_16B, S_2B),\ +} + /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D . */ #define QL_SHA512UPT \ { \ @@ -2533,6 +2551,30 @@ QLF3(V_4S, V_4H, S_H),\ } +/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.16B. */ +#define QL_V3FML8H \ +{ \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.B. */ +#define QL_V2FML8H \ +{ \ + QLF3(V_8H, V_16B, S_B),\ +} + +/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B. */ +#define QL_V3FMLL4S \ +{ \ + QLF3(V_4S, V_16B, V_16B),\ +} + +/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.B. */ +#define QL_V2FMLL4S \ +{ \ + QLF3(V_4S, V_16B, S_B),\ +} + /* e.g. RMIF <Xn>, #<shift>, #<mask>. */ #define QL_RMIF \ { \ @@ -2768,6 +2810,18 @@ static const aarch64_feature_set aarch64_feature_brbe = AARCH64_FEATURE (BRBE); static const aarch64_feature_set aarch64_feature_sme_lutv2 = AARCH64_FEATURES (3, SME_LUTv2, SME2, SME2p1); +static const aarch64_feature_set aarch64_feature_fp8fma = + AARCH64_FEATURE (FP8FMA); +static const aarch64_feature_set aarch64_feature_fp8dot4 = + AARCH64_FEATURE (FP8DOT4); +static const aarch64_feature_set aarch64_feature_fp8dot2 = + AARCH64_FEATURE (FP8DOT2); +static const aarch64_feature_set aarch64_feature_fp8fma_sve = + AARCH64_FEATURES (2, FP8FMA_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot4_sve = + AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot2_sve = + AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2846,6 +2900,12 @@ static const aarch64_feature_set aarch64_feature_sme_lutv2 = #define LUT_SVE2 &aarch64_feature_lut_sve2 #define BRBE &aarch64_feature_brbe #define LUTv2_SME2 &aarch64_feature_sme_lutv2 +#define FP8FMA &aarch64_feature_fp8fma +#define FP8DOT4 &aarch64_feature_fp8dot4 +#define FP8DOT2 &aarch64_feature_fp8dot2 +#define FP8FMA_SVE &aarch64_feature_fp8fma_sve +#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve +#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3049,6 +3109,18 @@ static const aarch64_feature_set aarch64_feature_sme_lutv2 = #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ FLAGS, 0, 0, NULL } +#define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6639,6 +6711,41 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0), LUTv2_SME2_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0), LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0), + /* FP8 multiplication AdvSIMD instructions. */ + FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0f400000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_V2DOTH, F_SIZEQ), + FP8FMA_INSN("fmlalb", 0x0ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalb", 0x0fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlallbb", 0x0e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x0e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x4e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x4e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbb", 0x2f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x2f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x6f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x6f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + + /* FP8 multiplication SVE instructions. */ + FP8DOT4_SVE_INSNC("fdot", 0x64608400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT4_SVE_INSNC("fdot", 0x64604400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64208400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64204400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64a08800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64205000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x64208800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x6420c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x64209800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x6460c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x6420a800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x64a0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x6420b800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x64e0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6715,6 +6822,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element") \ Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ "a SIMD vector element limited to V0-V15") \ + Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ + "a SIMD vector element limited to V0-V7") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \ @@ -7138,6 +7247,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \ + 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ "an indexed SVE vector register") \ |