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AgeCommit message (Expand)AuthorFilesLines
2022-12-22x86: correct/improve TSX controlsJan Beulich4-5/+38
2022-12-22x86: add dependencies on SVMEJan Beulich3-11/+53
2022-12-22x86: add dependencies on VMXJan Beulich3-5/+36
2022-12-22x86: correct XSAVE* dependenciesJan Beulich2-8/+10
2022-12-22x86: correct dependencies of a few AVX512 sub-featuresJan Beulich3-16/+16
2022-12-22x86: rework noavx512-1 testcaseJan Beulich3-587/+415
2022-12-22x86: add dependencies on AVX2Jan Beulich3-11/+33
2022-12-22x86: correct SSE dependenciesJan Beulich3-52/+96
2022-12-22x86: correct what gets disabled by certain ".arch .no*"Jan Beulich1-18/+18
2022-12-22x86: re-work ISA extension dependency handlingJan Beulich3-1024/+910
2022-12-21sim: mips: match target on cpu settingsMike Frysinger2-26/+26
2022-12-21sim: mips: move fpu bitsize defines to top-level configureMike Frysinger8-71/+44
2022-12-21sim: mips: move bitsize defines to top-level configureMike Frysinger8-99/+48
2022-12-21sim: mips: move subtarget defines to top-level configureMike Frysinger8-43/+68
2022-12-21sim: mips: always resolve active bfd mach dynamicallyMike Frysinger3-106/+3
2022-12-21sim: hw-config.h: move generation to top-levelMike Frysinger3-30/+54
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger16-127/+190
2022-12-21sim: build: hoist lists of common objects upMike Frysinger4-131/+167
2022-12-22Automatic date update in version.inGDB Administrator1-1/+1
2022-12-22PR29925, Memory leak in find_abstract_instanceAlan Modra1-12/+19
2022-12-21Fix compiling of top.cAndrew Pinski1-1/+0
2022-12-21Use toplevel configure for GMP and MPFR for gdbAndrew Pinski12-1094/+142
2022-12-21gdb/c++: validate 'using' directives based on the current lineBruno Larsen6-9/+95
2022-12-21Updated Romanian translation for the BFD sub-directory.Nick Clifton2-1970/+2073
2022-12-21Fix an attempt to allocate an unreasonably large amount of memory when parsin...Nick Clifton2-1/+9
2022-12-21Keep the .drectve section when performing a relocateable link.Nick Clifton3-2/+9
2022-12-21x86: rename CheckRegSize to CheckOperandSizeJan Beulich4-513/+513
2022-12-21gprofng/testsuite: restrict testing to native configurationsJan Beulich1-0/+7
2022-12-21enable-non-contiguous-regions warningsAlan Modra18-66/+59
2022-12-21PR29922, SHT_NOBITS section avoids section size sanity checkAlan Modra1-3/+9
2022-12-21sim: fully merge sim_cpu_base into sim_cpuMike Frysinger1-26/+19
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger29-66/+1
2022-12-21sim: or1k: invert sim_cpu storageMike Frysinger5-30/+43
2022-12-21sim: m32r: invert sim_cpu storageMike Frysinger5-14/+10
2022-12-21sim: lm32: invert sim_cpu storageMike Frysinger3-12/+7
2022-12-21sim: iq2000: invert sim_cpu storageMike Frysinger3-11/+7
2022-12-21sim: frv: invert sim_cpu storageMike Frysinger3-23/+18
2022-12-21sim: cris: invert sim_cpu storageMike Frysinger6-239/+244
2022-12-21sim: bpf: invert sim_cpu storageMike Frysinger3-7/+13
2022-12-21sim: cgen: prep for inverting sim_cpu storageMike Frysinger2-0/+15
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-21sim: pru: invert sim_cpu storageMike Frysinger3-8/+31
2022-12-21sim: example-synacor: invert sim_cpu storageMike Frysinger3-37/+47
2022-12-21sim: h8300: invert sim_cpu storageMike Frysinger2-34/+36
2022-12-21sim: m68hc11: invert sim_cpu storageMike Frysinger10-354/+446
2022-12-21sim: mips: invert sim_cpu storageMike Frysinger2-73/+90
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger3-20/+23
2022-12-21sim: mcore: invert sim_cpu storageMike Frysinger2-27/+41
2022-12-21sim: aarch64: invert sim_cpu storageMike Frysinger5-108/+152
2022-12-21sim: microblaze: invert sim_cpu storageMike Frysinger3-8/+8
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