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2021-05-29sim: leverage gnulibMike Frysinger8-3/+44
We use getline, so leverage gnulib to provide fallback implementation.
2021-05-29Re: readelf and objdump helpAlan Modra2-4/+8
Fix a last-minute change.. * objdump (usage): Add missing \n.
2021-05-29Fix InlinedFrameDecorator exampleHannes Domani2-1/+5
Argument fobj was only available in the constructor. gdb/doc/ChangeLog: 2021-05-29 Hannes Domani <ssbssa@yahoo.de> * python.texi (Writing a Frame Filter): Fix example.
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra7-1635/+1755
opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-29readelf and objdump helpAlan Modra3-132/+254
Splitting up help strings makes it more likely that at least some of the help translation survives adding new options. * readelf.c (parse_args): Call dwarf_select_sections_all on --debug-dump without optarg. (usage): Associate -w and --debug-dump options closely. Split up help message. Remove extraneous blank lines around ctf help. * objdump.c (usage): Similarly.
2021-05-28sim: bfin: fix the otp fix fixMike Frysinger2-2/+6
Need to shift the upper 32-bits and not just combine directly with the lower 32-bits.
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2-66/+73
Group legacy instructions using the COP0, COP2, COP3 opcodes together and by their coprocessor number, and move them towards the end of the opcode table. No functional change. With the addition of explicit ISA exclusions this is maybe not strictly necessary anymore as the individual legacy instructions are not supposed to match ISA levels or CPU implementations that have discarded them or replaced with a new instruction each, but let's not have them scattered randomly across blocks of unrelated instruction sets where someone chose to put them previously. Perhaps they could be put back in alphabetical order in the main instruction block, but let's leave it for another occasion. opcodes/ * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, COP3 opcode instructions.
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki54-0/+7580
Add tests for the generic C0, C1, C2, C3 coprocessor instructions. gas/ * testsuite/gas/mips/c0.d: New test. * testsuite/gas/mips/mips1@c0.d: New test. * testsuite/gas/mips/mips2@c0.d: New test. * testsuite/gas/mips/mips3@c0.d: New test. * testsuite/gas/mips/mips4@c0.d: New test. * testsuite/gas/mips/mips5@c0.d: New test. * testsuite/gas/mips/mips32@c0.d: New test. * testsuite/gas/mips/mips64@c0.d: New test. * testsuite/gas/mips/r3000@c0.d: New test. * testsuite/gas/mips/r3900@c0.d: New test. * testsuite/gas/mips/r4000@c0.d: New test. * testsuite/gas/mips/vr5400@c0.d: New test. * testsuite/gas/mips/r5900@c0.d: New test. * testsuite/gas/mips/sb1@c0.d: New test. * testsuite/gas/mips/interaptiv-mr2@c0.d: New test. * testsuite/gas/mips/octeon@c0.d: New test. * testsuite/gas/mips/xlr@c0.d: New test. * testsuite/gas/mips/c1.d: New test. * testsuite/gas/mips/mips1@c1.d: New test. * testsuite/gas/mips/mips2@c1.d: New test. * testsuite/gas/mips/mips3@c1.d: New test. * testsuite/gas/mips/mips4@c1.d: New test. * testsuite/gas/mips/mips5@c1.d: New test. * testsuite/gas/mips/mips32@c1.d: New test. * testsuite/gas/mips/mips64@c1.d: New test. * testsuite/gas/mips/mipsr6@c1.d: New test. * testsuite/gas/mips/r3000@c1.d: New test. * testsuite/gas/mips/r3900@c1.d: New test. * testsuite/gas/mips/r4000@c1.d: New test. * testsuite/gas/mips/vr5400@c1.d: New test. * testsuite/gas/mips/r5900@c1.d: New test. * testsuite/gas/mips/sb1@c1.d: New test. * testsuite/gas/mips/interaptiv-mr2@c1.d: New test. * testsuite/gas/mips/octeon@c1.d: New test. * testsuite/gas/mips/xlr@c1.d: New test. * testsuite/gas/mips/c2.d: New test. * testsuite/gas/mips/vr5400@c2.d: New test. * testsuite/gas/mips/r5900@c2.d: New test. * testsuite/gas/mips/octeon@c2.d: New test. * testsuite/gas/mips/c3.d: New test. * testsuite/gas/mips/mips1@c3.d: New test. * testsuite/gas/mips/mips2@c3.d: New test. * testsuite/gas/mips/mips32@c3.d: New test. * testsuite/gas/mips/r3000@c3.d: New test. * testsuite/gas/mips/r3900@c3.d: New test. * testsuite/gas/mips/c0.l: New test stderr output. * testsuite/gas/mips/c2.l: New test stderr output. * testsuite/gas/mips/c3.l: New test stderr output. * testsuite/gas/mips/c0.s: New test source. * testsuite/gas/mips/c1.s: New test source. * testsuite/gas/mips/c2.s: New test source. * testsuite/gas/mips/c3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki8-7/+39
Verify that the RFE instruction is not only accepted where supported, but rejected where it is not as well. gas/ * testsuite/gas/mips/mips.exp: Run RFE test across all ISAs. * testsuite/gas/mips/rfe.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@rfe.d: New test. * testsuite/gas/mips/mips2@rfe.d: New test. * testsuite/gas/mips/r3000@rfe.d: New test. * testsuite/gas/mips/r3900@rfe.d: New test. * testsuite/gas/mips/rfe.l: New test stderr output.
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki96-467/+1646
Verify that individual coprocessor instructions are not only accepted where supported, but rejected where they are not as well. gas/ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all ISAs. * testsuite/gas/mips/cp0b.d: Update for ISA exclusions. * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp0c.d: Update for ISA exclusions. * testsuite/gas/mips/cp0m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3.d: Update for ISA exclusions. * testsuite/gas/mips/cp3b.d: Update for ISA exclusions. * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp3m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3d.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0b.d: New test. * testsuite/gas/mips/mips3@cp0b.d: New test. * testsuite/gas/mips/r3000@cp0b.d: New test. * testsuite/gas/mips/r3900@cp0b.d: New test. * testsuite/gas/mips/r4000@cp0b.d: New test. * testsuite/gas/mips/r5900@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0bl.d: New test. * testsuite/gas/mips/mips3@cp0bl.d: New test. * testsuite/gas/mips/r3900@cp0bl.d: New test. * testsuite/gas/mips/r4000@cp0bl.d: New test. * testsuite/gas/mips/r5900@cp0bl.d: New test. * testsuite/gas/mips/mips1@cp0c.d: New test. * testsuite/gas/mips/mips2@cp0c.d: New test. * testsuite/gas/mips/mips3@cp0c.d: New test. * testsuite/gas/mips/mips4@cp0c.d: New test. * testsuite/gas/mips/mips5@cp0c.d: New test. * testsuite/gas/mips/r3000@cp0c.d: New test. * testsuite/gas/mips/r3900@cp0c.d: New test. * testsuite/gas/mips/r4000@cp0c.d: New test. * testsuite/gas/mips/vr5400@cp0c.d: New test. * testsuite/gas/mips/r5900@cp0c.d: New test. * testsuite/gas/mips/mips1@cp0m.d: New test. * testsuite/gas/mips/r3000@cp0m.d: New test. * testsuite/gas/mips/octeon@cp2.d: New test. * testsuite/gas/mips/mipsr6@cp2b.d: New test. * testsuite/gas/mips/vr5400@cp2b.d: New test. * testsuite/gas/mips/octeon@cp2b.d: New test. * testsuite/gas/mips/mips1@cp2bl.d: New test. * testsuite/gas/mips/mipsr6@cp2bl.d: New test. * testsuite/gas/mips/r3000@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2bl.d: New test. * testsuite/gas/mips/octeon@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2m.d: New test. * testsuite/gas/mips/r5900@cp2m.d: New test. * testsuite/gas/mips/octeon@cp2m.d: New test. * testsuite/gas/mips/mips1@cp2d.d: New test. * testsuite/gas/mips/r3000@cp2d.d: New test. * testsuite/gas/mips/r3900@cp2d.d: New test. * testsuite/gas/mips/vr5400@cp2d.d: New test. * testsuite/gas/mips/r5900@cp2d.d: New test. * testsuite/gas/mips/octeon@cp2d.d: New test. * testsuite/gas/mips/mips1@cp2-64.d: New test. * testsuite/gas/mips/mips2@cp2-64.d: New test. * testsuite/gas/mips/mips32@cp2-64.d: New test. * testsuite/gas/mips/mips32r2@cp2-64.d: New test. * testsuite/gas/mips/mips32r3@cp2-64.d: New test. * testsuite/gas/mips/mips32r5@cp2-64.d: New test. * testsuite/gas/mips/mips32r6@cp2-64.d: New test. * testsuite/gas/mips/r3000@cp2-64.d: New test. * testsuite/gas/mips/r3900@cp2-64.d: New test. * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test. * testsuite/gas/mips/mips1@cp3.d: New test. * testsuite/gas/mips/mips2@cp3.d: New test. * testsuite/gas/mips/mips32@cp3.d: New test. * testsuite/gas/mips/r3000@cp3.d: New test. * testsuite/gas/mips/r3900@cp3.d: New test. * testsuite/gas/mips/mips1@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3b.d: New test. * testsuite/gas/mips/mips32@cp3b.d: New test. * testsuite/gas/mips/r3000@cp3b.d: New test. * testsuite/gas/mips/r3900@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3bl.d: New test. * testsuite/gas/mips/mips32@cp3bl.d: New test. * testsuite/gas/mips/r3900@cp3bl.d: New test. * testsuite/gas/mips/mips1@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3m.d: New test. * testsuite/gas/mips/r3000@cp3m.d: New test. * testsuite/gas/mips/r3900@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3d.d: New test. * testsuite/gas/mips/cp0b.l: New test stderr output. * testsuite/gas/mips/cp0bl.l: New test stderr output. * testsuite/gas/mips/cp0c.l: New test stderr output. * testsuite/gas/mips/cp0m.l: New test stderr output. * testsuite/gas/mips/cp2.l: New test stderr output. * testsuite/gas/mips/cp2-64.l: New test stderr output. * testsuite/gas/mips/cp2b.l: New test stderr output. * testsuite/gas/mips/cp2bl.l: New test stderr output. * testsuite/gas/mips/cp2m.l: New test stderr output. * testsuite/gas/mips/cp2d.l: New test stderr output. * testsuite/gas/mips/cp3.l: New test stderr output. * testsuite/gas/mips/cp3b.l: New test stderr output. * testsuite/gas/mips/cp3bl.l: New test stderr output. * testsuite/gas/mips/cp3m.l: New test stderr output. * testsuite/gas/mips/cp3d.l: New test stderr output.
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki5-53/+114
Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2-4/+5
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2] with the LDC3 and SDC3 instructions having been replaced with LD and SD instructions respectively and therefore the doubleword move instructions from and to that coprocessor have never materialized (for 32-bit ISAs coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove the DMFC3 and DMTC3 instructions from the opcode table then to avoid confusion. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 317 opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" entries and associated comments.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki16-0/+215
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across the relevant ISA levels. Omit CP1 branches, covered elsewhere. gas/ * testsuite/gas/mips/cp0b.d: New test. * testsuite/gas/mips/cp0bl.d: New test. * testsuite/gas/mips/cp2b.d: New test. * testsuite/gas/mips/micromips@cp2b.d: New test. * testsuite/gas/mips/cp2bl.d: New test. * testsuite/gas/mips/micromips@cp2bl.d: New test. * testsuite/gas/mips/cp3b.d: New test. * testsuite/gas/mips/cp3bl.d: New test. * testsuite/gas/mips/cp0b.s: New test source. * testsuite/gas/mips/cp0bl.s: New test source. * testsuite/gas/mips/cp2b.s: New test source. * testsuite/gas/mips/cp2bl.s: New test source. * testsuite/gas/mips/cp3b.s: New test source. * testsuite/gas/mips/cp3bl.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki6-2/+34
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2-19/+24
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and handle the exclusion for any ISA levels properly in `opcode_is_member'. Flatten the structure of the `if' statements there. No functional change for the existing opcode tables. include/ * opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA exclusion. (opcode_is_member): Handle ISA level exclusion.
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2-4/+27
In preparation for the next change factor out code for ISA matching against instruction flags used in MIPS opcode tables, similarly to how CPU matching is already done. No functional change, though for clarity split the single `if' statement into multiple ones and use temporaries rather than repeated expressions. include/ * opcode/mips.h (isa_is_member): New inline function, factored out from... (opcode_is_member): ... here.
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki11-54/+94
The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki27-0/+2180
Cover basic CP0, CP2, CP3 move, load and store instructions across the relevant ISA levels. Omit CP0 move and CP1 instructions as they are covered elsewhere. gas/ * testsuite/gas/mips/cp0c.d: New test. * testsuite/gas/mips/cp0m.d: New test. * testsuite/gas/mips/r3900@cp0m.d: New test. * testsuite/gas/mips/cp2.d: New test. * testsuite/gas/mips/micromips@cp2.d: New test. * testsuite/gas/mips/cp2m.d: New test. * testsuite/gas/mips/mipsr6@cp2m.d: New test. * testsuite/gas/mips/micromips@cp2m.d: New test. * testsuite/gas/mips/cp2d.d: New test. * testsuite/gas/mips/mipsr6@cp2d.d: New test. * testsuite/gas/mips/micromips@cp2d.d: New test. * testsuite/gas/mips/cp2-64.d: New test. * testsuite/gas/mips/micromips@cp2-64.d: New test. * testsuite/gas/mips/cp3.d: New test. * testsuite/gas/mips/cp3m.d: New test. * testsuite/gas/mips/cp3d.d: New test. * testsuite/gas/mips/cp0c.s: New test source. * testsuite/gas/mips/cp0m.s: New test source. * testsuite/gas/mips/cp2.s: New test source. * testsuite/gas/mips/cp2m.s: New test source. * testsuite/gas/mips/cp2d.s: New test source. * testsuite/gas/mips/cp2-64.s: New test source. * testsuite/gas/mips/cp3.s: New test source. * testsuite/gas/mips/cp3m.s: New test source. * testsuite/gas/mips/cp3d.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki11-25/+73
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki5-1/+68
The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
2021-05-29MIPS/binutils/testsuite: Fix XPA and Virtualization ASE casesMaciej W. Rozycki5-4/+12
Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE instruction handling") and explicitly use the `mips:3000' machine for disassembly across the XPA base and XPA Virtualization ASE test cases, providing actual coverage for the `virt' and `xpa' disassembler options and removing failures for targets that default to those ASEs enabled: mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 This is because the test cases rely on these ASEs being disabled for disassembly by default and expect instructions belonging to these ASEs not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test case passes regardless, but we want it to verify the explicit options do work, so use the `mips:3000' machine to set the defaults there as well. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000' machine for disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki4-6/+15
In the operand handling rewrite made for the MIPS disassembler with commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki9-322/+337
The DMTC1 instruction operates on a floating-point general register as its second operand, however in the disassembly of the microMIPS encoding a floating-point control register is shown instead. This is due to an incorrect ordering of the two "dmtc1" entries in the opcode table, which gives precedence to one using the `G' aka coprocessor format over one using the `S' or floating-point register format. The coprocessor format, or OP_REG_COPRO, is used so that GAS supports referring to FPRs by their numbers in assembly, such as $0, $1, etc. however in the case of CP1/FPU it is also used by the disassembler to decode those numbers to the names of corresponding control registers. This in turn causes nonsensical disassembly such as: dmtc1 a1,c1_fir in a reference to $f0. It has been like this ever since microMIPS ISA support has been added. Correct the ordering of the two entries then by swapping them with each other, making disassembly output consistent with the regular MIPS DMTC1 instruction as well all the remaining CP1 move instructions. Adjust all the test cases affected accordingly. opcodes/ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" entries with each other. gas/ * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
2021-05-29MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1Maciej W. Rozycki2-4/+11
Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"), <https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR. While the register referred by its number is $31 in both cases, these instructions operate on the floating-point control register file rather than general-purpose registers. gas/ * config/tc-mips.c (FCSR): New macro. (macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
2021-05-29Automatic date update in version.inGDB Administrator1-1/+1
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu16-96/+70
The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-28sim: h8300 add special case test.Yoshinori Sato10-16/+520
* addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>. * andb.s: Likewise. * cmpb.s: Likewise. * orb.s: Likewise. * subb.s: Likewise. * xorb.s: Likewise. * movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg> @reg+,@reg+ / @-reg,@-reg. * movw.s: Likewise. * movl.s: Likewise.
2021-05-28sim: h8300 Fixed different behavior in preinc/predec.Yoshinori Sato3-3/+60
* sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC. * compile.c (decode): Rewrite oprand type for specific case. (fetch_1): Add handling OP_REG_DEC and OP_REG_INC. (step_once): Fix operand fetch order.
2021-05-28Automatic date update in version.inGDB Administrator1-1/+1
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner5-0/+19
opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.
2021-05-27gdb: fix tab after space indentation issuesSimon Marchi46-138/+142
I spotted some indentation issues where we had some spaces followed by tabs at beginning of line, that I wanted to fix. So while at it, I did a quick grep to find and fix all I could find. gdb/ChangeLog: * Fix tab after space indentation issues throughout. Change-Id: I1acb414dd9c593b474ae2b8667496584df4316fd
2021-05-27gdb: fix some indentation issuesSimon Marchi29-698/+704
I wrote a small script to spot a pattern of indentation mistakes I saw happened in breakpoint.c. And while at it I ran it on all files and fixed what I found. No behavior changes intended, just indentation and addition / removal of curly braces. gdb/ChangeLog: * Fix some indentation mistakes throughout. gdbserver/ChangeLog: * Fix some indentation mistakes throughout. Change-Id: Ia01990c26c38e83a243d8f33da1d494f16315c6e
2021-05-27gdb: remove iterate_over_bp_locations functionSimon Marchi4-29/+25
Remove it, change users (well, a single one) to use all_bp_locations. This requires moving all_bp_locations to breakpoint.h to expose it. gdb/ChangeLog: * breakpoint.h (iterate_over_bp_locations): Remove. Update users to use all_bp_locations. (all_bp_locations): New. * breakpoint.c (all_bp_locations): Make non-static. (iterate_over_bp_locations): Remove. Change-Id: Iaf1f716d6c2c5b2975579b3dc113a86f5d0975be
2021-05-27gdb: remove iterate_over_breakpoints functionSimon Marchi9-77/+65
Now that we have range functions that let us use ranged for loops, we can remove iterate_over_breakpoints in favor of those, which are easier to read and write. This requires exposing the declaration of all_breakpoints and all_breakpoints_safe in breakpoint.h, as well as the supporting types. Change some users of iterate_over_breakpoints to use all_breakpoints, when they don't need to delete the breakpoint, and all_breakpoints_safe otherwise. gdb/ChangeLog: * breakpoint.h (iterate_over_breakpoints): Remove. Update callers to use all_breakpoints or all_breakpoints_safe. (breakpoint_range, all_breakpoints, breakpoint_safe_range, all_breakpoints_safe): Move here. * breakpoint.c (all_breakpoints, all_breakpoints_safe): Make non-static. (iterate_over_breakpoints): Remove. * python/py-finishbreakpoint.c (bpfinishpy_detect_out_scope_cb): Return void. * python/py-breakpoint.c (build_bp_list): Add comment, reverse return value logic. * guile/scm-breakpoint.c (bpscm_build_bp_list): Return void. Change-Id: Idde764a1f577de0423e4f2444a7d5cdb01ba5e48
2021-05-27gdb: add all_bp_locations_at_addr functionSimon Marchi2-148/+119
Add the all_bp_locations_at_addr function, which returns a range of all breakpoint locations at exactly the given address. This lets us replace: bp_location *loc, **loc2p, *locp; ALL_BP_LOCATIONS_AT_ADDR (loc2p, locp, address) { loc = *loc2p; // use loc } with for (bp_location *loc : all_bp_locations_at_addr (address)) { // use loc } The all_bp_locations_at_addr returns a bp_locations_at_addr_range object, which is really just a wrapper around two std::vector iterators representing the beginning and end of the interesting range. These iterators are found when constructing the bp_locations_at_addr_range object using std::equal_range, which seems a perfect fit for this use case. One thing I noticed about the current ALL_BP_LOCATIONS_AT_ADDR is that if you call it with a NULL start variable, that variable gets filled in and can be re-used for subsequent iterations. This avoids the cost of finding the start of the interesting range again for the subsequent iterations. This happens in build_target_command_list, for example. The same effect can be achieved by storing the range in a local variable, it can be iterated on multiple times. Note that the original comment over ALL_BP_LOCATIONS_AT_ADDR says: Iterates through locations with address ADDRESS for the currently selected program space. I don't see anything restricting the iteration to a given program space, as we iterate over all bp_locations, which as far as I know contains all breakpoint locations, regardless of the program space. So I just dropped that part of the comment. gdb/ChangeLog: * breakpoint.c (get_first_locp_gte_addr): Remove. (ALL_BP_LOCATIONS_AT_ADDR): Remove. Replace all uses with all_bp_locations_at_addr. (struct bp_locations_at_addr_range): New. (all_bp_locations_at_addr): New. (bp_locations_compare_addrs): New. Change-Id: Icc8c92302045c47a48f507b7f1872bdd31d4ba59
2021-05-27gdb: add all_bp_locations functionSimon Marchi2-58/+32
Add the all_bp_locations function to replace the ALL_BP_LOCATIONS macro. For simplicity, all_bp_locations simply returns a const reference to the bp_locations vector. But the callers just treat it as a range to iterate on, so if we ever change the breakpoint location storage, we can change the all_bp_locations function to return some other range type, and the callers won't need to be changed. gdb/ChangeLog: * breakpoint.c (ALL_BP_LOCATIONS): Remove, update users to use all_bp_locations. (all_bp_locations): New. Change-Id: Iae71a1ba135c1a5bcdb4658bf3cf9793f0e9f81c
2021-05-27gdb: make bp_locations an std::vectorSimon Marchi2-58/+40
Change the type of the global location list, bp_locations, to be an std::vector. Adjust the users to deal with that, mostly in an obvious way by using .data() and .size(). The user where it's slightly less obvious is update_global_location_list. There, we std::move the old location list out of the global vector into a local variable. The code to fill the new location list gets simpler, as it's now simply using .push_back(), no need to count the locations beforehand. In the rest of update_global_location_list, the code is adjusted to work with indices instead of `bp_location **`, to iterate on the location list. I believe it's a bit easier to understand this way. But more importantly, when we build with _GLIBCXX_DEBUG, the operator[] of the vector does bound checking, so we will know if we ever access past a vector size (which we won't if we access by raw pointer). I think that work can further be done to make that function easier to understand, notably find better names than "loc" and "loc2" for variables, but that's work for later. gdb/ChangeLog: * breakpoint.c (bp_locations): Change to std::vector, update all users. (bp_locations_count): Remove. (update_global_location_list): Change to work with indices rather than bp_location**. Change-Id: I193ce40f84d5dc930fbab8867cf946e78ff0df0b
2021-05-27gdb: add breakpoint::locations methodSimon Marchi9-101/+83
Add the breakpoint::locations method, which returns a range that can be used to iterate over a breakpoint's locations. This shortens for (bp_location *loc = b->loc; loc != nullptr; loc = loc->next) into for (bp_location *loc : b->locations ()) Change all the places that I found that could use it. gdb/ChangeLog: * breakpoint.h (bp_locations_range): New. (struct breakpoint) <locations>: New. Use where possible. Change-Id: I1ba2f7d93d57e544e1f8609124587dcf2e1da037
2021-05-27gdb: add all_tracepoints functionSimon Marchi4-48/+58
Same idea as the previous patches, but to replace the ALL_TRACEPOINTS macro. Define a new filtered_iterator that only keeps the breakpoints for which is_tracepoint returns true (just like the macro did). I would have like to make it so tracepoint_range yields some `tracepoint *` instead of some `breakpoint *`, that would help simplify the callers, who wouldn't have to do the cast themselves. But I didn't find an obvious way to do it. It can always be added later. It turns out there is already an all_tracepoints function, which returns a vector containing all the breakpoints that are tracepoint. Remove it, most users will just work seamlessly with the new function. The exception is start_tracing, which iterated multiple times on the vector. Adapt this one so it iterates multiple times on the returned range. Since the existing users of all_tracepoints are outside of breakpoint.c, this requires defining all_tracepoints and a few supporting types in breakpoint.h. So, move breakpoint_iterator from breakpoint.c to breakpoint.h. gdb/ChangeLog: * breakpoint.h (all_tracepoints): Remove. (breakpoint_iterator): Move here. (struct tracepoint_filter): New. (tracepoint_iterator): New. (tracepoint_range): New. (all_tracepoints): New. * breakpoint.c (ALL_TRACEPOINTS): Remove, replace all users with all_tracepoints. (breakpoint_iterator): Move to header. (all_tracepoints): New. * tracepoint.c (start_tracing): Adjust. Change-Id: I76b1bba4215dbec7a03846c568368aeef7f1e05a
2021-05-27gdb: add all_breakpoints_safe functionSimon Marchi2-68/+47
Same as the previous patch, but intended to replace the ALL_BREAKPOINTS_SAFE macro, which allows deleting the current breakpoint while iterating. The new range type simply wraps the range added by the previous patch with basic_safe_range. I didn't remove the ALL_BREAKPOINTS_SAFE macro, because there is one spot where it's more tricky to remove, in the check_longjmp_breakpoint_for_call_dummy function. More thought it needed for this one. gdb/ChangeLog: * breakpoint.c (breakpoint_safe_range): New. (all_breakpoints_safe): New. Use instead of ALL_BREAKPOINTS_SAFE where possible. Change-Id: Ifccab29f135e1f85700e3697ed60f0b643c7682f
2021-05-27gdb: add all_breakpoints functionSimon Marchi2-119/+78
Introduce the all_breakpoints function, which returns a range that can be used to iterate on breakpoints. Replace all uses of the ALL_BREAKPOINTS macro with this. In one instance, I could replace the breakpoint iteration with a call to get_breakpoint. gdb/ChangeLog: * breakpoint.c (ALL_BREAKPOINTS): Remove, replace all uses with all_breakpoints. (breakpoint_iterator): New. (breakpoint_range): New. (all_breakpoints): New. Change-Id: I229595bddad7c9100b179a9dd56b04b8c206e86c
2021-05-27Add optional full_window argument to TuiWindow.writeHannes Domani4-7/+30
To prevent flickering when first calling erase, then write, this new argument indicates that the passed string contains the full contents of the window. This fills every unused cell of the window with a space, so it's not necessary to call erase beforehand. gdb/ChangeLog: 2021-05-27 Hannes Domani <ssbssa@yahoo.de> * python/py-tui.c (tui_py_window::output): Add full_window argument. (gdbpy_tui_write): Parse "full_window" argument. gdb/doc/ChangeLog: 2021-05-27 Hannes Domani <ssbssa@yahoo.de> * python.texi (TUI Windows In Python): Document "full_window" argument.
2021-05-27gdb: add option to reverse order of _initialize function callsSimon Marchi4-1/+51
An earlier patch in this series fixed a dependency problem between two _initialize functions. That problem was uncovered by reversing the order of the initialize function calls. In short, symtab.c tried to add the alias "maintenance flush-symbol-cache" for the command "maintenance flush symbol-cache". Because the "maintenance flush" prefix command was not yet created (it happens in maint.c, initialized later in this reversed order), the add_alias_cmd function returned NULL. That result was passed to deprecate_cmd, which didn't expected that value, and that caused a segfault. This was fixed by changing alias creation functions to take the target command as a cmd_list_element, instead of by name. This patch adds a runtime option to reverse the order of the initialize calls at will. I chose to use an environment variable for this, over a parameter (even a "maintenance" one), because: - The init functions are called before the early init commands are executed, so we could use -iex to turn this mode on early enough. This is obvious when you remember that commands / parameters are created by initialize funcitions :). - This is not something anybody would want to tweak after startup anyway. gdb/ChangeLog: * make-init-c: Add option to reverse function calls. gdb/testsuite/ChangeLog: * gdb.base/reverse-init-functions.exp: New. Change-Id: I543e609cf526e7cb145a006a794d0e6851b63f45
2021-05-27gdb: add make-init-c scriptSimon Marchi5-27/+82
I would like to modify how the init.c file is generated (its content). But as it is, a shell script with multiple sed invocations in a Makefile target, it's not very maintainable. Replace that with a shell script that does the same, but in a more readable way. The Makefile rule uses the "-" prefix in front of the for loop, I presume to ignore any error coming from the fact that xml-builtin.c and cp-name-parser.c are not found in the srcdir (they are generated source files). I prefer not to blindly ignore errors, so filter these files out of INIT_FILES instead (we already filter out other files). There are no expected meaningful changes to the generated init.c file. Just the _initialize_all_file declaration that is moved down and "void" in parenthesis that is removed. The new regular expression is a bit tighter than the existing one, it requires the init function to be followed by exactly ` ()`. Update bpf-tdep.c accordingly. gdb/ChangeLog: * Makefile.in (INIT_FILES_FILTER_OUT): New. (INIT_FILES): Use INIT_FILES_FILTER_OUT. (stamp-init): Use make-init-c. * bpf-tdep.c (_initialize_bpf_tdep): Remove "void". * silent-rules.mk (ECHO_INIT_C): Change. * make-init-c: New file. Change-Id: I6d6b12cbccf24ab79d1219bff05df01624c684f9
2021-05-27gdb: remove add_alias_cmd overload that accepts a stringSimon Marchi26-214/+260
Same idea as previous patch, but for add_alias_cmd. Remove the overload that accepts the target command as a string (the target command name), leaving only the one that takes the cmd_list_element. gdb/ChangeLog: * command.h (add_alias_cmd): Accept target as cmd_list_element. Update callers. Change-Id: I546311f411e9e7da9302322d6ffad4e6c56df266
2021-05-27gdb: make add_info_alias accept target as a cmd_list_elementSimon Marchi9-29/+43
Same idea as previous patch, but for add_info_alias. gdb/ChangeLog: * command.h (add_info_alias): Accept target as cmd_list_element. Update callers. Change-Id: If830d423364bf42d7bea5ac4dd3a81adcfce6f7a
2021-05-27gdb: make add_com_alias accept target as a cmd_list_elementSimon Marchi22-173/+219
The alias creation functions currently accept a name to specify the target command. They pass this to add_alias_cmd, which needs to lookup the target command by name. Given that: - We don't support creating an alias for a command before that command exists. - We always use add_info_alias just after creating that target command, and therefore have access to the target command's cmd_list_element. ... change add_com_alias to accept the target command as a cmd_list_element (other functions are done in subsequent patches). This ensures we don't create the alias before the target command, because you need to get the cmd_list_element from somewhere when you call the alias creation function. And it avoids an unecessary command lookup. So it seems better to me in every aspect. gdb/ChangeLog: * command.h (add_com_alias): Accept target as cmd_list_element. Update callers. Change-Id: I24bed7da57221cc77606034de3023fedac015150
2021-05-27gdb/python: use return values of add_setshow functions in add_setshow_genericSimon Marchi2-67/+71
In add_setshow_generic, we create set/show commands using add_setshow_* functions, then look up the commands by name to set the context pointer. It would be simpler and more efficient to use the return values of the add_setshow_* functions, do that. gdb/ChangeLog: * python/py-param.c (add_setshow_generic): Use return values of add_setshow functions. Change-Id: I04d50736e1001ddb732d81e088468876df9c88ff
2021-05-27gdb: remove unnecessary lookup_cmd when deprecating commandsSimon Marchi4-42/+37
Remove a few instances where we look up a command by name, but could just use the return value of a previous "add command" function call instead. gdb/ChangeLog: * mi/mi-main.c (_initialize_mi_main): * python/py-auto-load.c (gdbpy_initialize_auto_load): * remote.c (_initialize_remote): Change-Id: I6d06f9ca636e340c88c1064ae870483ad392607d
2021-05-27gdb: make add_setshow commands return set_show_commandsSimon Marchi7-264/+221
Some add_set_show commands return a single cmd_list_element, the one for the "set" command. A subsequent patch will need to access the show command's cmd_list_element as well. Change these functions to return a new structure type that holds both pointers. I initially only modified add_setshow_boolean_cmd (the one I needed), but I think it's better to change the whole chain to keep everything in sync. gdb/ChangeLog: * command.h (set_show_commands): New. (add_setshow_enum_cmd, add_setshow_auto_boolean_cmd, add_setshow_boolean_cmd, add_setshow_filename_cmd, add_setshow_string_cmd, add_setshow_string_noescape_cmd, add_setshow_optional_filename_cmd, add_setshow_integer_cmd, add_setshow_uinteger_cmd, add_setshow_zinteger_cmd, add_setshow_zuinteger_cmd, add_setshow_zuinteger_unlimited_cmd): Return set_show_commands. Adjust callers. * cli/cli-decode.c (add_setshow_cmd_full): Return set_show_commands, remove result parameters, adjust callers. Change-Id: I17492b01b76002d09effc84830f9c6db26f1db7a
generated by cgit v1.1 at 2025-09-20 02:23:04 +0000