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author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
---|---|---|
committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
commit | a3fb396f2dc57f585a49091e12ec6c588c45e681 (patch) | |
tree | 3672573d24c85cb9157ad2c5f4a8b9ceb4945fe3 | |
parent | 9623cc5d1fb947daf6a0eadb4f7662d0791f7893 (diff) | |
download | gdb-a3fb396f2dc57f585a49091e12ec6c588c45e681.zip gdb-a3fb396f2dc57f585a49091e12ec6c588c45e681.tar.gz gdb-a3fb396f2dc57f585a49091e12ec6c588c45e681.tar.bz2 |
MIPS/opcodes: Add TX39 CP0 register names
The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names. Add a test case accordingly.
References:
[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
coprocessor (CP0) registers", pp. 9-10
opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".
gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
-rw-r--r-- | gas/ChangeLog | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/cp0-names-r3900.d | 43 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
-rw-r--r-- | opcodes/ChangeLog | 6 | ||||
-rw-r--r-- | opcodes/mips-dis.c | 14 |
5 files changed, 68 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 3b94c5d..4d7f814 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * testsuite/gas/mips/cp0-names-r3900.d: New test. + * testsuite/gas/mips/mips.exp: Run it. + +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. diff --git a/gas/testsuite/gas/mips/cp0-names-r3900.d b/gas/testsuite/gas/mips/cp0-names-r3900.d new file mode 100644 index 0000000..fe971a8 --- /dev/null +++ b/gas/testsuite/gas/mips/cp0-names-r3900.d @@ -0,0 +1,43 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=r3900 +#name: MIPS CP0 register disassembly (r3900) +#as: -32 -march=r3900 +#source: cp0-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 40800000 mtc0 \$0,\$0 +[0-9a-f]+ <[^>]*> 40800800 mtc0 \$0,\$1 +[0-9a-f]+ <[^>]*> 40801000 mtc0 \$0,\$2 +[0-9a-f]+ <[^>]*> 40801800 mtc0 \$0,c0_config +[0-9a-f]+ <[^>]*> 40802000 mtc0 \$0,\$4 +[0-9a-f]+ <[^>]*> 40802800 mtc0 \$0,\$5 +[0-9a-f]+ <[^>]*> 40803000 mtc0 \$0,\$6 +[0-9a-f]+ <[^>]*> 40803800 mtc0 \$0,c0_cache +[0-9a-f]+ <[^>]*> 40804000 mtc0 \$0,c0_badvaddr +[0-9a-f]+ <[^>]*> 40804800 mtc0 \$0,\$9 +[0-9a-f]+ <[^>]*> 40805000 mtc0 \$0,\$10 +[0-9a-f]+ <[^>]*> 40805800 mtc0 \$0,\$11 +[0-9a-f]+ <[^>]*> 40806000 mtc0 \$0,c0_sr +[0-9a-f]+ <[^>]*> 40806800 mtc0 \$0,c0_cause +[0-9a-f]+ <[^>]*> 40807000 mtc0 \$0,c0_epc +[0-9a-f]+ <[^>]*> 40807800 mtc0 \$0,c0_prid +[0-9a-f]+ <[^>]*> 40808000 mtc0 \$0,c0_debug +[0-9a-f]+ <[^>]*> 40808800 mtc0 \$0,c0_depc +[0-9a-f]+ <[^>]*> 40809000 mtc0 \$0,\$18 +[0-9a-f]+ <[^>]*> 40809800 mtc0 \$0,\$19 +[0-9a-f]+ <[^>]*> 4080a000 mtc0 \$0,\$20 +[0-9a-f]+ <[^>]*> 4080a800 mtc0 \$0,\$21 +[0-9a-f]+ <[^>]*> 4080b000 mtc0 \$0,\$22 +[0-9a-f]+ <[^>]*> 4080b800 mtc0 \$0,\$23 +[0-9a-f]+ <[^>]*> 4080c000 mtc0 \$0,\$24 +[0-9a-f]+ <[^>]*> 4080c800 mtc0 \$0,\$25 +[0-9a-f]+ <[^>]*> 4080d000 mtc0 \$0,\$26 +[0-9a-f]+ <[^>]*> 4080d800 mtc0 \$0,\$27 +[0-9a-f]+ <[^>]*> 4080e000 mtc0 \$0,\$28 +[0-9a-f]+ <[^>]*> 4080e800 mtc0 \$0,\$29 +[0-9a-f]+ <[^>]*> 4080f000 mtc0 \$0,\$30 +[0-9a-f]+ <[^>]*> 4080f800 mtc0 \$0,\$31 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index d021f05..8f3c7d9 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1315,6 +1315,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "cp0-names-numeric" run_dump_test "cp0-names-r3000" + run_dump_test "cp0-names-r3900" run_dump_test "cp0-names-r4000" \ { { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } } run_dump_test "cp0-names-r4000" \ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f81b2f7..1a1833a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * mips-dis.c (mips_cp0_names_r3900): New variable. + (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' + for "r3900". + +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index d519420..0bdf7cf 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -122,6 +122,18 @@ static const char * const mips_cp1_names_numeric[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const mips_cp0_names_r3900[32] = +{ + "$0", "$1", "$2", "c0_config", + "$4", "$5", "$6", "c0_cache", + "c0_badvaddr", "$9", "$10", "$11", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "c0_debug", "c0_depc", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", + "$28", "$29", "$30", "$31", +}; + static const char * const mips_cp0_names_r3000[32] = { "c0_index", "c0_random", "c0_entrylo", "$3", @@ -457,7 +469,7 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, - mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, |