diff options
Diffstat (limited to 'sim')
89 files changed, 142 insertions, 142 deletions
diff --git a/sim/aarch64/memory.c b/sim/aarch64/memory.c index 8552914..e6ae5f5 100644 --- a/sim/aarch64/memory.c +++ b/sim/aarch64/memory.c @@ -158,7 +158,7 @@ aarch64_get_mem_ptr (sim_cpu *cpu, uint64_t address) an out-of-memory condition by noticing a stack/heap collision. The heap starts at the end of loaded memory and carries on up - to an arbitary 2Gb limit. */ + to an arbitrary 2Gb limit. */ uint64_t aarch64_get_heap_start (sim_cpu *cpu) diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c index 5cd33fb..70cebcd 100644 --- a/sim/arm/armcopro.c +++ b/sim/arm/armcopro.c @@ -134,7 +134,7 @@ check_cp15_access (ARMul_State * state, return ARMul_CANT; break; case 7: - /* Permissable combinations: + /* Permissible combinations: Opcode_2 CRm 0 5 0 6 @@ -157,7 +157,7 @@ check_cp15_access (ARMul_State * state, break; case 8: - /* Permissable combinations: + /* Permissible combinations: Opcode_2 CRm 0 5 0 6 @@ -232,7 +232,7 @@ write_cp15_reg (ARMul_State * state, /* Writes are not allowed. */ return; - case 1: /* Auxillary Control. */ + case 1: /* Auxiliary Control. */ /* Only BITS (5, 4) and BITS (1, 0) can be written. */ value &= 0x33; break; diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index cafaabb..2958977 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -6033,7 +6033,7 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking - care to propogate the carries from the additions. */ + care to propagate the carries from the additions. */ RdLo = Add32 (lo, (mid1 << 16), &carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), &carry); diff --git a/sim/bfin/devices.h b/sim/bfin/devices.h index aebf3b2..1bc9222 100644 --- a/sim/bfin/devices.h +++ b/sim/bfin/devices.h @@ -28,7 +28,7 @@ #include "bfin-sim.h" -/* We keep the same inital structure layout with DMA enabled devices. */ +/* We keep the same initial structure layout with DMA enabled devices. */ struct dv_bfin { bu32 base; struct hw *dma_master; diff --git a/sim/bfin/dv-bfin_cec.c b/sim/bfin/dv-bfin_cec.c index 2ba56e3..c0dffeb 100644 --- a/sim/bfin/dv-bfin_cec.c +++ b/sim/bfin/dv-bfin_cec.c @@ -574,7 +574,7 @@ _cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg) /* XXX: what happens with 'raise 0' ? */ SET_RETEREG (oldpc); excp_to_sim_halt (sim_stopped, SIM_SIGTRAP); - /* XXX: Need an easy way for gdb to signal it isnt here. */ + /* XXX: Need an easy way for gdb to signal it isn't here. */ cec->ipend &= ~IVG_EMU_B; break; case IVG_RST: diff --git a/sim/common/dv-pal.c b/sim/common/dv-pal.c index dd251ab..c415cc5 100644 --- a/sim/common/dv-pal.c +++ b/sim/common/dv-pal.c @@ -96,7 +96,7 @@ non-zero 32 bit big-endian value to this register sets the countdown timer to expire in VALUE ticks (ticks is target dependant). Reading the countdown register returns the last value - writen. + written. COUNTDOWN VALUE (read): Reading this 32 bit big-endian register returns the number of ticks remaining until the countdown timer diff --git a/sim/common/hw-base.h b/sim/common/hw-base.h index 01ea1e7..2843ab7 100644 --- a/sim/common/hw-base.h +++ b/sim/common/hw-base.h @@ -23,7 +23,7 @@ #ifndef HW_BASE #define HW_BASE -/* Create a primative device */ +/* Create a primitive device */ struct hw *hw_create (struct sim_state *sd, diff --git a/sim/common/hw-device.h b/sim/common/hw-device.h index f64b2c2..bea9e94 100644 --- a/sim/common/hw-device.h +++ b/sim/common/hw-device.h @@ -170,7 +170,7 @@ typedef unsigned (hw_reset_method) /* Hardware operations: Connecting a parent to its children is a common bus. The parent - node is described as the bus owner and is responisble for + node is described as the bus owner and is responsible for co-ordinating bus operations. On the bus, a SPACE:ADDR pair is used to specify an address. A device that is both a bus owner (parent) and bus client (child) are referred to as a bridging device. diff --git a/sim/common/hw-instances.h b/sim/common/hw-instances.h index 789ccd3..2a8cb92 100644 --- a/sim/common/hw-instances.h +++ b/sim/common/hw-instances.h @@ -33,7 +33,7 @@ disks file system. The operations would be implemented using the basic block I/O model provided by the disk. - This model includes methods that faciliate the creation of device + This model includes methods that facilitate the creation of device instance and (should a given device support it) standard operations on those instances. diff --git a/sim/common/hw-tree.c b/sim/common/hw-tree.c index 5df3bd5..f3a855e 100644 --- a/sim/common/hw-tree.c +++ b/sim/common/hw-tree.c @@ -1264,7 +1264,7 @@ hw_tree_find_device (struct hw *root, /* parse the path */ split_device_specifier (root, path_to_device, &spec); if (spec.value != NULL) - return NULL; /* something wierd */ + return NULL; /* something weird */ /* now find it */ node = split_find_device (root, &spec); diff --git a/sim/common/sim-arange.c b/sim/common/sim-arange.c index a58b064..efdaae0 100644 --- a/sim/common/sim-arange.c +++ b/sim/common/sim-arange.c @@ -82,12 +82,12 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p) { if (! delete_p) { - /* Try next range if current range preceeds new one and not + /* Try next range if current range precedes new one and not adjacent or overlapping. */ if (asr->end < caller->start - 1) goto next_range; - /* Break out if new range preceeds current one and not + /* Break out if new range precedes current one and not adjacent or overlapping. */ if (asr->start > caller->end + 1) break; @@ -114,11 +114,11 @@ frob_range (ADDR_RANGE *ar, address_word start, address_word end, int delete_p) } else /* deleting a range */ { - /* Try next range if current range preceeds new one. */ + /* Try next range if current range precedes new one. */ if (asr->end < caller->start) goto next_range; - /* Break out if new range preceeds current one. */ + /* Break out if new range precedes current one. */ if (asr->start > caller->end) break; diff --git a/sim/common/sim-bits.h b/sim/common/sim-bits.h index 53d8a12..63ac452 100644 --- a/sim/common/sim-bits.h +++ b/sim/common/sim-bits.h @@ -548,7 +548,7 @@ do { \ /* some rotate functions. The generic macro's ROT, ROTL, ROTR are - intentionally omited. */ + intentionally omitted. */ INLINE_SIM_BITS(uint8_t) ROT8 (uint8_t val, int shift); diff --git a/sim/common/sim-config.h b/sim/common/sim-config.h index 9ca0149..2470378 100644 --- a/sim/common/sim-config.h +++ b/sim/common/sim-config.h @@ -141,7 +141,7 @@ extern enum bfd_endian current_target_byte_order; expect to see (VEA includes things like coherency and the time base) while OEA is what an operating system expects to see. By setting these to specific values, the build process is able to - eliminate non relevent environment code. + eliminate non relevant environment code. STATE_ENVIRONMENT(sd) specifies which of vea or oea is required for the current runtime. diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index 85a384a..a3b73b0 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -130,7 +130,7 @@ extern SIM_RC sim_core_install (SIM_DESC sd); such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal hook that allows clients to do nasty things that the interface doesn't - accomodate. */ + accommodate. */ extern void sim_core_attach (SIM_DESC sd, @@ -161,7 +161,7 @@ extern void sim_core_detach Transfer a variable sized block of raw data between the host and target. Should any problems occur, the number of bytes - successfully transfered is returned. + successfully transferred is returned. No host/target byte endian conversion is performed. No xor-endian conversion is performed. @@ -207,7 +207,7 @@ extern void sim_core_set_xor Transfer a variable sized block of raw data between the host and target. Should any problems occur, the number of bytes - successfully transfered is returned. + successfully transferred is returned. No host/target byte endian conversion is performed. If applicable (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is* @@ -245,7 +245,7 @@ extern void *sim_core_trans_addr /* Fixed sized, processor oriented, read/write. Transfer a fixed amout of memory between the host and target. The - data transfered is translated from/to host to/from target byte + data transferred is translated from/to host to/from target byte order (including xor endian). Should the transfer fail, the operation shall abort (no return). diff --git a/sim/common/sim-engine.h b/sim/common/sim-engine.h index 72f3972..af64f2f 100644 --- a/sim/common/sim-engine.h +++ b/sim/common/sim-engine.h @@ -134,7 +134,7 @@ extern void sim_engine_vabort /* Called by the generic sim_resume to run the simulation within the - above safty net. + above safety net. An example implementation of sim_engine_run can be found in the file sim-run.c */ diff --git a/sim/common/sim-inline.h b/sim/common/sim-inline.h index 5d0ea65..091cd87 100644 --- a/sim/common/sim-inline.h +++ b/sim/common/sim-inline.h @@ -38,7 +38,7 @@ speed improvement (x3-x5). In the case of RISC (sparc) while the performance gain isn't as great it is still significant. - Each module is controled by the macro <module>_INLINE which can + Each module is controlled by the macro <module>_INLINE which can have the values described below 0 (ZERO) diff --git a/sim/common/sim-io.c b/sim/common/sim-io.c index 988c50e..196efe8 100644 --- a/sim/common/sim-io.c +++ b/sim/common/sim-io.c @@ -333,7 +333,7 @@ sim_io_poll_quit (SIM_DESC sd) FIXME: Some completly new mechanism for handling the general problem of asynchronous IO is needed. - FIXME: This function does not supress the echoing (ECHO) of input. + FIXME: This function does not suppress the echoing (ECHO) of input. Consequently polled input is always displayed. FIXME: This function does not perform uncooked reads. diff --git a/sim/common/sim-resume.c b/sim/common/sim-resume.c index e2f260a..dd1a6c8 100644 --- a/sim/common/sim-resume.c +++ b/sim/common/sim-resume.c @@ -35,7 +35,7 @@ has_stepped (SIM_DESC sd, } -/* Generic resume - assumes the existance of sim_engine_run */ +/* Generic resume - assumes the existence of sim_engine_run */ void sim_resume (SIM_DESC sd, diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c index c84371f..50bd5d3 100644 --- a/sim/erc32/exec.c +++ b/sim/erc32/exec.c @@ -314,7 +314,7 @@ mul64 (uint32_t n1, uint32_t n2, uint32_t *result_hi, uint32_t *result_lo, int m hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ reg_lo = add32 (lo, (mid1 << 16), &carry); reg_hi = carry; reg_lo = add32 (reg_lo, (mid2 << 16), &carry); diff --git a/sim/erc32/float.c b/sim/erc32/float.c index 2b851ca..069436c 100644 --- a/sim/erc32/float.c +++ b/sim/erc32/float.c @@ -20,7 +20,7 @@ FPU. IEEE trap handling is done as follows: 1. In the host, all IEEE traps are masked 2. After each simulated FPU instruction, check if any exception - occured by reading the exception bits from the host FPU status + occurred by reading the exception bits from the host FPU status register (get_accex()). 3. Propagate any exceptions to the simulated FSR. 4. Clear host exception bits. diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h index cf44ddf..9044a08 100644 --- a/sim/erc32/sis.h +++ b/sim/erc32/sis.h @@ -114,7 +114,7 @@ struct pstate { uint64_t pwdtime; /* Cycles in power-down mode */ uint64_t nstore; /* Number of load instructions */ uint64_t nload; /* Number of store instructions */ - uint64_t nannul; /* Number of annuled instructions */ + uint64_t nannul; /* Number of annulled instructions */ uint64_t nbranch; /* Number of branch instructions */ uint32_t ildreg; /* Destination of last load instruction */ uint64_t ildtime; /* Last time point for load dependency */ diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h index d6c0912..e504abe 100644 --- a/sim/frv/frv-sim.h +++ b/sim/frv/frv-sim.h @@ -266,7 +266,7 @@ enum frv_ec /* FR-V Interrupt. This struct contains enough information to describe a particular interrupt - occurance. */ + occurrence. */ struct frv_interrupt { enum frv_interrupt_kind kind; diff --git a/sim/frv/profile.c b/sim/frv/profile.c index 6903a1b..1f63549 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -598,14 +598,14 @@ request_complete (SIM_CPU *cpu, CACHE_QUEUE_ELEMENT *q) } /* Run the insn and data caches through the given number of cycles, taking - note of load requests which are fullfilled as a result. */ + note of load requests which are fulfilled as a result. */ static void run_caches (SIM_CPU *cpu, int cycles) { FRV_CACHE* data_cache = CPU_DATA_CACHE (cpu); FRV_CACHE* insn_cache = CPU_INSN_CACHE (cpu); int i; - /* For each cycle, run the caches, noting which requests have been fullfilled + /* For each cycle, run the caches, noting which requests have been fulfilled and submitting new requests on their designated cycles. */ for (i = 0; i < cycles; ++i) { diff --git a/sim/frv/traps.c b/sim/frv/traps.c index 9953145..006550d 100644 --- a/sim/frv/traps.c +++ b/sim/frv/traps.c @@ -780,7 +780,7 @@ frvbf_check_swap_address (SIM_CPU *current_cpu, SI address) if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) return; - /* Adress must be aligned on a word boundary. */ + /* Address must be aligned on a word boundary. */ if (address & 0x3) frv_queue_data_access_exception_interrupt (current_cpu); } diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index cfa6eee..0698809 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -1568,7 +1568,7 @@ store2 (SIM_DESC sd, ea_type *arg, int n) return store_1 (sd, arg, n, 1); } -/* Callback for qsort. We sort first based on availablity +/* Callback for qsort. We sort first based on availability (available instructions sort lower). When availability state is the same, then we use the first 4 bit nibble as a secondary sort key. diff --git a/sim/igen/gen-engine.c b/sim/igen/gen-engine.c index cdf77ad..2533536 100644 --- a/sim/igen/gen-engine.c +++ b/sim/igen/gen-engine.c @@ -67,7 +67,7 @@ print_run_body (lf *file, const gen_entry *table) { /* Output the function to execute real code: - Unfortunatly, there are multiple cases to consider vis: + Unfortunately, there are multiple cases to consider vis: <icache> X <smp> diff --git a/sim/igen/gen-icache.c b/sim/igen/gen-icache.c index 77d170d..641c20e 100644 --- a/sim/igen/gen-icache.c +++ b/sim/igen/gen-icache.c @@ -152,7 +152,7 @@ print_icache_extraction (lf *file, switch (what_to_declare) { case undef_variables: - /* We've finished with the #define value - destory it */ + /* We've finished with the #define value - destroy it */ lf_indent_suppress (file); lf_printf (file, "#undef %s\n", entry_name); return; @@ -632,7 +632,7 @@ print_icache_struct (lf *file, const insn_table *isa, cache_entry *cache_rules) else { /* alernativly, since no cache, emit a dummy definition for - idecode_cache so that code refering to the type can still compile */ + idecode_cache so that code referring to the type can still compile */ lf_printf (file, "typedef void %sidecode_cache;\n", options.module.global.prefix.l); } diff --git a/sim/igen/gen-semantics.c b/sim/igen/gen-semantics.c index f6cb55a..fed0914 100644 --- a/sim/igen/gen-semantics.c +++ b/sim/igen/gen-semantics.c @@ -246,7 +246,7 @@ print_semantic_body (lf *file, } /* Architecture expects a REG to be zero. Instead of having to - check every read to see if it is refering to that REG just zap it + check every read to see if it is referring to that REG just zap it at the start of every instruction */ if (options.gen.zero_reg) { diff --git a/sim/igen/gen-semantics.h b/sim/igen/gen-semantics.h index 786e5ba..7844f6a 100644 --- a/sim/igen/gen-semantics.h +++ b/sim/igen/gen-semantics.h @@ -36,9 +36,9 @@ o cached - separate cracker and semantic - Two independant functions are created. Firstly the + Two independent functions are created. Firstly the function that cracks an instruction entering it into a - cache and secondly the semantic function propper that + cache and secondly the semantic function proper that uses the cache. o cached - semantic + cracking semantic diff --git a/sim/igen/gen.c b/sim/igen/gen.c index 1499147..bf57162 100644 --- a/sim/igen/gen.c +++ b/sim/igen/gen.c @@ -644,7 +644,7 @@ insns_bit_useless (const insn_list *insns, const decode_table *rule, int bit_nr) /* Given only one constant value has been found, check through all the instructions to see if at least one conditional makes it - usefull */ + useful */ if (value >= 0 && is_useless) { for (entry = insns; entry != NULL; entry = entry->next) @@ -981,7 +981,7 @@ gen_entry_expand_opcode (gen_entry *table, condition->field->last); /* this is a requirement of a conditonal field - refering to another field */ + referring to another field */ ASSERT ((condition->field->first - condition->field->last) == (first_pos - last_pos)); diff --git a/sim/igen/igen.c b/sim/igen/igen.c index 94caf6e..60314a6 100644 --- a/sim/igen/igen.c +++ b/sim/igen/igen.c @@ -481,7 +481,7 @@ print_itrace (lf *file, const insn_entry *insn, int idecode) { /* NB: Here we escape each EOLN. This is so that the the compiler treats a trace function call as a single line. Consequently any - errors in the line are refered back to the same igen assembler + errors in the line are referred back to the same igen assembler source line */ const char *phase = (idecode) ? "DECODE" : "INSN"; lf_printf (file, "\n"); diff --git a/sim/igen/igen.h b/sim/igen/igen.h index 7d3b9b4..6e68bfb 100644 --- a/sim/igen/igen.h +++ b/sim/igen/igen.h @@ -138,7 +138,7 @@ struct _igen_decode_options int combine; /* Instruction expansion? Should the semantic code for each - instruction, when the oportunity arrises, be expanded according + instruction, when the opportunity arrises, be expanded according to the variable opcode files that the instruction decode process renders constant */ int duplicate; diff --git a/sim/igen/ld-decode.c b/sim/igen/ld-decode.c index 5f67d52..368138e 100644 --- a/sim/igen/ld-decode.c +++ b/sim/igen/ld-decode.c @@ -161,7 +161,7 @@ load_decode_table (const char *file_name) else new_rule->last = options.insn_bit_size - 1; if (new_rule->first > new_rule->last) - error (new_rule->line, "First must preceed last\n"); + error (new_rule->line, "First must precede last\n"); /* force first/last, with default values based on first/last */ if (entry->nr_fields > decode_force_first_field diff --git a/sim/igen/ld-decode.h b/sim/igen/ld-decode.h index e26de29..562628a 100644 --- a/sim/igen/ld-decode.h +++ b/sim/igen/ld-decode.h @@ -89,7 +89,7 @@ If an instruction field was found, enlarge the field size so that it is forced to at least include bits starting from <force_first> - (<force_last>). To stop this occuring, use <force_first> = <last> + (<force_last>). To stop this occurring, use <force_first> = <last> + 1 and <force_last> = <first> - 1. <force_reserved> @@ -101,7 +101,7 @@ Treat any contained register (string) fields as constant when determining the instruction field. For the instruction decode (and - controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of + controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of what would otherwize be non constant bits of an instruction. <use_switch> diff --git a/sim/igen/ld-insn.c b/sim/igen/ld-insn.c index a561bad..baa8e12 100644 --- a/sim/igen/ld-insn.c +++ b/sim/igen/ld-insn.c @@ -201,7 +201,7 @@ parse_insn_word (const line_ref *line, char *string, int word_nr) { if (strlen_pos == 0) { - /* when the length/pos field is omited, an integer field + /* when the length/pos field is omitted, an integer field is always binary */ uint64_t val = 0; int i; @@ -409,7 +409,7 @@ parse_insn_words (insn_entry * insn, char *formats) insn->word[i] = word; } - /* Go over all fields that have conditionals refering to other + /* Go over all fields that have conditionals referring to other fields. Link the fields up. Verify that the two fields have the same size. Verify that the two fields are different */ { @@ -442,9 +442,9 @@ parse_insn_words (insn_entry * insn, char *formats) && strcmp (refered_field->val_string, cond->string) == 0) { - /* found field being refered to by conditonal */ + /* found field being referred to by conditonal */ cond->field = refered_field; - /* check refered to and this field are + /* check referred to and this field are the same size */ if (f->width != refered_field->width) error (insn->line, diff --git a/sim/igen/lf.h b/sim/igen/lf.h index 6a6c1e2..eac9fa4 100644 --- a/sim/igen/lf.h +++ b/sim/igen/lf.h @@ -47,7 +47,7 @@ lf_file_references; /* Open the file NAME for writing ("-" for stdout). Use REAL_NAME - when refering to the opened file. Line number information (in the + when referring to the opened file. Line number information (in the output) can be suppressed with FILE_REFERENCES == LF_OMIT_REFERENCES. TYPE is to determine the formatting of some of the print messages below. */ diff --git a/sim/lm32/dv-lm32uart.c b/sim/lm32/dv-lm32uart.c index 345f937..2d2065f 100644 --- a/sim/lm32/dv-lm32uart.c +++ b/sim/lm32/dv-lm32uart.c @@ -97,7 +97,7 @@ do_uart_tx_event (struct hw *me, void *data) hw_port_event (me, INT_PORT, 1); } - /* Indicate which interrupt has occured. */ + /* Indicate which interrupt has occurred. */ uart->iir = MICOUART_IIR_TXRDY; /* Indicate THR is empty. */ diff --git a/sim/m32r/mloop2.in b/sim/m32r/mloop2.in index 202bdd1..b363b85 100644 --- a/sim/m32r/mloop2.in +++ b/sim/m32r/mloop2.in @@ -107,7 +107,7 @@ emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, with the first insn. */ /* ??? Revisit to handle exceptions right. */ - /* FIXME: No need to handle this parallely if second is nop. */ + /* FIXME: No need to handle this parallelly if second is nop. */ id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1); /* Note that this can never be a cti. No cti's go in the S pipeline. */ diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in index 64342da..562263e 100644 --- a/sim/m32r/mloopx.in +++ b/sim/m32r/mloopx.in @@ -107,7 +107,7 @@ emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, with the first insn. */ /* ??? Revisit to handle exceptions right. */ - /* FIXME: No need to handle this parallely if second is nop. */ + /* FIXME: No need to handle this parallelly if second is nop. */ id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1); /* Note that this can never be a cti. No cti's go in the S pipeline. */ diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 7140d95..fe0f948 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -152,7 +152,7 @@ t2h_addr (host_callback *cb, struct cb_syscall *sc, /* TODO: These functions are a big hack and assume that the host runtime has type sizes and struct layouts that match the target. So the Linux emulation - probaly only really works in 32-bit runtimes. */ + probably only really works in 32-bit runtimes. */ static void translate_endian_h2t (void *addr, size_t size) diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c index dc43cc5..3214b0d 100644 --- a/sim/m68hc11/dv-m68hc11tim.c +++ b/sim/m68hc11/dv-m68hc11tim.c @@ -351,7 +351,7 @@ m68hc11tim_timer_event (struct hw *me, void *data) compare = (m68hc11_cpu->ios[i] << 8) + m68hc11_cpu->ios[i + 1]; - /* See if compare is reached; handle wrap arround. */ + /* See if compare is reached; handle wrap around. */ if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt) || (compare >= tcnt_prev && tcnt_prev > tcnt) || (compare < tcnt && tcnt_prev > tcnt)) diff --git a/sim/mips/acinclude.m4 b/sim/mips/acinclude.m4 index f32a841..ab7fa9c 100644 --- a/sim/mips/acinclude.m4 +++ b/sim/mips/acinclude.m4 @@ -224,7 +224,7 @@ __EOF__ for fc in ${sim_mips_multi_configs}; do dnl Split up the entry. ${c} contains the first three elements. - dnl Note: outer sqaure brackets are m4 quotes. + dnl Note: outer square brackets are m4 quotes. c=`echo ${fc} | sed ['s/:[^:]*$//']` bfdmachs=`echo ${fc} | sed 's/.*://'` name=`echo ${c} | sed 's/:.*//'` diff --git a/sim/mips/interp.c b/sim/mips/interp.c index b15b228..a2757ec 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -2579,7 +2579,7 @@ mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) } else if (exception != 0 && mips_cpu->exc_suspended == 0) { - sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); + sim_io_eprintf(sd, "Warning, ignoring spontaneous exception signal (%d)\n", exception); } mips_cpu->exc_suspended = 0; } diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen index 1d53d18..ab44995 100644 --- a/sim/mips/m16.igen +++ b/sim/mips/m16.igen @@ -1049,7 +1049,7 @@ { if (STATE & simDELAYSLOT) { - return DSPC; /* return saved address of preceeding jmp */ + return DSPC; /* return saved address of preceding jmp */ } else { diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 09f82aa..8203d19 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -305,9 +305,9 @@ // suggest they don't. // // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have -// these restrictions, while others, like the VR5500, don't. To accomodate +// these restrictions, while others, like the VR5500, don't. To accommodate // such differences, the MIPS IV and MIPS V version of these helper functions -// use auxillary routines to determine whether the restriction applies. +// use auxiliary routines to determine whether the restriction applies. // check_mf_cycles: // @@ -474,7 +474,7 @@ *micromips32: *micromips64: { - /* FIXME: could record the fact that a stall occured if we want */ + /* FIXME: could record the fact that a stall occurred if we want */ int64_t time = sim_events_time (SD); hi->op.timestamp = time; lo->op.timestamp = time; diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index e87a12b..cb7d7ce 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -109,7 +109,7 @@ typedef enum { /* For some MIPS targets, the HI/LO registers have certain timing restrictions in that, for instance, a read of a HI register must be - separated by at least three instructions from a preceeding read. + separated by at least three instructions from a preceding read. The struct below is used to record the last access by each of A MT, MF or other OP instruction to a HI/LO register. See mips.igen for @@ -282,7 +282,7 @@ struct mips_sim_cpu { #define simPCOC1 (1 << 18) /* COC[1] from previous */ #define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */ #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ -#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ +#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occurred */ #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ #define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */ diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index 8a3f73c..d3dc018 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -172,7 +172,7 @@ sim_open (SIM_OPEN_KIND kind, sim_hw_parse (sd, "/mn103cpu@0x20000000"); sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42"); - /* DEBUG: ACK output wired upto a glue device */ + /* DEBUG: ACK output wired up to a glue device */ sim_hw_parse (sd, "/glue@0x20002000"); sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4"); sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000"); @@ -478,7 +478,7 @@ mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) } else if(exception != 0 && State.exc_suspended == 0) { - sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); + sim_io_eprintf(sd, "Warning, ignoring spontaneous exception signal (%d)\n", exception); } State.exc_suspended = 0; } diff --git a/sim/ppc/BUGS b/sim/ppc/BUGS index 300c791..816f054 100644 --- a/sim/ppc/BUGS +++ b/sim/ppc/BUGS @@ -34,7 +34,7 @@ Better and more devices. PORTABILITY: (Notes taken from Michael Meissner): Heavy use of the ## operator - -fix using the clasic X/**/Y hack; Use of the signed keyword. In +fix using the classic X/**/Y hack; Use of the signed keyword. In particular, signed char has no analogue in classic C (though most implementations of classic C use signed chars); Use of long long which restricts the target compiler to be GCC. @@ -94,7 +94,7 @@ IGEN: Igen at present can't do the following: - o duplication is an all or nothing afair. + o duplication is an all or nothing affair. It should be configurable according to the instruction or the sub-table. diff --git a/sim/ppc/INSTALL b/sim/ppc/INSTALL index 22ead08..220ed4d 100644 --- a/sim/ppc/INSTALL +++ b/sim/ppc/INSTALL @@ -146,7 +146,7 @@ At the time of writing the following were outstanding: the description of a target machine (including the initial state of all processor registers) from a file. - Unfortunatly GDB does not yet have a standard command that + Unfortunately GDB does not yet have a standard command that facilitates the use of this feature. Until such a command is added, the patch (hack?) gdb-4.15+attach.diff.gz can be used to extend GDB's attach command so that it can be used to initialize diff --git a/sim/ppc/README b/sim/ppc/README index f5049e8..683d51f 100644 --- a/sim/ppc/README +++ b/sim/ppc/README @@ -173,7 +173,7 @@ contributed in their own unique way: If PSIM doesn't monitor a components of interest, the source code is freely available, and hence - there is no hinderance to changing things + there is no hindrance to changing things to meet a specific analysts needs. diff --git a/sim/ppc/RUN b/sim/ppc/RUN index 6c3cfef..07d6505 100644 --- a/sim/ppc/RUN +++ b/sim/ppc/RUN @@ -193,7 +193,7 @@ requirements. The output from a performance run (on a P90) for the program psim-test/profile/bench is below. In this run psim was fairly -agressively configured (see the file INSTALL for compile time +aggressively configured (see the file INSTALL for compile time configuration). CPU #1 executed 41,994 AND instructions. diff --git a/sim/ppc/altivec_registers.h b/sim/ppc/altivec_registers.h index 19d645c..3df5c63 100644 --- a/sim/ppc/altivec_registers.h +++ b/sim/ppc/altivec_registers.h @@ -46,7 +46,7 @@ struct altivec_regs { /* AltiVec endian helpers, wrong endian hosts vs targets need to be sure to get the right bytes/halfs/words when the order matters. Note that many AltiVec instructions do not depend on byte order and - work on N independant bits of data. This is only for the + work on N independent bits of data. This is only for the instructions that actually move data around. */ #if (HOST_BYTE_ORDER == BIG_ENDIAN) diff --git a/sim/ppc/corefile.h b/sim/ppc/corefile.h index 9297f3e..be28d70 100644 --- a/sim/ppc/corefile.h +++ b/sim/ppc/corefile.h @@ -85,7 +85,7 @@ INLINE_CORE\ restarting it. For callback maps it is possible to further order them by - specifiying specifying a callback level (eg callback + 1). + specifying specifying a callback level (eg callback + 1). When the core is resolving an access it searches each of the maps in order. First raw-memory and then callback maps (in assending @@ -119,7 +119,7 @@ INLINE_CORE\ The operation of mapping between an address and its destination device or memory array is currently implemented using a simple linked list. The posibility of replacing this list with a more - powerfull data structure exists. + powerful data structure exists. */ @@ -171,7 +171,7 @@ INLINE_CORE\ Transfer (zero) a variable size block of data between the host and target (possibly byte swapping it). Should any problems occure, - the number of bytes actually transfered is returned. */ + the number of bytes actually transferred is returned. */ INLINE_CORE\ (unsigned) core_map_read_buffer diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h index dfd2244..b9f7885 100644 --- a/sim/ppc/cpu.h +++ b/sim/ppc/cpu.h @@ -139,7 +139,7 @@ INLINE_CPU\ #if WITH_IDECODE_CACHE_SIZE -/* Return the cache entry that matches the given CIA. No guarentee +/* Return the cache entry that matches the given CIA. No guarantee that the cache entry actually contains the instruction for that address */ @@ -160,7 +160,7 @@ INLINE_CPU\ inner vm maps, to have the cpu its self provide memory manipulation functions. (eg cpu_instruction_fetch() cpu_data_read_4()) - Unfortunatly in addition to these functions is the need (for the + Unfortunately in addition to these functions is the need (for the debugger) to be able to read/write to memory in ways that violate the vm protection (eg store breakpoint instruction in the instruction map). */ diff --git a/sim/ppc/debug.c b/sim/ppc/debug.c index a9b48c3..74a37e9 100644 --- a/sim/ppc/debug.c +++ b/sim/ppc/debug.c @@ -39,7 +39,7 @@ typedef struct _trace_option_descriptor { static trace_option_descriptor trace_description[] = { { trace_gdb, "gdb", "calls made by gdb to the sim_calls.c file" }, - { trace_os_emul, "os-emul", "VEA mode sytem calls - like strace" }, + { trace_os_emul, "os-emul", "VEA mode system calls - like strace" }, { trace_events, "events", "event queue handling" }, /* decode/issue */ { trace_semantics, "semantics", "Instruction execution (issue)" }, diff --git a/sim/ppc/device.h b/sim/ppc/device.h index 65c85e4..609afb5 100644 --- a/sim/ppc/device.h +++ b/sim/ppc/device.h @@ -430,7 +430,7 @@ INLINE_DEVICE\ disks file system. The operations would be implemented using the basic block I/O model provided by the disk. - This model includes methods that faciliate the creation of device + This model includes methods that facilitate the creation of device instance and (should a given device support it) standard operations on those instances. diff --git a/sim/ppc/emul_bugapi.c b/sim/ppc/emul_bugapi.c index 067e406..ae8b564 100644 --- a/sim/ppc/emul_bugapi.c +++ b/sim/ppc/emul_bugapi.c @@ -59,7 +59,7 @@ #define _NETWR 0x019 /* Write to host */ #define _NETCFIG 0x01a /* Configure network parameters */ #define _NETOPN 0x01b /* Open file for reading */ -#define _NETFRD 0x01c /* Retreive specified file blocks */ +#define _NETFRD 0x01c /* Retrieve specified file blocks */ #define _NETCTRL 0x01d /* Implement special control functions */ #define _OUTCHR 0x020 /* Output character (pointer / pointer format) */ #define _OUTSTR 0x021 /* Output string (pointer / pointer format) */ @@ -118,7 +118,7 @@ static const struct bug_map bug_mapping[] = { { _NETWR, ".NETWR -- Write to host" }, { _NETCFIG, ".NETCFIG -- Configure network parameters" }, { _NETOPN, ".NETOPN -- Open file for reading" }, - { _NETFRD, ".NETFRD -- Retreive specified file blocks" }, + { _NETFRD, ".NETFRD -- Retrieve specified file blocks" }, { _NETCTRL, ".NETCTRL -- Implement special control functions" }, { _OUTCHR, ".OUTCHR -- Output character" }, { _OUTSTR, ".OUTSTR -- Output string (pointer / pointer format)" }, diff --git a/sim/ppc/gen-icache.c b/sim/ppc/gen-icache.c index d9b76ad..de483ba 100644 --- a/sim/ppc/gen-icache.c +++ b/sim/ppc/gen-icache.c @@ -102,7 +102,7 @@ print_icache_extraction(lf *file, /* Define a storage area for the cache element */ if (what_to_declare == undef_variables) { - /* We've finished with the value - destory it */ + /* We've finished with the value - destroy it */ lf_indent_suppress(file); lf_printf(file, "#undef %s\n", entry_name); return; @@ -482,7 +482,7 @@ print_icache_struct(insn_table *instructions, } else { /* alernativly, since no cache, emit a dummy definition for - idecode_cache so that code refering to the type can still compile */ + idecode_cache so that code referring to the type can still compile */ lf_printf(file, "typedef void idecode_cache;\n"); } lf_printf(file, "\n"); diff --git a/sim/ppc/gen-idecode.c b/sim/ppc/gen-idecode.c index bbb1cc9..0f500c8 100644 --- a/sim/ppc/gen-idecode.c +++ b/sim/ppc/gen-idecode.c @@ -693,7 +693,7 @@ print_run_until_stop_body(lf *file, { /* Output the function to execute real code: - Unfortunatly, there are multiple cases to consider vis: + Unfortunately, there are multiple cases to consider vis: <icache> X <smp> X <events> X <keep-running-flag> X ... diff --git a/sim/ppc/gen-semantics.h b/sim/ppc/gen-semantics.h index 8d1804b..02e3c25 100644 --- a/sim/ppc/gen-semantics.h +++ b/sim/ppc/gen-semantics.h @@ -32,9 +32,9 @@ o cached - separate cracker and semantic - Two independant functions are created. Firstly the + Two independent functions are created. Firstly the function that cracks an instruction entering it into a - cache and secondly the semantic function propper that + cache and secondly the semantic function proper that uses the cache. o cached - semantic + cracking semantic diff --git a/sim/ppc/hw_cpu.c b/sim/ppc/hw_cpu.c index df807c1..8857fed 100644 --- a/sim/ppc/hw_cpu.c +++ b/sim/ppc/hw_cpu.c @@ -118,7 +118,7 @@ hw_cpu_init_address(device *me) /* Take the interrupt and synchronize its delivery with the clock. If we've not yet scheduled an interrupt for the next clock tick, take - the oportunity to do it now */ + the opportunity to do it now */ static void hw_cpu_interrupt_event(device *me, diff --git a/sim/ppc/hw_eeprom.c b/sim/ppc/hw_eeprom.c index 2bbcd77..1f58ca6 100644 --- a/sim/ppc/hw_eeprom.c +++ b/sim/ppc/hw_eeprom.c @@ -29,7 +29,7 @@ /* DEVICE - eeprom - JEDEC? compatible electricaly erasable programable device + eeprom - JEDEC? compatible electricaly erasable programmable device DESCRIPTION diff --git a/sim/ppc/hw_ide.c b/sim/ppc/hw_ide.c index af61eec..ce911e9 100644 --- a/sim/ppc/hw_ide.c +++ b/sim/ppc/hw_ide.c @@ -37,7 +37,7 @@ This device models the primary/secondary <<ide>> controller described in the [CHRPIO] document. - The controller has separate independant interrupt outputs for each + The controller has separate independent interrupt outputs for each <<ide>> bus. @@ -91,7 +91,7 @@ | i0,0,1c,6 1 \ | i0,0,20,0 8' \ - Note: the fouth and fifth reg entries specify that the register is + Note: the fourth and fifth reg entries specify that the register is at an offset into the address specified by the base register (<<assigned-addresses>>); Apart from restrictions placed by the <<pci>> specification, no restrictions are placed on the number of diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c index 804daa9..79dd646 100644 --- a/sim/ppc/hw_init.c +++ b/sim/ppc/hw_init.c @@ -182,7 +182,7 @@ static device_callbacks const hw_file_callbacks = { eeprom requires a complex sequence of accesses). The <<real-address>> is specified as <<0x0c00>> which is the offset into the eeprom. For brevity, most of the eeprom properties have - been omited. + been omitted. | /iobus/eeprom@0xfff00000/reg 0xfff00000 0x80000 | /openprom/init/data@0xfff00c00/real-address 0x0c00 diff --git a/sim/ppc/hw_opic.c b/sim/ppc/hw_opic.c index 4247411..f518b05 100644 --- a/sim/ppc/hw_opic.c +++ b/sim/ppc/hw_opic.c @@ -782,13 +782,13 @@ handle_interrupt(device *me, else if (!src->is_level_triggered && src->is_positive_polarity && !asserted) { - DTRACE(opic, ("interrupt %d - ignore falling edge (positive edge trigered)\n", + DTRACE(opic, ("interrupt %d - ignore falling edge (positive edge triggered)\n", src->nr)); } else if (!src->is_level_triggered && !src->is_positive_polarity && asserted) { - DTRACE(opic, ("interrupt %d - ignore rising edge (negative edge trigered)\n", + DTRACE(opic, ("interrupt %d - ignore rising edge (negative edge triggered)\n", src->nr)); } else if (src->in_service != 0) { @@ -879,7 +879,7 @@ do_end_of_interrupt_register_N_write(device *me, DTRACE(opic, ("eoi %d - ignoring nonzero value\n", dest->nr)); } - /* user doing wierd things? */ + /* user doing weird things? */ if (dest->current_in_service == NULL) { DTRACE(opic, ("eoi %d - strange, no current interrupt\n", dest->nr)); return; @@ -1393,7 +1393,7 @@ timer_event(void *data) opic_timer *timer = data; device *me = timer->me; if (timer->inhibited) - device_error(timer->me, "internal-error - timer event occured when timer %d inhibited", + device_error(timer->me, "internal-error - timer event occurred when timer %d inhibited", timer->nr); handle_interrupt(timer->me, timer->opic, timer->interrupt_source, 1); timer->timeout_event = device_event_queue_schedule(me, timer->base_count, diff --git a/sim/ppc/hw_phb.c b/sim/ppc/hw_phb.c index 06eb29f..ac0223d 100644 --- a/sim/ppc/hw_phb.c +++ b/sim/ppc/hw_phb.c @@ -90,7 +90,7 @@ Since device tree entries that are specified on the command line are added before most of the device tree has been built it is often - necessary to explictly add certain device properties and thus + necessary to explicitly add certain device properties and thus ensure they are already present in the device tree. For the <<phb>> one such property is parent busses <<#address-cells>>. @@ -154,7 +154,7 @@ The Open Firmware PCI bus bindings document (rev 1.6) suggests that the register field of non-relocatable PCI address should be zero. - Unfortunatly, PCI addresses specified in the <<assigned-addresses>> + Unfortunately, PCI addresses specified in the <<assigned-addresses>> property must be both non-relocatable and have non-zero register fields. @@ -316,7 +316,7 @@ hw_phb_attach_address(device *me, if (phb_type != hw_phb_normal_decode && phb_type != hw_phb_subtractive_decode) device_error(me, "attach type (%d) specified by %s invalid", type, device_path(client)); - /* attach it to the relevent bus */ + /* attach it to the relevant bus */ DTRACE(phb, ("attach %s - %s %s:0x%lx (0x%lx bytes)\n", device_path(client), hw_phb_decode_name(phb_type), diff --git a/sim/ppc/idecode_expression.h b/sim/ppc/idecode_expression.h index 86b3394..c44083c 100644 --- a/sim/ppc/idecode_expression.h +++ b/sim/ppc/idecode_expression.h @@ -48,7 +48,7 @@ /* 64bit target expressions: - Unfortunatly 128bit arrithemetic isn't that common. Consequently + Unfortunately 128bit arrithemetic isn't that common. Consequently the 32/64 bit trick can not be used. Instead all calculations are required to retain carry/overflow information in separate variables. Even with this restriction it is still possible for the diff --git a/sim/ppc/igen.c b/sim/ppc/igen.c index 635030d..5396771 100644 --- a/sim/ppc/igen.c +++ b/sim/ppc/igen.c @@ -365,7 +365,7 @@ main(int argc, printf(" -C Include semantics in cache functions\n"); printf(" -S Include insn (instruction) in icache\n"); printf(" -R Use defines to reference cache vars\n"); - printf(" -L Supress line numbering in output files\n"); + printf(" -L Suppress line numbering in output files\n"); printf(" -B <bit-size> Set the number of bits in an instruction\n"); printf(" -H <high-bit> Set the nr of the high (msb bit)\n"); printf(" -N <nr-cpus> Specify the max number of cpus the simulation will support\n"); diff --git a/sim/ppc/igen.h b/sim/ppc/igen.h index 052806a..813632c 100644 --- a/sim/ppc/igen.h +++ b/sim/ppc/igen.h @@ -41,7 +41,7 @@ typedef enum { generate_calls = 0x100, - /* In addition, when refering to fields access them directly instead + /* In addition, when referring to fields access them directly instead of via variables */ generate_calls_with_direct_access @@ -116,7 +116,7 @@ extern int icache_size; /* Instruction expansion? - Should the semantic code for each instruction, when the oportunity + Should the semantic code for each instruction, when the opportunity arrises, be expanded according to the variable opcode files that the instruction decode process renders constant */ diff --git a/sim/ppc/ld-decode.h b/sim/ppc/ld-decode.h index 4332dcc..046b97d 100644 --- a/sim/ppc/ld-decode.h +++ b/sim/ppc/ld-decode.h @@ -52,7 +52,7 @@ If an instruction field was found, enlarge the field size so that it is forced to at least include bits starting from <force_first> - (<force_last>). To stop this occuring, use <force_first> = <last> + (<force_last>). To stop this occurring, use <force_first> = <last> + 1 and <force_last> = <first> - 1. <force_slash> @@ -64,7 +64,7 @@ Treat any contained register (string) fields as constant when determining the instruction field. For the instruction decode (and - controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of + controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of what would otherwize be non constant bits of an instruction. <use_switch> diff --git a/sim/ppc/powerpc.igen b/sim/ppc/powerpc.igen index 60840fe..79b0d9b 100644 --- a/sim/ppc/powerpc.igen +++ b/sim/ppc/powerpc.igen @@ -3964,7 +3964,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - double product; /*HACK! - incorrectly loosing precision ... */ + double product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4011,7 +4011,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - float product; /*HACK! - incorrectly loosing precision ... */ + float product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4058,7 +4058,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - double product; /*HACK! - incorrectly loosing precision ... */ + double product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4105,7 +4105,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - float product; /*HACK! - incorrectly loosing precision ... */ + float product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4152,7 +4152,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - double product; /*HACK! - incorrectly loosing precision ... */ + double product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4199,7 +4199,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - float product; /*HACK! - incorrectly loosing precision ... */ + float product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4246,7 +4246,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 2, 4, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - double product; /*HACK! - incorrectly loosing precision ... */ + double product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, @@ -4293,7 +4293,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603e:PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 *604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0 FPSCR_BEGIN; - float product; /*HACK! - incorrectly loosing precision ... */ + float product; /*HACK! - incorrectly losing precision ... */ /* compute the multiply */ if (is_invalid_operation(processor, cia, *frA, *frC, diff --git a/sim/ppc/psim.c b/sim/ppc/psim.c index 3b86b86..b2fff6a 100644 --- a/sim/ppc/psim.c +++ b/sim/ppc/psim.c @@ -445,7 +445,7 @@ psim_create(const char *file_name, os_emulation = os_emul_create(file_name, root); if (os_emulation == NULL) - error("psim: either file %s was not reconized or unreconized or unknown os-emulation type\n", file_name); + error("psim: either file %s was not recognized or unreconized or unknown os-emulation type\n", file_name); /* fill in the missing real number of CPU's */ nr_cpus = tree_find_integer_property(root, "/openprom/options/smp"); @@ -991,7 +991,7 @@ psim_write_register(psim *system, processor = system->processors[which_cpu]; - /* If the data is comming in raw (target order), need to cook it + /* If the data is coming in raw (target order), need to cook it into host order before putting it into PSIM's internal structures */ if (mode == raw_transfer) { switch (description.size) { diff --git a/sim/ppc/psim.texinfo b/sim/ppc/psim.texinfo index b551387..6e30f53 100644 --- a/sim/ppc/psim.texinfo +++ b/sim/ppc/psim.texinfo @@ -147,7 +147,7 @@ This is Edition @value{edition} of the Texinfo documentation, @end ifinfo @c Here is a spare copy of the chapter menu entry descriptions, -@c in case they are accidently deleted +@c in case they are accidentally deleted @ignore Your rights. Texinfo in brief. @@ -927,7 +927,7 @@ contributed in their own unique way: If PSIM doesn't monitor a components of interest, the source code is freely available, and hence - there is no hinderance to changing things + there is no hindrance to changing things to meet a specific analysts needs. diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h index de68cf2..d1cd981 100644 --- a/sim/ppc/std-config.h +++ b/sim/ppc/std-config.h @@ -106,7 +106,7 @@ extern enum bfd_endian current_target_byte_order; expect to see (VEA includes things like coherency and the time base) while OEA is what an operating system expects to see. By setting these to specific values, the build process is able to - eliminate non relevent environment code + eliminate non relevant environment code CURRENT_ENVIRONMENT specifies which of vea or oea is required for the current runtime. */ @@ -131,7 +131,7 @@ extern int current_environment; /* Events. Devices modeling real H/W need to be able to efficiently schedule things to do at known times in the future. The event - queue implements this. Unfortunatly this adds the need to check + queue implements this. Unfortunately this adds the need to check for any events once each full instruction cycle. */ #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) @@ -284,7 +284,7 @@ extern int current_stdio; speed improvement (x3-x5). In the case of RISC (sparc) while the performance gain isn't as great it is still significant. - Each module is controled by the macro <module>_INLINE which can + Each module is controlled by the macro <module>_INLINE which can have the values described below 0 Do not inline any thing for the given module @@ -384,7 +384,7 @@ extern int current_stdio; Prefix to any declaration of a global object (function or variable) that should not be inlined and should have only one definition. The #ifndef wrapper goes around the definition - propper to ensure that only one copy is generated. + proper to ensure that only one copy is generated. nb: this will not work when a module is being inlined for every use. diff --git a/sim/ppc/tree.c b/sim/ppc/tree.c index c2fe917..5ccb8ad 100644 --- a/sim/ppc/tree.c +++ b/sim/ppc/tree.c @@ -1217,7 +1217,7 @@ tree_find_device(device *root, /* parse the path */ split_device_specifier(root, path_to_device, &spec); if (spec.value != NULL) - return NULL; /* something wierd */ + return NULL; /* something weird */ /* now find it */ node = split_find_device(root, &spec); diff --git a/sim/ppc/vm.c b/sim/ppc/vm.c index b5ef758..3f82766 100644 --- a/sim/ppc/vm.c +++ b/sim/ppc/vm.c @@ -445,7 +445,7 @@ om_write_word(om_map *map, } -/* Bring things into existance */ +/* Bring things into existence */ INLINE_VM\ (vm *) diff --git a/sim/ppc/vm.h b/sim/ppc/vm.h index 63dc23c..2b6137a 100644 --- a/sim/ppc/vm.h +++ b/sim/ppc/vm.h @@ -60,7 +60,7 @@ INLINE_VM\ /* generic block transfers. Dependant on the presence of the - PROCESSOR arg, either returns the number of bytes transfered or (if + PROCESSOR arg, either returns the number of bytes transferred or (if PROCESSOR is non NULL) aborts the simulation */ INLINE_VM\ diff --git a/sim/sh/interp.c b/sim/sh/interp.c index bbf26bb..379b44f 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -146,7 +146,7 @@ static int maskl = 0; /* Alternate bank of registers r0-r7 */ -/* Note: code controling SR handles flips between BANK0 and BANK1 */ +/* Note: code controlling SR handles flips between BANK0 and BANK1 */ #define Rn_BANK(n) (saved_state.asregs.bank[(n)]) #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0) @@ -726,7 +726,7 @@ static int nsamples; #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */ #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */ -#define SCI_RDRF 0x40 /* Recieve data register full */ +#define SCI_RDRF 0x40 /* Receive data register full */ #define SCI_TDRE 0x80 /* Transmit data register empty */ static int @@ -1238,7 +1238,7 @@ macl (int *regs, unsigned char *memory, int n, int m) mach |= 0xffff8000; /* Sign extend higher 16 bits */ } else - mach = mach & 0x00007fff; /* Postive Result */ + mach = mach & 0x00007fff; /* Positive Result */ } MACL = macl; diff --git a/sim/testsuite/bfin/se_illegalcombination.S b/sim/testsuite/bfin/se_illegalcombination.S index 85633d1..c3a0cc7 100644 --- a/sim/testsuite/bfin/se_illegalcombination.S +++ b/sim/testsuite/bfin/se_illegalcombination.S @@ -2,7 +2,7 @@ // Description: Multi-issue Illegal Combinations # mach: bfin # sim: --environment operating -# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-* +# xfail: "missing a few checks; hardware doesn't seem to match PRM?" *-* #include "test.h" .include "testutils.inc" diff --git a/sim/testsuite/bfin/se_undefinedinstruction1.S b/sim/testsuite/bfin/se_undefinedinstruction1.S index 5337a74..fa1ab72 100644 --- a/sim/testsuite/bfin/se_undefinedinstruction1.S +++ b/sim/testsuite/bfin/se_undefinedinstruction1.S @@ -200,7 +200,7 @@ BEGIN: .dw 0x21 ; .dw 0x22 ; .dw 0x26 ; - .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ? + .dw 0x27 ; // XXX: hardware doesn't trigger illegal exception ? .dw 0x28 ; .dw 0x29 ; .dw 0x2A ; diff --git a/sim/testsuite/bfin/se_undefinedinstruction2.S b/sim/testsuite/bfin/se_undefinedinstruction2.S index d21e375..9d68ccb 100644 --- a/sim/testsuite/bfin/se_undefinedinstruction2.S +++ b/sim/testsuite/bfin/se_undefinedinstruction2.S @@ -175,12 +175,12 @@ BEGIN: .dw 0x10E ; .dw 0x124 ; .ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? + // XXX: hardware doesn't trigger illegal exception ? .dw 0x125 ; .endif .dw 0x164 ; .ifndef BFIN_HW - // XXX: hardware doesnt trigger illegal exception ? + // XXX: hardware doesn't trigger illegal exception ? .dw 0x165 ; .endif .dw 0x128 ; diff --git a/sim/testsuite/d10v/t-macros.i b/sim/testsuite/d10v/t-macros.i index d6e155c..d5e85a4 100644 --- a/sim/testsuite/d10v/t-macros.i +++ b/sim/testsuite/d10v/t-macros.i @@ -174,7 +174,7 @@ _start: .data 1: ldi r1, 2f@word jmp r1 -;;; Successfull trap jumps back to here +;;; Successful trap jumps back to here .text ;;; Verify the PSW 2: mvfc r2, cr0 diff --git a/sim/testsuite/frv/testutils.inc b/sim/testsuite/frv/testutils.inc index 8261b4fa..3ff78f0 100644 --- a/sim/testsuite/frv/testutils.inc +++ b/sim/testsuite/frv/testutils.inc @@ -347,7 +347,7 @@ test_gr\@: test_fr_iimmed \val,fr31 .endm -; Test CPR agains an immediate value +; Test CPR against an immediate value .macro test_cpr_limmed valh vall reg addi sp,-4,gr31 stc \reg,@(gr31,gr0) diff --git a/sim/testsuite/h8300/ldc.s b/sim/testsuite/h8300/ldc.s index 3712a6c..74cba02 100644 --- a/sim/testsuite/h8300/ldc.s +++ b/sim/testsuite/h8300/ldc.s @@ -341,7 +341,7 @@ ldc_reg_sbr: mov #0xaaaaaaaa, er0 ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value + stc sbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. @@ -358,7 +358,7 @@ ldc_reg_vbr: mov #0xaaaaaaaa, er0 ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value + stc vbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. diff --git a/sim/testsuite/h8300/stc.s b/sim/testsuite/h8300/stc.s index 232bd5a..62b8ac0 100644 --- a/sim/testsuite/h8300/stc.s +++ b/sim/testsuite/h8300/stc.s @@ -304,7 +304,7 @@ stc_sbr_reg: mov #0xaaaaaaaa, er0 ldc er0, sbr ; set sbr to 0xaaaaaaaa - stc sbr, er1 ; retreive and check sbr value + stc sbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. @@ -321,7 +321,7 @@ stc_vbr_reg: mov #0xaaaaaaaa, er0 ldc er0, vbr ; set sbr to 0xaaaaaaaa - stc vbr, er1 ; retreive and check sbr value + stc vbr, er1 ; retrieve and check sbr value test_h_gr32 0xaaaaaaaa er1 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure. diff --git a/sim/testsuite/h8300/testutils.inc b/sim/testsuite/h8300/testutils.inc index 9c2c27a..63d27d4 100644 --- a/sim/testsuite/h8300/testutils.inc +++ b/sim/testsuite/h8300/testutils.inc @@ -326,7 +326,7 @@ tccr\@: .byte 0 mov.b @tccr\@, r0l .endm -; Test that all (accessable) condition codes are clear +; Test that all (accessible) condition codes are clear .macro test_cc_clear test_carry_clear test_ovf_clear diff --git a/sim/v850/simops.c b/sim/v850/simops.c index 97948f7..e2799af 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -355,7 +355,7 @@ Multiply64 (int sign, unsigned long op0) hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry); diff --git a/sim/v850/v850-sim.h b/sim/v850/v850-sim.h index 6bd5fcf..1719cf8 100644 --- a/sim/v850/v850-sim.h +++ b/sim/v850/v850-sim.h @@ -28,7 +28,7 @@ typedef struct _v850_regs { reg_t mpu0_sregs[28]; /* mpu0 system registers */ reg_t mpu1_sregs[28]; /* mpu1 system registers */ reg_t fpu_sregs[28]; /* fpu system registers */ - reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */ + reg_t selID_sregs[7][32]; /* system registers, selID 1 through selID 7 */ reg64_t vregs[32]; /* vector registers. */ } v850_regs; diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 6b9a8bb..ef0f559 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -1149,7 +1149,7 @@ rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry); @@ -1214,7 +1214,7 @@ rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry); |