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-rw-r--r--sim/testsuite/sim/aarch64/ChangeLog6
-rw-r--r--sim/testsuite/sim/aarch64/ldn_single.s100
-rw-r--r--sim/testsuite/sim/aarch64/ldnr.s176
-rw-r--r--sim/testsuite/sim/aarch64/stn_single.s122
4 files changed, 404 insertions, 0 deletions
diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog
index 6a39354..86940e2 100644
--- a/sim/testsuite/sim/aarch64/ChangeLog
+++ b/sim/testsuite/sim/aarch64/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-14 Jim Wilson <jim.wilson@linaro.org>
+
+ * ldn_single.s: New.
+ * ldnr.s: New.
+ * stn_single.s: New.
+
2017-01-23 Jim Wilson <jim.wilson@linaro.org>
* cmtst.s: New.
diff --git a/sim/testsuite/sim/aarch64/ldn_single.s b/sim/testsuite/sim/aarch64/ldn_single.s
new file mode 100644
index 0000000..3102e9e
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/ldn_single.s
@@ -0,0 +1,100 @@
+# mach: aarch64
+
+# Check the load single 1-element structure to one lane instructions:
+# ld1, ld2, ld3, ld4.
+# Check the addressing modes: no offset, post-index immediate offset,
+# post-index register offset.
+
+.include "testutils.inc"
+
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+ .word 0x14131211
+ .word 0x18171615
+ .word 0x1c1b1a19
+ .word 0x201f1e1d
+
+ start
+ adrp x0, input
+ add x0, x0, :lo12:input
+
+ mov x2, x0
+ mov x3, #1
+ mov x4, #4
+ ld1 {v0.b}[0], [x2], 1
+ ld1 {v0.b}[1], [x2], x3
+ ld1 {v0.h}[1], [x2], 2
+ ld1 {v0.s}[1], [x2], x4
+ ld1 {v0.d}[1], [x2]
+ addv b1, v0.16b
+ mov x5, v1.d[0]
+ cmp x5, #136
+ bne .Lfailure
+
+ mov x2, x0
+ mov x3, #16
+ mov x4, #4
+ ld2 {v0.d, v1.d}[0], [x2], x3
+ ld2 {v0.s, v1.s}[2], [x2], 8
+ ld2 {v0.h, v1.h}[6], [x2], x4
+ ld2 {v0.b, v1.b}[14], [x2], 2
+ ld2 {v0.b, v1.b}[15], [x2]
+ addv b2, v0.16b
+ addv b3, v1.16b
+ mov x5, v2.d[0]
+ mov x6, v3.d[0]
+ cmp x5, #221
+ bne .Lfailure
+ cmp x6, #307
+ bne .Lfailure
+
+ mov x2, x0
+ ld3 {v0.s, v1.s, v2.s}[0], [x2], 12
+ ld3 {v0.s, v1.s, v2.s}[1], [x2]
+ mov x2, x0
+ mov x3, #12
+ ld3 {v0.s, v1.s, v2.s}[2], [x2], x3
+ ld3 {v0.s, v1.s, v2.s}[3], [x2]
+ addv b3, v0.16b
+ addv b4, v1.16b
+ addv b5, v2.16b
+ mov x4, v3.d[0]
+ mov x5, v4.d[0]
+ mov x6, v5.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ cmp x5, #200
+ bne .Lfailure
+ cmp x6, #264
+ bne .Lfailure
+
+ mov x2, x0
+ ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
+ ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2]
+ mov x2, x0
+ mov x3, #16
+ ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3
+ ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
+ addv b4, v0.16b
+ addv b5, v1.16b
+ addv b6, v2.16b
+ addv b7, v3.16b
+ mov x4, v4.d[0]
+ mov x5, v5.d[0]
+ mov x6, v6.d[0]
+ mov x7, v7.d[0]
+ cmp x4, #168
+ bne .Lfailure
+ cmp x5, #232
+ bne .Lfailure
+ cmp x6, #296
+ bne .Lfailure
+ cmp x7, #360
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail
diff --git a/sim/testsuite/sim/aarch64/ldnr.s b/sim/testsuite/sim/aarch64/ldnr.s
new file mode 100644
index 0000000..a4bfffa
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/ldnr.s
@@ -0,0 +1,176 @@
+# mach: aarch64
+
+# Check the load single 1-element structure and replicate to all lanes insns:
+# ld1r, ld2r, ld3r, ld4r.
+# Check the addressing modes: no offset, post-index immediate offset,
+# post-index register offset.
+
+.include "testutils.inc"
+
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+input2:
+ .word 0x00000001
+ .word 0x00000002
+ .word 0x00000003
+ .word 0x00000004
+ .word 0x00000005
+ .word 0x00000006
+ .word 0x00000007
+ .word 0x00000008
+ .word 0x00000009
+ .word 0x0000000a
+ .word 0x0000000b
+ .word 0x0000000c
+
+ start
+ adrp x0, input
+ add x0, x0, :lo12:input
+ adrp x1, input2
+ add x1, x1, :lo12:input2
+
+ mov x2, x0
+ mov x3, #1
+ ld1r {v0.8b}, [x2], 1
+ ld1r {v1.16b}, [x2], x3
+ ld1r {v2.4h}, [x2], 2
+ ld1r {v3.8h}, [x2]
+ addv b0, v0.8b
+ addv b1, v1.16b
+ addv b2, v2.8b
+ addv b3, v3.16b
+ mov x2, v0.d[0]
+ mov x3, v1.d[0]
+ mov x4, v2.d[0]
+ mov x5, v3.d[0]
+ cmp x2, #8
+ bne .Lfailure
+ cmp x3, #32
+ bne .Lfailure
+ cmp x4, #28
+ bne .Lfailure
+ cmp x5, #88
+ bne .Lfailure
+
+ mov x2, x1
+ mov x3, #8
+ ld2r {v0.2s, v1.2s}, [x2], 8
+ ld2r {v2.4s, v3.4s}, [x2], x3
+ ld2r {v4.1d, v5.1d}, [x2], 16
+ ld2r {v6.2d, v7.2d}, [x2]
+ addp v0.2s, v0.2s, v1.2s
+ addv s2, v2.4s
+ addv s3, v3.4s
+ addp v4.2s, v4.2s, v5.2s
+ addv s6, v6.4s
+ addv s7, v7.4s
+ mov w2, v0.s[0]
+ mov w3, v0.s[1]
+ mov x4, v2.d[0]
+ mov x5, v3.d[0]
+ mov w6, v4.s[0]
+ mov w7, v4.s[1]
+ mov x8, v6.d[0]
+ mov x9, v7.d[0]
+ cmp w2, #2
+ bne .Lfailure
+ cmp w3, #4
+ bne .Lfailure
+ cmp x4, #12
+ bne .Lfailure
+ cmp x5, #16
+ bne .Lfailure
+ cmp w6, #11
+ bne .Lfailure
+ cmp w7, #15
+ bne .Lfailure
+ cmp x8, #38
+ bne .Lfailure
+ cmp x9, #46
+ bne .Lfailure
+
+ mov x2, x0
+ mov x3, #3
+ ld3r {v0.8b, v1.8b, v2.8b}, [x2], 3
+ ld3r {v3.8b, v4.8b, v5.8b}, [x2], x3
+ ld3r {v6.8b, v7.8b, v8.8b}, [x2]
+ addv b0, v0.8b
+ addv b1, v1.8b
+ addv b2, v2.8b
+ addv b3, v3.8b
+ addv b4, v4.8b
+ addv b5, v5.8b
+ addv b6, v6.8b
+ addv b7, v7.8b
+ addv b8, v8.8b
+ addv b9, v9.8b
+ mov x2, v0.d[0]
+ mov x3, v1.d[0]
+ mov x4, v2.d[0]
+ mov x5, v3.d[0]
+ mov x6, v4.d[0]
+ mov x7, v5.d[0]
+ mov x8, v6.d[0]
+ mov x9, v7.d[0]
+ mov x10, v8.d[0]
+ cmp x2, #8
+ bne .Lfailure
+ cmp x3, #16
+ bne .Lfailure
+ cmp x4, #24
+ bne .Lfailure
+ cmp x5, #32
+ bne .Lfailure
+ cmp x6, #40
+ bne .Lfailure
+ cmp x7, #48
+ bne .Lfailure
+ cmp x8, #56
+ bne .Lfailure
+ cmp x9, #64
+ bne .Lfailure
+ cmp x10, #72
+ bne .Lfailure
+
+ mov x2, x1
+ ld4r {v0.4s, v1.4s, v2.4s, v3.4s}, [x2], 16
+ ld4r {v4.4s, v5.4s, v6.4s, v7.4s}, [x2]
+ addv s0, v0.4s
+ addv s1, v1.4s
+ addv s2, v2.4s
+ addv s3, v3.4s
+ addv s4, v4.4s
+ addv s5, v5.4s
+ addv s6, v6.4s
+ addv s7, v7.4s
+ mov x2, v0.d[0]
+ mov x3, v1.d[0]
+ mov x4, v2.d[0]
+ mov x5, v3.d[0]
+ mov x6, v4.d[0]
+ mov x7, v5.d[0]
+ mov x8, v6.d[0]
+ mov x9, v7.d[0]
+ cmp x2, #4
+ bne .Lfailure
+ cmp x3, #8
+ bne .Lfailure
+ cmp x4, #12
+ bne .Lfailure
+ cmp x5, #16
+ bne .Lfailure
+ cmp x6, #20
+ bne .Lfailure
+ cmp x7, #24
+ bne .Lfailure
+ cmp x8, #28
+ bne .Lfailure
+ cmp x9, #32
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail
diff --git a/sim/testsuite/sim/aarch64/stn_single.s b/sim/testsuite/sim/aarch64/stn_single.s
new file mode 100644
index 0000000..5527c84
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/stn_single.s
@@ -0,0 +1,122 @@
+# mach: aarch64
+
+# Check the store single 1-element structure to one lane instructions:
+# st1, st2, st3, st4.
+# Check the addressing modes: no offset, post-index immediate offset,
+# post-index register offset.
+
+.include "testutils.inc"
+
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+ .word 0x14131211
+ .word 0x18171615
+ .word 0x1c1b1a19
+ .word 0x201f1e1d
+output:
+ .zero 64
+
+ start
+ adrp x0, input
+ add x0, x0, :lo12:input
+ adrp x1, output
+ add x1, x1, :lo12:output
+
+ mov x2, x0
+ ldr q0, [x2], 8
+ ldr q1, [x2]
+ mov x2, x0
+ ldr q2, [x2], 8
+ ldr q3, [x2]
+
+ mov x2, x1
+ mov x3, #1
+ mov x4, #4
+ st1 {v0.b}[0], [x2], 1
+ st1 {v0.b}[1], [x2], x3
+ st1 {v0.h}[1], [x2], 2
+ st1 {v0.s}[1], [x2], x4
+ st1 {v0.d}[1], [x2]
+ ldr q4, [x1]
+ addv b4, v4.16b
+ mov x5, v4.d[0]
+ cmp x5, #136
+ bne .Lfailure
+
+ mov x2, x1
+ mov x3, #16
+ mov x4, #4
+ st2 {v0.d, v1.d}[0], [x2], x3
+ st2 {v0.s, v1.s}[2], [x2], 8
+ st2 {v0.h, v1.h}[6], [x2], x4
+ st2 {v0.b, v1.b}[14], [x2], 2
+ st2 {v0.b, v1.b}[15], [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ mov x5, v4.d[0]
+ mov x6, v5.d[0]
+ cmp x5, #136
+ bne .Lfailure
+ cmp x6, #264
+ bne .Lfailure
+
+ mov x2, x1
+ mov x3, #12
+ st3 {v0.s, v1.s, v2.s}[0], [x2], 12
+ st3 {v0.s, v1.s, v2.s}[1], [x2], x3
+ st3 {v0.s, v1.s, v2.s}[2], [x2], 12
+ st3 {v0.s, v1.s, v2.s}[3], [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ mov x4, v4.d[0]
+ mov x5, v5.d[0]
+ mov x6, v6.d[0]
+ cmp x4, #88
+ bne .Lfailure
+ cmp x5, #200
+ bne .Lfailure
+ cmp x6, #248
+ bne .Lfailure
+
+ mov x2, x1
+ mov x3, #16
+ st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
+ st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3
+ st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16
+ st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2], 16
+ ldr q7, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ addv b7, v7.16b
+ mov x4, v4.d[0]
+ mov x5, v5.d[0]
+ mov x6, v6.d[0]
+ mov x7, v7.d[0]
+ cmp x4, #104
+ bne .Lfailure
+ cmp x5, #168
+ bne .Lfailure
+ cmp x6, #232
+ bne .Lfailure
+ cmp x7, #296
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail
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