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-rw-r--r--sim/testsuite/bfin/se_illegalcombination.S2
-rw-r--r--sim/testsuite/bfin/se_undefinedinstruction1.S2
-rw-r--r--sim/testsuite/bfin/se_undefinedinstruction2.S4
-rw-r--r--sim/testsuite/d10v/t-macros.i2
-rw-r--r--sim/testsuite/frv/testutils.inc2
-rw-r--r--sim/testsuite/h8300/ldc.s4
-rw-r--r--sim/testsuite/h8300/stc.s4
-rw-r--r--sim/testsuite/h8300/testutils.inc2
-rw-r--r--sim/testsuite/mips/hilo-hazard-3.s2
-rw-r--r--sim/testsuite/mips/hilo-hazard-4.s2
-rw-r--r--sim/testsuite/pru/mul.s8
11 files changed, 17 insertions, 17 deletions
diff --git a/sim/testsuite/bfin/se_illegalcombination.S b/sim/testsuite/bfin/se_illegalcombination.S
index 85633d1..c3a0cc7 100644
--- a/sim/testsuite/bfin/se_illegalcombination.S
+++ b/sim/testsuite/bfin/se_illegalcombination.S
@@ -2,7 +2,7 @@
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
-# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
+# xfail: "missing a few checks; hardware doesn't seem to match PRM?" *-*
#include "test.h"
.include "testutils.inc"
diff --git a/sim/testsuite/bfin/se_undefinedinstruction1.S b/sim/testsuite/bfin/se_undefinedinstruction1.S
index 5337a74..fa1ab72 100644
--- a/sim/testsuite/bfin/se_undefinedinstruction1.S
+++ b/sim/testsuite/bfin/se_undefinedinstruction1.S
@@ -200,7 +200,7 @@ BEGIN:
.dw 0x21 ;
.dw 0x22 ;
.dw 0x26 ;
- .dw 0x27 ; // XXX: hardware doesnt trigger illegal exception ?
+ .dw 0x27 ; // XXX: hardware doesn't trigger illegal exception ?
.dw 0x28 ;
.dw 0x29 ;
.dw 0x2A ;
diff --git a/sim/testsuite/bfin/se_undefinedinstruction2.S b/sim/testsuite/bfin/se_undefinedinstruction2.S
index d21e375..9d68ccb 100644
--- a/sim/testsuite/bfin/se_undefinedinstruction2.S
+++ b/sim/testsuite/bfin/se_undefinedinstruction2.S
@@ -175,12 +175,12 @@ BEGIN:
.dw 0x10E ;
.dw 0x124 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x125 ;
.endif
.dw 0x164 ;
.ifndef BFIN_HW
- // XXX: hardware doesnt trigger illegal exception ?
+ // XXX: hardware doesn't trigger illegal exception ?
.dw 0x165 ;
.endif
.dw 0x128 ;
diff --git a/sim/testsuite/d10v/t-macros.i b/sim/testsuite/d10v/t-macros.i
index d6e155c..d5e85a4 100644
--- a/sim/testsuite/d10v/t-macros.i
+++ b/sim/testsuite/d10v/t-macros.i
@@ -174,7 +174,7 @@ _start:
.data
1: ldi r1, 2f@word
jmp r1
-;;; Successfull trap jumps back to here
+;;; Successful trap jumps back to here
.text
;;; Verify the PSW
2: mvfc r2, cr0
diff --git a/sim/testsuite/frv/testutils.inc b/sim/testsuite/frv/testutils.inc
index 8261b4fa..3ff78f0 100644
--- a/sim/testsuite/frv/testutils.inc
+++ b/sim/testsuite/frv/testutils.inc
@@ -347,7 +347,7 @@ test_gr\@:
test_fr_iimmed \val,fr31
.endm
-; Test CPR agains an immediate value
+; Test CPR against an immediate value
.macro test_cpr_limmed valh vall reg
addi sp,-4,gr31
stc \reg,@(gr31,gr0)
diff --git a/sim/testsuite/h8300/ldc.s b/sim/testsuite/h8300/ldc.s
index 3712a6c..74cba02 100644
--- a/sim/testsuite/h8300/ldc.s
+++ b/sim/testsuite/h8300/ldc.s
@@ -341,7 +341,7 @@ ldc_reg_sbr:
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -358,7 +358,7 @@ ldc_reg_vbr:
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/h8300/stc.s b/sim/testsuite/h8300/stc.s
index 232bd5a..62b8ac0 100644
--- a/sim/testsuite/h8300/stc.s
+++ b/sim/testsuite/h8300/stc.s
@@ -304,7 +304,7 @@ stc_sbr_reg:
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
+ stc sbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
@@ -321,7 +321,7 @@ stc_vbr_reg:
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
+ stc vbr, er1 ; retrieve and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
diff --git a/sim/testsuite/h8300/testutils.inc b/sim/testsuite/h8300/testutils.inc
index 9c2c27a..63d27d4 100644
--- a/sim/testsuite/h8300/testutils.inc
+++ b/sim/testsuite/h8300/testutils.inc
@@ -326,7 +326,7 @@ tccr\@: .byte 0
mov.b @tccr\@, r0l
.endm
-; Test that all (accessable) condition codes are clear
+; Test that all (accessible) condition codes are clear
.macro test_cc_clear
test_carry_clear
test_ovf_clear
diff --git a/sim/testsuite/mips/hilo-hazard-3.s b/sim/testsuite/mips/hilo-hazard-3.s
index 9d50da2..4c0aebf 100644
--- a/sim/testsuite/mips/hilo-hazard-3.s
+++ b/sim/testsuite/mips/hilo-hazard-3.s
@@ -1,4 +1,4 @@
-# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between.
#
# mach: -mips32r6 -mips64r6 all
# as: -mabi=eabi
diff --git a/sim/testsuite/mips/hilo-hazard-4.s b/sim/testsuite/mips/hilo-hazard-4.s
index 03c000c..d44a974 100644
--- a/sim/testsuite/mips/hilo-hazard-4.s
+++ b/sim/testsuite/mips/hilo-hazard-4.s
@@ -1,4 +1,4 @@
-# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops in between.
#
# mach: all
# as: -mabi=eabi -mmicromips
diff --git a/sim/testsuite/pru/mul.s b/sim/testsuite/pru/mul.s
index d62b3ea..754a129 100644
--- a/sim/testsuite/pru/mul.s
+++ b/sim/testsuite/pru/mul.s
@@ -28,16 +28,16 @@
ldi r29, 4567
nop
xin 0, r26, 4
- qbne32 2f, r26, 1001 * 4567
+ qbne32 2f, r26, (1001 * 4567)
# MUL: Test the pipeline emulation
ldi r28, 1002
ldi r29, 1003
ldi r29, 4004
xin 0, r26, 4
- qbne32 2f, r26, 1002 * 1003
+ qbne32 2f, r26, (1002 * 1003)
xin 0, r26, 4
- qbne32 2f, r26, 1002 * 4004
+ qbne32 2f, r26, (1002 * 4004)
# MUL: Test 64-bit result
ldi32 r28, 0x12345678
@@ -62,7 +62,7 @@
xout 0, r25, 1
xin 0, r26, 4
- qbne32 2f, r26, (1001 * 2002) + (3003 * 4004)
+ qbne32 2f, r26, ((1001 * 2002) + (3003 * 4004))
# MAC: Test 64-bit result
ldi r25, 3
generated by cgit v1.1 at 2025-02-07 18:32:55 +0000