diff options
Diffstat (limited to 'sim/sh')
| -rw-r--r-- | sim/sh/ChangeLog | 1242 | ||||
| -rw-r--r-- | sim/sh/Makefile.in | 44 | ||||
| -rw-r--r-- | sim/sh/acconfig.h | 15 | ||||
| -rw-r--r-- | sim/sh/config.in | 158 | ||||
| -rwxr-xr-x | sim/sh/configure | 5973 | ||||
| -rw-r--r-- | sim/sh/configure.ac | 14 | ||||
| -rw-r--r-- | sim/sh/gencode.c | 3450 | ||||
| -rw-r--r-- | sim/sh/interp.c | 2777 | ||||
| -rw-r--r-- | sim/sh/syscall.h | 36 | ||||
| -rw-r--r-- | sim/sh/tconfig.in | 17 |
10 files changed, 0 insertions, 13726 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog deleted file mode 100644 index 6b18c0b..0000000 --- a/sim/sh/ChangeLog +++ /dev/null @@ -1,1242 +0,0 @@ -2006-06-13 Richard Earnshaw <rearnsha@arm.com> - - * configure: Regenerated. - -2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> - - * configure: Regenerated. - -2006-05-31 Daniel Jacobowitz <dan@codesourcery.com> - - * configure: Regenerated. - -2005-11-10 Andrew Stubbs <andrew.stubbs@st.com> - - * interp.c (sim_memory_size): Use same amount of memory on Windows as - elsewhere. - -2005-09-19 J"orn Rennecke <joern.rennecke@st.com> - - * interp.c (<sys/mman.h>): Include. - (mcalloc): New function / macro. - (mfree): New macro. - (sim_size): Use mcalloc and mfree. - -2005-08-02 J"orn Rennecke <joern.rennecke@st.com> - - * interp.c (strswaplen): Add one for '\0' delimiter. - -2005-06-16 Daniel Jacobowitz <dan@codesourcery.com> - - * gencode.c (tab): Avoid lvalue casts. Suggested by - Ralf Corsepius <ralf.corsepius@rtems.org>. - -2005-04-12 Jonathan Larmour <jifl@eCosCentric.com> - - * gencode.c (tab): Avoid inserting code before variables all declared. - -2005-03-23 Mark Kettenis <kettenis@gnu.org> - - * configure: Regenerate. - -2005-01-14 Andrew Cagney <cagney@gnu.org> - - * configure.ac: Sinclude aclocal.m4 before common.m4. Add - explicit call to AC_CONFIG_HEADER. - * configure: Regenerate. - -2005-01-12 Andrew Cagney <cagney@gnu.org> - - * configure.ac: Update to use ../common/common.m4. - * configure: Re-generate. - -2005-01-11 Andrew Cagney <cagney@localhost.localdomain> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -2005-01-07 Andrew Cagney <cagney@gnu.org> - - * configure.ac: Rename configure.in, require autoconf 2.59. - * configure: Re-generate. - -2004-12-08 Hans-Peter Nilsson <hp@axis.com> - - * configure: Regenerate for ../common/aclocal.m4 update. - -2004-09-08 DJ Delorie <dj@redhat.com> - - Commited by Corinna Vinschen <vinschen@redhat.com> - * gencode.c (movua.l): Compensate for endianness. - -2004-09-08 Corinna Vinschen <vinschen@redhat.com> - - * interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro. - (in_delay_slot): New flag variable. - (Delay_Slot): Set in_delay_slot. - (sim_resume): Reset in_delay_slot after leaving code switch. - * gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all - instructions not allowed in delay slots. - -2004-09-08 Michael Snyder <msnyder@redhat.com> - - Commited by Corinna Vinschen <vinschen@redhat.com> - Introduce SH2a support. - * interp.c: Change type of jump table to short. Add various macros. - (sim_load): Save the bfd machine code. - (sim_create_inferior): Ditto. - (union saved_state_type): Add tbr, ibnr and ibcr registers. - Move bfd_mach to end of struct. Add regstack pointer. - (init_dsp): Don't swap contents of sh_dsp_table any more. Instead - use it directly in its own switch statement. Allocate space for 512 - register banks. - (do_long_move_insn): New function. - (do_blog_insn): Ditto. - (trap): Use trap #13 and trap #14 to set ibnr and ibcr. - * gencode.c: Move movx/movy insns into separate switch statement. - (op tab): Add sh2a insns. Reject instructions that are disabled - on that chip. - (gensim_caselist): Generate default case here instead of in caller. - (gensim): Generate two separate switch statements. Call - gensim_caselist once for each (for movsxy_tab and for tab). - Add tokens for r15 and multiple regs. - (conflict_warn, warn_conflicts): Add for debugging. - -2004-08-18 J"orn Rennecke <joern.rennecke@superh.com> - - * gencode.c (tab): For shad snd shld, fix result for - (op1 < 0 && shift_amount == 0). - -2004-02-02 Michael Snyder <msnyder@redhat.com> - - * gencode.c (movua.l): Set thislock to 0, not n. - -2004-02-12 Michael Snyder <msnyder@redhat.com> - - * gencode.c (table): Change from char to short. - (dumptable): Change generated table from char to short. - * interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short. - (init_dsp): Compute size of sh_dsp_table. - (sim_resume): Change jump_table from char to short. - -2004-01-27 Michael Snyder <msnyder@redhat.com> - - * gencode.c: (op tab): Some refs and defs fixes. - "fsrra" -> "fsrra <FREG_N>". - "sleep": replace array ref with array addr. - "trapa": ditto. - Comment and whitespace clean-ups. - -2004-01-07 Michael Snyder <msnyder@redhat.com> - - * gencode.c: Whitespace cleanup. - * interp.c: Ditto. - - * gencode.c: Replace 'Hitachi' with 'Renesas'. - (op tab): Add new instructions for sh4a, DBR, SBR. - (expand_opcode): Add handling for new movxy combinations. - (gensym_caselist): Ditto. - (expand_ppi_movxy): Remove movx/movy expansions, - now handled in expand_opcode. - (gensym): Add some helpful macros. - (expand_ppi_code): Flatten loop for simplicity, tweak for 12-bit - instead of 8-bit table (some insns are ambiguous to 8 bits). - (ppi_gensim, main): Generate 12-bit instead of 8-bit ppi table. - - * interp.c: Replace 'Hitachi' with 'Renesas'. - (union saved_state_type): Add dbr, sgr, ldst. - (get_loop_bounds_ext): New function. - (init_dsp): Add bfd_mach_sh4al_dsp. - (sim_resume): Handle extended loop bounds. - -2003-12-18 Michael Snyder <msnyder@redhat.com> - - * gencode.c (expand_opcode): Simplify and reorganize. - Eliminate "shift" parameter. Eliminate "4 bits at a time" - assumption. Flatten switch statement to a single level. - Add "eeee" token for even-numbered registers. - (bton): Delete. - (fsca): Use "eeee" token. - (ppi_moves): Rename to "expand_ppi_movxy". Do the ddt - [movx/movy] expansion here, as well as the ppi expansion. - (gensim_caselist): Accept 'eeee' along with 'nnnn'. - -2003-11-03 J"orn Rennecke <joern.rennecke@superh.com> - - * interp.c (fsca_s, fsrra_s): New functions. - * gencode.c (tab): Add entries for fsca and fsrra. - (expand_opcode): Allow variable length n / m fields. - -2003-10-15 J"orn Rennecke <joern.rennecke@superh.com> - - * syscall.h (SYS_truncate, SYS_ftruncate): Define. - * interp.c (trap): Add support for SYS_ftruncate and SYS_truncate. - -2003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com> - * sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and - correction for MAC.W handler - * sim/sh/interp.c ( macl ): New Function. Implementation of - MAC.L handler. - -2003-08-07 Michael Snyder <msnyder@redhat.com> - - * gencode.c (expand_ppi_code): Comment spelling fix. - -2003-07-25 Michael Snyder <msnyder@redhat.com> - - * gencode.c (pshl): Change < to <= (shift by 16 is allowed). - Cast argument of >> to unsigned to prevent sign extension. - (psha): Change < to <= (shift by 32 is allowed). - -2003-07-24 Michael Snyder <msnyder@redhat.com> - - * gencode.c: Fix typo in comment. - -2003-07-23 Michael Snyder <msnyder@redhat.com> - - * gencode.c: A few more fix-ups of refs and defs. - (frchg): Raise SIGILL if in double-precision mode. - (ldtlb): We don't simulate cache, so this is a no-op. - (movsxy_tab): Correct a few bit pattern errors. - -2003-07-09 Michael Snyder <msnyder@redhat.com> - - * gencode.c (prnd): Clear LSW of result to zeros. - * gencode.c (pmuls): Expression is mis-parenthesized. - * gencode.c (ppi_gensim): For a conditional ppi insn, if the - condition is false, we want to return (not break). A break - will take us to the end of the function where registers will - be updated, whereas the desired outcome is for nothing to change. - -2003-07-03 Michael Snyder <msnyder@redhat.com> - - * gencode.c (movs): Fix a couple of text transpositions. - -2003-06-27 Michael Snyder <msnyder@redhat.com> - - * gencode.c (op tab): Some fix-ups of refs and defs. - (ocbi, ocbp): Cache not simulated, but may cause memory fault. - (gensym_caselist): Add default case to switch statement. - (expand_ppi_code): Add default case to switch statement. - * gencode.c (op tab): Implement movca.l. - * gencode.c (op movsxy_tab): Fix an error in the bit pattern. - * gencode.c (gensim_caselist): The movy instructions use - registers R6 and R7 (not R4 and R5 like the movx insns). - -2003-06-27 Michael Snyder <msnyder@redhat.com> - - * gencode.c (op movsxy_tab): Fix up some copy/paste errors - in name: s/REG_x/REG_y/. - - * gencode.c (op tab): Move misplaced semicolon. - -2003-02-27 Andrew Cagney <cagney@redhat.com> - - * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd - to bfd. - -Fri Oct 11 16:22:28 2002 J"orn Rennecke <joern.rennecke@superh.com> - - * interp.c (trap): Return int. Take extra parameter for address - of the trap instruction. Changed all callers. - Add case 33 for profiling. - * gencode.c (trapa): Handle trap 33 using the trap function. - Add read of vector for generic traps. - -Wed Jul 17 19:36:38 2002 J"orn Rennecke <joern.rennecke@superh.com> - - * Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h. - * interp.c: Include "gdb/sim-sh.h". - (sim_store_register, sim_fetch_register): Use constants defined there. - -Tue Jun 18 16:53:11 2002 J"orn Rennecke <joern.rennecke@superh.com> - - * interp.c (sim_resume): Fix setting of bus error for - instruction fetch. - -2002-06-16 Andrew Cagney <ac131313@redhat.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -2002-06-08 Andrew Cagney <cagney@redhat.com> - - * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". - -2001-01-30 Ben Elliston <bje@redhat.com> - - * interp.c (sim_create_inferior): Record program arguments for - later inspection by the trap handler. - (count_argc): New function. - (prog_argv): Declare static. - (sim_write): Declare. - (trap): Implement argc, argnlen and argn system calls. Do not - abort on unknown system calls--simply return -1. - * syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define. - -2001-01-24 Alexandre Oliva <aoliva@redhat.com> - - * interp.c (trap): Implement time. - -2000-10-24 Ben Elliston <bje@redhat.com> - - * gencode.c (tab): Delimit strings with commas where applicable. - -Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon May 15 22:04:51 2000 J"orn Rennecke <amylaar@cygnus.co.uk> - -sh-dsp support, simulator speedup by using host byte order: - - * Makefile.in (interp.o): Depends on ppi.c . - (ppi.c): New rule. - * gencode.c (printonmatch, think, genopc): Deleted. - (MAX_NR_STUFF): Now 42. - (tab): Add SH-DSP CPU instructions. - Amalgamate ldc / stc / lds / sts instructions with similar - bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>. - Fix semantics of lds.l @<REG_N>+,MACH (no sign extend). - (movsxy_tab): New array. - For movs, change MMMM field to GGGG, and mmmm field to MMMM. - Added entries for movx, movy and parallel processing insns. - (ppi_tab): New array. - (qfunc): Stabilize sort. - (expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy. - Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'. - (dumptable): Now takes three arguments. Changed all callers. - Emit just one contigous jump table. - (filltable): Now takes an argument. Changed all callers. - Make index static. - (ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions. - (gensim_caselist): New function, broken out of gensim. - Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'. - Handle ref '9'. - (gensim): Handle 'N' in code field and '8' in refs field. - Call gensim_caselist - twice. - (ppi_index): New static variable. - (main): Unsupport default action. - Add dsp support for -x / -s option. Add -p option. - * interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare. - (saved_state_type): Rearrange to allow amalgamated ldc / stc / - lds / sts to work efficiently. - (target_dsp): New static variable. - (GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change. - (FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise. - (SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise. - (RS, RE, MOD, MOD_ME, DSP_R): Likewise. - (set_fpscr1): Likewise. Use target_dsp to check for dsp. - (MOD_MSi, SIG_BUS_FETCH): Deleted. - (CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros. - (SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise. - (SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead - of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME. - (set_sr): Reflect saved_state_type change. Fix SR_RB handling. - Use SET_MOD. - (MA, L, TL, TB): Now controlled by ACE_FAST. - (SEXT32): Just cast to int. - (SIGN32): Fixed to only shift by 31. - (CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0. - (ppi_insn): Declare. - (ppi.c): Include. - (init_dsp): Set target_dsp. When it changes, switch end of - sh_jump_table with sh_dsp_table. - (sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead. - Don't Declare PR if it's #defined. - Fix single-stepping (Was broken in Mar 6 16:59:10 patch). - (sim_store_register, sim_read_register): Translate accesses to - reflect saved_state_type change. - - * interp.c (set_sr): Set sr. - (SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros. - (set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp. - (DSP_R): Fix definition. - (sim_resume): Remove outdated SET_SR use. - - * interp.c (saved_state): New members for struct member asregs: - rs, re, insn_end, xram_start, yram_start. - (struct loop_bounds): New struct. - (SKIP_INSN): New macro. - (get_loop_bounds): New function. - (endianw): Renamed to global_endianw. - (maskw): negated bits. - (PC): Now insn_ptr. - (SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros. - (RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise. - (M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise. - (SIG_BUS_FETCH): Likewise - (raise_exception, riat_fast): New functions. - (raise_buserror, sim_stop): Use raise_exception. - (PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start. - (BUSERROR, WRITE_BUSERROR, READ_BUSERROR): - Reverse sense of mask argument. - (FP_OP, set_dr): Use RAISE_EXCEPTION. - (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast): - Declare. Remove redundant masking. - (wwat_fast, rwat_fast): Add argument endianw. Changed callers. - (MA): Updated for change pc -> PC. - (Delay_Slot): Use RIAT. - (empty): Deleted. - (trap): Remove argument little_endian. Add argument endianw. - Changed all callers. Use raise_exception. - (macw): Add argument endainw. Changed all callers. - (init_dsp): New function, extended after broken out of init_pointers. - (sim_resume): Replace pc with insn_ptr. Replace little_endian with - endianw. Replace nia with nip. Reverse sense of maskb / maskw / - maskl. Implement logic for zero-overhead loops. Don't try to - interpret garbage when getting a SIGBUS at insn fetch. - (sim_open): Call init_dsp. - * gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H / - RAISE_EXCEPTION where appropriate. - Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr. - - * interp.c (sim_store_register, sim_fetch_register): - Do proper endianness switch. - - * interp.c (saved_state_type): New members for struct member asregs: - xymem_select, xmem, ymem, xmem_offset, ymem_offset. - (special_address): Delete. - (BUSERROR): Now a two-argument predicate. - (PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros. - (wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete. - (process_wlat_addr, process_wwat_addr): New functions. - (process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise. - (process_rbat_addr): Likewise. - (wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR. - (rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete. - (rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR. - (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions. - (do_rdat, trap): Delete SLOW code. - (SEXT32, SIGN32): New macros. - (swap, swap16): Now integer in - integer out. Changed all callers. - (strswaplen, strnswap): Delete SLOW versions. - (init_pointers): Initialize dsp memory selection (preliminary). - (sim_store_register, sim_fetch_register): Use swap instead of - big / little endian read / write functions. - - * interp.c (maskl): Deleted. - (endianw, endianb): New variables. - (special_address): Now inline. - (bp_holder): Put raising of buserror there, rename to: - (raise_buserror). - (BUSERROR): Now yields a value. Changed all users. - (wbat_big): Delete. - (wlat_fast, wwat_fast, wbat_fast): New functions. - (rlat_fast, rwat_fast, rbat_fast): Likewise. - (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions. - (do_rdat, do_wdat): Likewise. Take maskl argument instead of - little_endian one. Changed caller macros. - (swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly. - (strswaplen, strnswap): New functions. - (trap): Use them to fix up endian mismatches; - disable SYS_execve and SYS_execv; fix double address translation for - SYS_pipe and SYS_stat. - (sym_write, sym_read): Add endianness translation. - (sym_store_register, sym_fetch_register): Add maskl local variable. - (sim_open): Set endianw and endianb. - -Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Aug 25 07:55:23 1999 Brendan Kehoe <brendan@cygnus.com> - - * gencode.c (fcnvds <DR_N>,FPUL): Rewrite to use a local anonymous - union type, instead of casting to an int* then a float*. - (fcnvsd FPUL,<DR_N>): Likewise. - (flds <FREG_N>,FPUL): Likewise. - (fsts FPUL,<FREG_N>): Likewise. - -1999-05-08 Felix Lee <flee@cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -1999-04-02 Keith Seitz <keiths@cygnus.com> - - * interp.c (POLL_QUIT_INTERVAL): Define. Used to tweak the - frequency at which the poll_quit callback is called. - (sim_resume): Use POLL_QUIT_INTERVAL instead of a - hard-coded value. - -Thu Sep 10 02:16:39 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * interp.c (saved_state.asregs): Add new member pad_dummy. - (sim_store_register, sim_fetch_regsiter): Add 1 to rn for use - as index into saved_state.asints. - -Mon Jun 29 19:35:24 1998 Jason Molenda (crash@bugshack.cygnus.com) - - * interp.c (sim_open): set endianness based on the ABFD if a -E - option is not present and we have an ABFD. - -Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Sun Apr 26 15:19:48 1998 Tom Tromey <tromey@cygnus.com> - - * acconfig.h: New file. - * configure.in: Reverted change of Apr 24; use sinclude again. - -Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Fri Apr 24 11:18:35 1998 Tom Tromey <tromey@cygnus.com> - - * configure.in: Don't call sinclude. - -Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Feb 17 12:49:44 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_fetch_register, sim_store_register): Pass in - length parameter. Return -1. - -Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_load): Pass lma_p and sim_write args to - sim_load_file. - -Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Sep 9 20:52:21 1997 Felix Lee <flee@cygnus.com> - - * interp.c (sim_resume): poll_quit() at least once per call; - otherwise gdb can loop sim_resume() uninterruptably. - -Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Tue Sep 2 13:15:27 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * gencode.c (tab): Order instructions according to SH3 document. - -Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Tue Aug 26 10:41:55 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_kill): Delete. - (sim_create_inferior): Add ABFD argument. - (sim_load): Move setting of PC from here. - (sim_create_inferior): To here. - -Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Mon Aug 25 16:17:51 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_open): Add ABFD argument. - -Mon Jun 23 15:49:14 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (get_dr): Avoid SIGFPE by moving integers instead of - FP's around. - (set_dr): Ditto. - -Mon Jun 23 15:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (XD, SET_XD): Delete. - (XF, SET_XF, XD_TO_XF): Define, move around registers in either - FP bank. - - * gencode.c (fmov): Update. - -Sun Jun 22 19:33:33 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (set_fpscr1): From J"orn Rennecke - <amylaar@cygnus.co.uk>, Fix typo. Ditto for comment. - -Tue Aug 12 00:19:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * interp.c (special_address): New function. - (BUSERROR): Call it. Added parameters bits_written and data. - Changed all callers. - * gencode.c (tab): Fixed ocbwb and pref. - -Fri Jun 20 22:03:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * interp.c (do_wdat, do_wdat): Fix bug in register number calculation. - -Thu Jun 19 00:28:08 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_create_inferior): Clear registers each time an - inferior is started. - -Mon Jun 16 14:01:55 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (*FP, FP_OP, FP_CMP, FP_UNARY): Provide a hook for - when a host doesn't support IEEE FP. - (*DP): Provide alternative definition that supports 64bit floating - point. - (target_little_endian): Combine little_endian and little_endian_p. - (saved_state_type): Make fpscr and sr simple integers. - (SET_FPSCR, GET_FPSCR): Use macros to update fpscr register. - (set_fpscr1): New function. Handle swapping when PR / FR bits - changed. Call via *_FPSCR macro. - (SET_SR*, GET_SR*): Use macro's to access the SR bits - avoids - endian problems. - - * gencode.c (tab): Update. - -Sun Jun 15 15:22:52 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * gencode.c (main): Perform basic checks on tab entries. - - * Makefile.in (gencode): Always compile with -g. - -Sat Jun 14 13:45:09 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * gencode.c (gensim): Move ref checking code to before `stuff'. - For branches with delay slots refs were not being checked. - - * interp.c (sim_resume): Use nia to specify the next instruction - address instead of overloading pc. - (C): Delete definiton - refer to cycles directly. - (SEXT12): New macro - sign extend a 12 bit quantity. - (Delay_Slot): Rename from SL. - - * gencode.c (tab): Update/simplify. - - * gencode.c (gensim): Better formatting of output code. - (gensim): Replace 10 with constant MAX_NR_STUFF- define as 15. - (tab): Sort alphabetically. Break `stuff' into multiple lines. - -Fri Jun 13 22:10:13 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * gencode.c (braf, bsrf): Fix branch destination calculation to - be in accordance with the documentation. - -Fri Jun 13 15:33:53 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * interp.c (init_pointers): Fix little endian test. - -Thu Jun 5 12:56:08 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * interp.c (init_pointers): SH4 hardware is always WORDS_BIT_ENDIAN. - * gencode (fmov from/to memory): take endian_mismatch into account - for 32 bit moves too. - -Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * gencode.c (swap.b): Fix treatment of high word. - -Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * sh/gencode.c, - * interp.c: experimental SH4 support. - DFmode moves are probaly broken for target little endian. - -Tue May 20 10:23:28 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_open): Add callback argument. - (sim_set_callbacks): Delete SIM_DESC argument. - -Wed Apr 30 11:38:08 1997 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (SIM_EXTRA_CLEAN): Define. - (clean targets): Delete. - (sh-clean): New target. - -Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Apr 23 17:55:22 1997 Doug Evans <dje@canuck.cygnus.com> - - * tconfig.in: New file. - * interp.c (sim_open): Handle missing arg to -E. - -Tue Apr 22 08:55:35 1997 Stu Grossman (grossman@critters.cygnus.com) - - * Makefile.in: Add clean targets. - -Fri Apr 18 18:57:04 1997 Stu Grossman (grossman@critters.cygnus.com) - - * interp.c: Include float.h and define SIGTRAP if _WIN32. - WIN32 -> _WIN32. - * (trap): Do do SYS_chown for _WIN32. - -Fri Apr 18 13:33:09 1997 Doug Evans <dje@canuck.cygnus.com> - - * interp.c (sim_resume): Fix argument to poll_quit. - -Fri Apr 18 14:14:49 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * interp.c (sim_stop): New function. - (sim_resume): Use poll_quit for polling. - -Thu Apr 17 03:32:04 1997 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (SIM_OBJS): Add sim-load.o. - * interp.c (target_byte_order): Delete. - (sim_kind, myname, little_endian_p): New static locals. - (init_pointers): Use little_endian_p instead of target_byte_order. - (sim_resume): Likewise. - (sim_open): Set sim_kind, myname. Set little_endian_p from -E arg. - (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to - load file into simulator. Set start address from bfd. - (sim_create_inferior): Return SIM_RC. Delete arg start_address. - -Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - * config.in: Ditto. - -Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> - - * interp.c (sim_open): New arg `kind'. - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Wed Mar 19 09:34:36 1997 Fred Fish <fnf@cygnus.com> - - * interp.c (sim_do_command): Check for NULL command or empty - string and handle it the same as a "help" command. Use callback - to print error message for unrecognized commands. Replace - hardcoded tab in literal string with a \t. Other minor code - cleanup. - -Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> - - * configure: Re-generate. - -Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> - - * configure: Regenerate to track ../common/aclocal.m4 changes. - -Thu Mar 13 13:00:00 1997 Doug Evans <dje@canuck.cygnus.com> - - * interp.c (sim_open): New SIM_DESC result. Argument is now - in argv form. - (other sim_*): New SIM_DESC argument. - -Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (@COMMON_MAKEFILE_FRAG): Use - COMMON_{PRE,POST}_CONFIG_FRAG instead. - * configure.in: sinclude ../common/aclocal.m4. - * configure: Regenerated. - -Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) - - * configure configure.in Makefile.in: Update to new configure - scheme which is more compatible with WinGDB builds. - * configure.in: Improve comment on how to run autoconf. - * configure: Re-run autoconf to get new ../common/aclocal.m4. - * Makefile.in: Use autoconf substitution to install common - makefile fragment. - -Wed Nov 20 02:04:32 1996 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in: Delete stuff moved to ../common/Make-common.in. - (SIM_OBJS,SIM_EXTRA_LIBS): Define. - * configure.in: Simplify using macros in ../common/aclocal.m4. - Call AC_CHECK_HEADERS(unistd.h). - * configure: Regenerated. - * config.in: New file. - * interp.c: #include "config.h". #include <unistd.h> if present. - (trap): Fetch errno value with callback->get_errno. - -Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> - - * interp.c: Don't include windows polling code if inside simluator. - -Fri Sep 20 14:57:50 1996 Stan Shebs <shebs@andros.cygnus.com> - - * interp.c: Minor formatting improvements. - (saved_state_type): Add bank registers. - (bp_holder): New function, use to break on when debugging BUSERROR. - (BUSERROR): Call it if bus error occurs. - -Wed Jun 26 12:29:22 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, - INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. - (docdir): Removed. - * configure.in (AC_PREREQ): autoconf 2.5 or higher. - (AC_PROG_INSTALL): Added. - * configure: Rebuilt. - -Thu May 16 15:44:29 1996 Ian Lance Taylor <ian@cygnus.com> - - * interp.c (saved_state_type): Add memstalls field. - (MA) Define macro. - (sim_resume): New local variable memstalls. Add it back in to - saved_state at the end of the function. - (sim_info): Report memstalls. - * gencode.c (tab): Add MA() to the execution string of all - instructions which access memory. - -Wed Feb 21 12:16:41 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Regenerate with autoconf 2.7. - -Tue Dec 5 16:38:55 1995 Stu Grossman (grossman@cygnus.com) - - * gencode.c (mac.l): Don't abort GDB if executing mac.l - instruction (which is unimplemented). Generate a SIGTRAP (in the - simulated target) instead. - -Mon Dec 4 12:22:24 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * gencode.c (tab): Added several sh3 opcodes. - (think): Added printonmatch for A_SSR and A_SPC. - * interp.c (SSR, SPC): Added definitions. - (saved_state_type): Added ssr and spc registers. - -Wed Nov 29 12:39:27 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * gencode.c (tab): In shad/shld definitions, negate R[m] before - the and operation instead of after. For shad delete cast. For shld - use UR instead of R and delete cast. - -Fri Nov 17 12:48:55 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * gencode.c (tab): Add explicit NaN support for ftrc instruction. - -Wed Nov 15 11:25:27 1995 Stu Grossman (grossman@cygnus.com) - - * interp.c: Make target_byte_order be extern to prevent SGI cc from - issuing warnings about the use of common symbols. - -Tue Nov 14 15:19:43 1995 Stu Grossman (grossman@cygnus.com) - - * gencode.c: jsr, bsr and bsrf actually save pc+4 in pr, and rts - actually uses pr+0. - -Sat Oct 21 13:01:18 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh/interp.c (sim_stop_reason): Catch SIGQUIT and indicate - program exited. - (sim_get_quit_code): Delete. - - * gencode.c (gensim): Indicate SIGILL instead of calling abort for - default case. - -Mon Oct 16 18:24:03 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * interp.c (saved_state_type): Move FP registers to immediately - after SR. - -Tue Oct 10 11:12:15 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (BISON): Remove macro. - -Fri Oct 6 12:08:18 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * interp.c (trap, case SYS_utime): Cast second arg of utime to - void * to avoid compiler error. - - * interp.c (callback): Remove last change. It is initialized by - a sim_set_callbacks call. - -Thu Oct 5 14:13:29 1995 steve chamberlain <sac@slash.cygnus.com> - - * interp.c (callback): Initialize to default callback. - -Thu Sep 28 15:26:59 1995 steve chamberlain <sac@slash.cygnus.com> - - * run.c: Moved to ../common. - * interp.c (trap): Use gdb's callback interface. - * Makefile.in: Updated. - -Wed Sep 20 13:35:13 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (maintainer-clean): New synonym for realclean. - -Wed Sep 20 09:51:50 1995 steve chamberlain <sac@slash.cygnus.com> - - * run.c (sim_callback_write_stdout): New. - * interp.c (trap): Call sim_callback_write_stdout when needed. - -Mon Sep 18 18:42:27 1995 steve chamberlain <sac@slash.cygnus.com> - - * interp.c (trap): Remove useless code. - -Fri Sep 15 19:30:05 1995 steve chamberlain <sac@slash.cygnus.com> - - * syscall.h: Copy from newlib. - -Thu Sep 14 19:32:59 1995 Stu Grossman (grossman@cygnus.com) - - * gencode.c: Back up PC by 2 for breakpoints. - * interp.c: Move fp regs beyond pc/pr/etc to avoid confusing GDB, - which expect pc to immediatly follow regs[]. - -Fri Sep 8 14:18:13 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Define CC_FOR_BUILD. Don't call AC_PROG_INSTALL. - * configure: Rebuild. - * Makefile.in (INSTALL): Revert to using install.sh. - (INSTALL_PROGRAM, INSTALL_DATA): Set to $(INSTALL). - (INSTALL_XFORM, INSTALL_XFORM1): Restore. - (CC_FOR_BUILD): Restore. - (gencode): Build using $(CC_FOR_BUILD). - (install): Don't install in $(tooldir). - -Thu Sep 7 15:02:31 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - (Try to) Update to new bfd autoconf scheme. - * run.c: Don't include sysdep.h. - * Makefile.in (INSTALL{,_PROGRAM,_DATA}): Use autoconf computed value. - (CC, CFLAGS, AR, RANLIB): Likewise. - (HDEFINES, TDEFINES): Define. - (CC_FOR_BUILD): Delete. - (host_makefile_frag): Delete. - (Makefile): Don't depend on frags. - * configure.in (sysdep.h): Don't create symlink. - (host_makefile_frag, frags): Deleted. - (CC, CFLAGS, AR, RANLIB, INSTALL): Compute values. - * configure: Regenerated. - -Thu Aug 31 12:39:07 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * interp.c: Include <math.h>. - -Wed Aug 30 22:05:17 1995 Jeff Law (law@snake.cs.utah.edu) - - * Makefile.in (run): Link in math library too. - * gencode.c (gensim): abort if an unknown opcode is encountered. - * interp.c (FPSCR, FPUL): Define. - (struct save_state): Add fields for floating point registers, - FPSCR and FPUL. - (sim_resume): Add 'F' for accessing floating point registers - in the save state structure. - * gencode.c: Add sh3e opcodes. - (gensym): Define a buffer for int<->fp conversions. - -Tue Aug 22 14:16:46 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * interp.c (trap): Use trap vector 34 for host system interface. - * gencode.c: Add 34 to conditional which determines which traps - will be handled by simulator. - -Fri Aug 11 17:59:15 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * run.c: Include <signal.h>. Define SIGQUIT if not defined. - (main): New variables reason and sigrc. After simulator exits, - check to see if it exited because of a signal, and if so, then - use the signal number as the return value. - -Thu Aug 3 10:45:37 1995 Fred Fish <fnf@cygnus.com> - - * Update all FSF addresses except those in COPYING* files. - -Tue Jul 18 23:33:10 1995 Fred Fish <fnf@fishbowl> - - * interp.c (trap): Only use SYS_execv if defined. Might be - implemented as execve(arg1,arg2,0), as with Unixware 2.0. - (sim_resume): In sbit initializer, cast shifted arg to unsigned - to avoid signed integer overflow. - -Wed Jul 5 14:32:54 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * Makefile.in (clean): Remove run, libsim.a. - (distclean, mostlyclean, realclean): Remove Makefile and - autoconf files. - - * sh.mt: Removed. - - * Makefile.in, configure.in: converted to autoconf. - * configure: New file, generated with autconf 2.4. - -Fri Jun 30 16:51:38 1995 Stan Shebs <shebs@andros.cygnus.com> - - * interp.c (sim_open): If argument supplied, interpret as - desired memory size. - (parse_and_set_memory_size): New function. - (sim_do_command): New function. - -Thu Jun 29 10:02:28 1995 Fred Fish <fnf@deneb.cygnus.com> - - * interp.c (SYS_wait): Define as SYS_wait4 if available and - SYS_wait is not already defined (SunOS 4.1.3 for example). - (SYS_utime): Define as SYS_utimes if available and - SYS_utime is not already defined. - -Thu Jun 22 17:25:57 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * interp.c: Don't include sys/times.h or sys/param.h - -Wed Jun 21 15:03:49 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * interp.c (SIGBUS, SIGTERM): Define if not. - (sim_memory_size): default to 2^19 on PCs. - (sim_resume): Poll for quits on win32. - -Wed May 24 16:22:48 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * gencode.c (op_tab): Add SH3 support. - -Wed May 24 14:07:11 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * gencode.c (tab): Add bsrf and braf. - -Mon Apr 24 15:09:49 1995 Jason Molenda (crash@cygnus.com) - - * configure.in: use ../../bfd/hosts/std-host.h, not - ../bfd/hosts/std-host.h (which doesn't exist). - -Mon Mar 27 10:32:34 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * run.c: parse arguments with getopt(). - -Sun Feb 26 15:27:24 1995 Steve Chamberlain <sac@cygnus.com> - - * configure.in: Use ../../bfd/hosts/std-host.h if specific - host unavailable. - -Mon Jan 23 16:10:58 1995 Torbjorn Granlund <tege@rtl.cygnus.com> - - * interp.c (macw): Sign extend MACH at bit 10 for non-saturating case. - -Sun Jan 22 13:55:36 1995 Torbjorn Granlund <tege@rtl.cygnus.com> - - * gencode.c (op_tab): Make MAC.W call macw, not abort. - * interp.c (macw): New function. - (S): New #define. - -Sat Jan 21 15:52:30 1995 Torbjorn Granlund <tege@rtl.cygnus.com> - - * gencode.c (op_tab): New code for ADDV and SUBV. - Make MAC.L abort sicne it is not implemented. - - * interp.c (dmul): Handle the signed case by adjusting after unsigned multiply. - Get rid of __GNUC__ conditional. - -aThu Jan 19 05:50:50 1995 Torbjorn Granlund <tege@rtl.cygnus.com> - - * gencode.c (op_tab): Also replace NEGC, and try again with SUBC. - Change ADDC for symmetry. - - * gencode.c (op_tab): Replace code for ADDC and SUBC. - -Mon Jan 9 15:43:53 1995 Stu Grossman (grossman@cygnus.com) - - * interp.c: Remove def of INLINE. This comes from bfd.h. Also, - declare IOMEM before using it. - -Wed Dec 28 21:25:31 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * interp.c (BUSERROR): New macro. - ([r|w][bwl]at[little|big]) New functions. - (sim_resume): If GO32 check for interrupt every now - and again. Decrement PC if SIGBUS seen. - * run.c (main): Return result of simulated _exit. - -Mon Dec 5 21:59:51 1994 Doug Evans <dje@canuck.cygnus.com> - - * Makefile.in (gencode): Allow build in different directory. - -Wed Nov 30 17:47:13 1994 Jim Wilson <wilson@chestnut.cygnus.com> - - * Makefile.in (gencode): Change $< to gencode.c for portability. - -Wed Nov 23 21:31:55 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * interp.c ([wr][bwl]at): New functions. - (trap): Cope with both byte modes. - -Thu Sep 8 17:35:07 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * gencode.c (tab): Simulate T bit after a negc insn right. - * interp.c (RSBAT): Sign extend the arg. - (ACE_FAST): New macro. - (sim_resume): Remove obsolete test of sim_timeout. - -Fri Aug 5 14:12:31 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * interp.c (IOMEM): New function, simulates very basic I/O area of - the SH. - (WBAT, RBAT) : Call I/O functions. - * gencode.c (tab): Special case trapa #3. - -Mon Jun 27 18:04:54 1994 Steve Chamberlain (sac@cirdan.cygnus.com) - - * run.c (main): Specify the file type again. - -Thu May 26 19:04:37 1994 Steve Chamberlain (sac@thepub.cygnus.com) - - * interp.c (trap): Fix irix incompatibility. - * run.c (main): open without specifying file type. - -Wed May 18 14:18:53 1994 Doug Evans (dje@canuck.cygnus.com) - - * interp.c (sim_*): Make result void where there isn't one. - (sim_set_pc): Delete. - (sim_info): Delete printf_fn arg, all callers changed. - Call printf_filtered instead. - (sim_close): New function. - (sim_load): New function. - (sim_create_inferior): Renamed from sim_set_args, all callers changed. - * run.c: #include <varargs.h>, "remote-sim.h". - (printf_filtered): New function. - -Wed Apr 27 12:03:48 1994 Steve Chamberlain (sac@cygnus.com) - - * gencode.c (table): Get direction of some opcodes right. - (trapa, rte): Implement fully. - * interp.c (trap): Make stat call more portable. - -Fri Feb 11 21:59:38 1994 Steve Chamberlain (sac@sphagnum.cygnus.com) - - * gencode.c (main, gendefines): New -d option prints table of defines. - * interp.c (trap): Add a load of system calls. - (sim_memory_size): Now default to 8Mbyte. - (PARANOID): Keep vector of registers with undefined contents. - -Mon Nov 15 14:37:18 1993 Steve Chamberlain (sac@jonny.cygnus.com) - - * gencode.c: mova uses aligned addresses - * interp.c (trap): Return results in r0. - -Tue Oct 26 10:38:55 1993 Doug Evans (dje@canuck.cygnus.com) - - * Makefile.in (CSEARCH): Add -I$(srcdir)/../../gdb - * interp.c: #include "remote-sim.h". - (sim_resume): int result, new arg `siggnal'. - (sim_write): Use SIM_ADDR for type of arg `addr'. - (sim_read): Use SIM_ADDR for type of arg `addr'. - Use unsigned char * for `buffer'. - (sim_store_register): int result. - (sim_fetch_register): Ditto. - (sim_stop_reason): Renamed from sim_stop_signal. New arg `reason'. - (sim_set_pc): int result, use SIM_ADDR for type of arg `x'. - (sim_info): int result, new args `verbose', `printf_fn'. - (sim_kill): int result. - (sim_open): int result, new arg `name'. - * run.c: #include <stdio.h> - (main): Update call to sim_info. - -Sat Oct 23 15:09:29 1993 Doug Evans (dje@canuck.cygnus.com) - - * interp.c (sim_stop_signal): Result is now enum sim_stop. - -Fri Oct 8 10:47:09 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * gencode.c (table): Becomes unsigned. - * interp.c (trap): Get right breakpoint SIGnum. (sim_write, - sim_read): Return number of bytes copied. (sim_store_register): - Value passed by reference. (sim_kill, sim_open, sim_set_args): New functions. - -Tue Sep 7 16:24:13 1993 Stan Shebs (shebs@rtl.cygnus.com) - - * interp.c (sim_info): Fix small typo in printf string. - -Thu Aug 5 11:37:48 1993 Stan Shebs (shebs@rtl.cygnus.com) - - * interp.c (sim_resume): Set memory after pointers inited. - -Mon Aug 2 14:13:22 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * interp.c (get_now): Use time system call. - * Makefile.in: install correctly. - -Tue Jul 6 10:30:46 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * run.c (main), interp.c (sim_set_timeout): Remove timeout - functionality. - -Thu Jun 24 13:29:57 1993 david d `zoo' zuhn (zoo at rtl.cygnus.com) - - * Makefile.in: don't run indent everytime; also add a space in the - includes - -Thu Jun 17 18:30:42 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * gencode.c: Fix some opcodes. - * interp.c: Support for profiling and portability fixes. - * run.c (main): Get profiling args. - -Wed May 5 13:17:22 1993 Steve Chamberlain (sac@cygnus.com) - - * gencode.c (tab): Lint for sgi compiler - * interp.c: Lint for sgi compiler. - -Mon May 3 15:25:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * run.c (main): Support for resizing simulated RAM. - * Makefile.in: Support for broken makes. - * interp.c, gencode.c: Lint. - -Mon Apr 26 18:01:10 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * created - diff --git a/sim/sh/Makefile.in b/sim/sh/Makefile.in deleted file mode 100644 index 784c39a..0000000 --- a/sim/sh/Makefile.in +++ /dev/null @@ -1,44 +0,0 @@ -# Makefile template for Configure for the SH sim library. -# Copyright (C) 1990, 91, 92, 95, 96, 1997 Free Software Foundation, Inc. -# Written by Cygnus Support. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -## COMMON_PRE_CONFIG_FRAG - -SIM_OBJS = interp.o table.o sim-load.o -SIM_EXTRA_LIBS = -lm -SIM_EXTRA_CLEAN = sh-clean - -## COMMON_POST_CONFIG_FRAG - -interp.o: interp.c code.c table.c ppi.c $(srcroot)/include/gdb/sim-sh.h - -code.c: gencode - ./gencode -x >code.c -# indent code.c - -table.c: gencode - ./gencode -s >table.c -# indent table.c - -ppi.c: gencode - ./gencode -p >ppi.c - -gencode: gencode.c - $(CC_FOR_BUILD) -o gencode $(srcdir)/gencode.c - -sh-clean: - rm -f gencode code.c table.c diff --git a/sim/sh/acconfig.h b/sim/sh/acconfig.h deleted file mode 100644 index f9b87a1..0000000 --- a/sim/sh/acconfig.h +++ /dev/null @@ -1,15 +0,0 @@ - -/* Define to 1 if NLS is requested. */ -#undef ENABLE_NLS - -/* Define as 1 if you have catgets and don't want to use GNU gettext. */ -#undef HAVE_CATGETS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - -/* Define as 1 if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES diff --git a/sim/sh/config.in b/sim/sh/config.in deleted file mode 100644 index 1f87a2b..0000000 --- a/sim/sh/config.in +++ /dev/null @@ -1,158 +0,0 @@ -/* config.in. Generated automatically from configure.in by autoheader. */ - -/* Define if using alloca.c. */ -#undef C_ALLOCA - -/* Define to empty if the keyword does not work. */ -#undef const - -/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. - This function is required for alloca.c support on those systems. */ -#undef CRAY_STACKSEG_END - -/* Define if you have alloca, as a function or macro. */ -#undef HAVE_ALLOCA - -/* Define if you have <alloca.h> and it should be used (not on Ultrix). */ -#undef HAVE_ALLOCA_H - -/* Define if you have a working `mmap' system call. */ -#undef HAVE_MMAP - -/* Define as __inline if that's what the C compiler calls it. */ -#undef inline - -/* Define to `long' if <sys/types.h> doesn't define. */ -#undef off_t - -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - -/* Define as the return type of signal handlers (int or void). */ -#undef RETSIGTYPE - -/* Define to `unsigned' if <sys/types.h> doesn't define. */ -#undef size_t - -/* If using the C implementation of alloca, define if you know the - direction of stack growth for your system; otherwise it will be - automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown - */ -#undef STACK_DIRECTION - -/* Define if you have the ANSI C header files. */ -#undef STDC_HEADERS - -/* Define to 1 if NLS is requested. */ -#undef ENABLE_NLS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - -/* Define as 1 if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES - -/* Define if you have the __argz_count function. */ -#undef HAVE___ARGZ_COUNT - -/* Define if you have the __argz_next function. */ -#undef HAVE___ARGZ_NEXT - -/* Define if you have the __argz_stringify function. */ -#undef HAVE___ARGZ_STRINGIFY - -/* Define if you have the __setfpucw function. */ -#undef HAVE___SETFPUCW - -/* Define if you have the dcgettext function. */ -#undef HAVE_DCGETTEXT - -/* Define if you have the getcwd function. */ -#undef HAVE_GETCWD - -/* Define if you have the getpagesize function. */ -#undef HAVE_GETPAGESIZE - -/* Define if you have the getrusage function. */ -#undef HAVE_GETRUSAGE - -/* Define if you have the munmap function. */ -#undef HAVE_MUNMAP - -/* Define if you have the putenv function. */ -#undef HAVE_PUTENV - -/* Define if you have the setenv function. */ -#undef HAVE_SETENV - -/* Define if you have the setlocale function. */ -#undef HAVE_SETLOCALE - -/* Define if you have the sigaction function. */ -#undef HAVE_SIGACTION - -/* Define if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if you have the strcasecmp function. */ -#undef HAVE_STRCASECMP - -/* Define if you have the strchr function. */ -#undef HAVE_STRCHR - -/* Define if you have the time function. */ -#undef HAVE_TIME - -/* Define if you have the <argz.h> header file. */ -#undef HAVE_ARGZ_H - -/* Define if you have the <fcntl.h> header file. */ -#undef HAVE_FCNTL_H - -/* Define if you have the <fpu_control.h> header file. */ -#undef HAVE_FPU_CONTROL_H - -/* Define if you have the <limits.h> header file. */ -#undef HAVE_LIMITS_H - -/* Define if you have the <locale.h> header file. */ -#undef HAVE_LOCALE_H - -/* Define if you have the <malloc.h> header file. */ -#undef HAVE_MALLOC_H - -/* Define if you have the <nl_types.h> header file. */ -#undef HAVE_NL_TYPES_H - -/* Define if you have the <stdlib.h> header file. */ -#undef HAVE_STDLIB_H - -/* Define if you have the <string.h> header file. */ -#undef HAVE_STRING_H - -/* Define if you have the <strings.h> header file. */ -#undef HAVE_STRINGS_H - -/* Define if you have the <sys/param.h> header file. */ -#undef HAVE_SYS_PARAM_H - -/* Define if you have the <sys/resource.h> header file. */ -#undef HAVE_SYS_RESOURCE_H - -/* Define if you have the <sys/time.h> header file. */ -#undef HAVE_SYS_TIME_H - -/* Define if you have the <time.h> header file. */ -#undef HAVE_TIME_H - -/* Define if you have the <unistd.h> header file. */ -#undef HAVE_UNISTD_H - -/* Define if you have the <values.h> header file. */ -#undef HAVE_VALUES_H diff --git a/sim/sh/configure b/sim/sh/configure deleted file mode 100755 index 63f6cc3..0000000 --- a/sim/sh/configure +++ /dev/null @@ -1,5973 +0,0 @@ -#! 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Super-H architecture. - - Written by Steve Chamberlain of Cygnus Support. - sac@cygnus.com - - This file is part of SH sim. - - - THIS SOFTWARE IS NOT COPYRIGHTED - - Cygnus offers the following for use in the public domain. Cygnus - makes no warranty with regard to the software or it's performance - and the user accepts the software "AS IS" with all faults. - - CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO - THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -*/ - -/* This program generates the opcode table for the assembler and - the simulator code. - - -t prints a pretty table for the assembler manual - -s generates the simulator code jump table - -d generates a define table - -x generates the simulator code switch statement - default used to generate the opcode tables - -*/ - -#include <stdio.h> - -#define MAX_NR_STUFF 42 - -typedef struct -{ - char *defs; - char *refs; - char *name; - char *code; - char *stuff[MAX_NR_STUFF]; - int index; -} op; - - -op tab[] = -{ - - { "n", "", "add #<imm>,<REG_N>", "0111nnnni8*1....", - "R[n] += SEXT (i);", - "if (i == 0) {", - " UNDEF(n); /* see #ifdef PARANOID */", - " break;", - "}", - }, - { "n", "mn", "add <REG_M>,<REG_N>", "0011nnnnmmmm1100", - "R[n] += R[m];", - }, - - { "n", "mn", "addc <REG_M>,<REG_N>", "0011nnnnmmmm1110", - "ult = R[n] + T;", - "SET_SR_T (ult < R[n]);", - "R[n] = ult + R[m];", - "SET_SR_T (T || (R[n] < ult));", - }, - - { "n", "mn", "addv <REG_M>,<REG_N>", "0011nnnnmmmm1111", - "ult = R[n] + R[m];", - "SET_SR_T ((~(R[n] ^ R[m]) & (ult ^ R[n])) >> 31);", - "R[n] = ult;", - }, - - { "0", "0", "and #<imm>,R0", "11001001i8*1....", - "R0 &= i;", - }, - { "n", "nm", "and <REG_M>,<REG_N>", "0010nnnnmmmm1001", - "R[n] &= R[m];", - }, - { "", "0", "and.b #<imm>,@(R0,GBR)", "11001101i8*1....", - "MA (1);", - "WBAT (GBR + R0, RBAT (GBR + R0) & i);", - }, - - { "", "", "bf <bdisp8>", "10001011i8p1....", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (!T) {", - " SET_NIP (PC + 4 + (SEXT (i) * 2));", - " cycles += 2;", - "}", - }, - - { "", "", "bf.s <bdisp8>", "10001111i8p1....", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (!T) {", - " SET_NIP (PC + 4 + (SEXT (i) * 2));", - " cycles += 2;", - " Delay_Slot (PC + 2);", - "}", - }, - - { "", "n", "bit32 #imm3,@(disp12,<REG_N>)", "0011nnnni8*11001", - "/* 32-bit logical bit-manipulation instructions. */", - "int word2 = RIAT (nip);", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "i >>= 4; /* BOGUS: Using only three bits of 'i'. */", - "/* MSB of 'i' must be zero. */", - "if (i > 7)", - " RAISE_EXCEPTION (SIGILL);", - "MA (1);", - "do_blog_insn (1 << i, (word2 & 0xfff) + R[n], ", - " (word2 >> 12) & 0xf, memory, maskb);", - "SET_NIP (nip + 2); /* Consume 2 more bytes. */", - }, - { "", "", "bra <bdisp12>", "1010i12.........", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (PC + 4 + (SEXT12 (i) * 2));", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - - { "", "n", "braf <REG_N>", "0000nnnn00100011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (PC + 4 + R[n]);", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - - { "", "", "bsr <bdisp12>", "1011i12.........", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "PR = PH2T (PC + 4);", - "SET_NIP (PC + 4 + (SEXT12 (i) * 2));", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - - { "", "n", "bsrf <REG_N>", "0000nnnn00000011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "PR = PH2T (PC) + 4;", - "SET_NIP (PC + 4 + R[n]);", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - - { "", "", "bt <bdisp8>", "10001001i8p1....", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (T) {", - " SET_NIP (PC + 4 + (SEXT (i) * 2));", - " cycles += 2;", - "}", - }, - - { "", "m", "bld/st #<imm>, <REG_M>", "10000111mmmmi4*1", - "/* MSB of 'i' is true for load, false for store. */", - "if (i <= 7)", - " if (T)", - " R[m] |= (1 << i);", - " else", - " R[m] &= ~(1 << i);", - "else", - " SET_SR_T ((R[m] & (1 << (i - 8))) != 0);", - }, - { "m", "m", "bset/clr #<imm>, <REG_M>", "10000110mmmmi4*1", - "/* MSB of 'i' is true for set, false for clear. */", - "if (i <= 7)", - " R[m] &= ~(1 << i);", - "else", - " R[m] |= (1 << (i - 8));", - }, - { "n", "n", "clips.b <REG_N>", "0100nnnn10010001", - "if (R[n] < -128 || R[n] > 127) {", - " L (n);", - " SET_SR_CS (1);", - " if (R[n] > 127)", - " R[n] = 127;", - " else if (R[n] < -128)", - " R[n] = -128;", - "}", - }, - { "n", "n", "clips.w <REG_N>", "0100nnnn10010101", - "if (R[n] < -32768 || R[n] > 32767) {", - " L (n);", - " SET_SR_CS (1);", - " if (R[n] > 32767)", - " R[n] = 32767;", - " else if (R[n] < -32768)", - " R[n] = -32768;", - "}", - }, - { "n", "n", "clipu.b <REG_N>", "0100nnnn10000001", - "if (R[n] < -256 || R[n] > 255) {", - " L (n);", - " SET_SR_CS (1);", - " R[n] = 255;", - "}", - }, - { "n", "n", "clipu.w <REG_N>", "0100nnnn10000101", - "if (R[n] < -65536 || R[n] > 65535) {", - " L (n);", - " SET_SR_CS (1);", - " R[n] = 65535;", - "}", - }, - { "n", "0n", "divs R0,<REG_N>", "0100nnnn10010100", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (R0 == 0)", - " R[n] = 0x7fffffff;", - "else if (R0 == -1 && R[n] == 0x80000000)", - " R[n] = 0x7fffffff;", - "else R[n] /= R0;", - "L (n);", - }, - { "n", "0n", "divu R0,<REG_N>", "0100nnnn10000100", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (R0 == 0)", - " R[n] = 0xffffffff;", - "/* FIXME: The result may be implementation-defined if it is outside */", - "/* the range of signed int (i.e. if R[n] was negative and R0 == 1). */", - "else R[n] = R[n] / (unsigned int) R0;", - "L (n);", - }, - { "n", "0n", "mulr R0,<REG_N>", "0100nnnn10000000", - "R[n] = (R[n] * R0) & 0xffffffff;", - "L (n);", - }, - { "0", "n", "ldbank @<REG_N>,R0", "0100nnnn11100101", - "int regn = (R[n] >> 2) & 0x1f;", - "int bankn = (R[n] >> 7) & 0x1ff;", - "if (regn > 19)", - " regn = 19; /* FIXME what should happen? */", - "R0 = saved_state.asregs.regstack[bankn].regs[regn];", - "L (0);", - }, - { "", "0n", "stbank R0,@<REG_N>", "0100nnnn11100001", - "int regn = (R[n] >> 2) & 0x1f;", - "int bankn = (R[n] >> 7) & 0x1ff;", - "if (regn > 19)", - " regn = 19; /* FIXME what should happen? */", - "saved_state.asregs.regstack[bankn].regs[regn] = R0;", - }, - { "", "", "resbank", "0000000001011011", - "int i;", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - /* FIXME: cdef all */ - "if (BO) { /* Bank Overflow */", - /* FIXME: how do we know when to reset BO? */ - " for (i = 0; i <= 14; i++) {", - " R[i] = RLAT (R[15]);", - " MA (1);", - " R[15] += 4;", - " }", - " PR = RLAT (R[15]);", - " R[15] += 4;", - " MA (1);", - " GBR = RLAT (R[15]);", - " R[15] += 4;", - " MA (1);", - " MACH = RLAT (R[15]);", - " R[15] += 4;", - " MA (1);", - " MACL = RLAT (R[15]);", - " R[15] += 4;", - " MA (1);", - "}", - "else if (BANKN == 0) /* Bank Underflow */", - " RAISE_EXCEPTION (SIGILL);", /* FIXME: what exception? */ - "else {", - " SET_BANKN (BANKN - 1);", - " for (i = 0; i <= 14; i++)", - " R[i] = saved_state.asregs.regstack[BANKN].regs[i];", - " MACH = saved_state.asregs.regstack[BANKN].regs[15];", - " PR = saved_state.asregs.regstack[BANKN].regs[17];", - " GBR = saved_state.asregs.regstack[BANKN].regs[18];", - " MACL = saved_state.asregs.regstack[BANKN].regs[19];", - "}", - }, - { "f", "f-", "movml.l <REG_N>,@-R15", "0100nnnn11110001", - "/* Push Rn...R0 (if n==15, push pr and R14...R0). */", - "do {", - " MA (1);", - " R[15] -= 4;", - " if (n == 15)", - " WLAT (R[15], PR);", - " else", - " WLAT (R[15], R[n]);", - "} while (n-- > 0);", - }, - { "f", "f+", "movml.l @R15+,<REG_N>", "0100nnnn11110101", - "/* Pop R0...Rn (if n==15, pop R0...R14 and pr). */", - "int i = 0;\n", - "do {", - " MA (1);", - " if (i == 15)", - " PR = RLAT (R[15]);", - " else", - " R[i] = RLAT (R[15]);", - " R[15] += 4;", - "} while (i++ < n);", - }, - { "f", "f-", "movmu.l <REG_N>,@-R15", "0100nnnn11110000", - "/* Push pr, R14...Rn (if n==15, push pr). */", /* FIXME */ - "int i = 15;\n", - "do {", - " MA (1);", - " R[15] -= 4;", - " if (i == 15)", - " WLAT (R[15], PR);", - " else", - " WLAT (R[15], R[i]);", - "} while (i-- > n);", - }, - { "f", "f+", "movmu.l @R15+,<REG_N>", "0100nnnn11110100", - "/* Pop Rn...R14, pr (if n==15, pop pr). */", /* FIXME */ - "do {", - " MA (1);", - " if (n == 15)", - " PR = RLAT (R[15]);", - " else", - " R[n] = RLAT (R[15]);", - " R[15] += 4;", - "} while (n++ < 15);", - }, - { "", "", "nott", "0000000001101000", - "SET_SR_T (T == 0);", - }, - - { "", "", "bt.s <bdisp8>", "10001101i8p1....", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (T) {", - " SET_NIP (PC + 4 + (SEXT (i) * 2));", - " cycles += 2;", - " Delay_Slot (PC + 2);", - "}", - }, - - { "", "", "clrmac", "0000000000101000", - "MACH = 0;", - "MACL = 0;", - }, - - { "", "", "clrs", "0000000001001000", - "SET_SR_S (0);", - }, - - { "", "", "clrt", "0000000000001000", - "SET_SR_T (0);", - }, - - /* sh4a */ - { "", "", "clrdmxy", "0000000010001000", - "saved_state.asregs.cregs.named.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);" - }, - - { "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....", - "SET_SR_T (R0 == SEXT (i));", - }, - { "", "mn", "cmp/eq <REG_M>,<REG_N>", "0011nnnnmmmm0000", - "SET_SR_T (R[n] == R[m]);", - }, - { "", "mn", "cmp/ge <REG_M>,<REG_N>", "0011nnnnmmmm0011", - "SET_SR_T (R[n] >= R[m]);", - }, - { "", "mn", "cmp/gt <REG_M>,<REG_N>", "0011nnnnmmmm0111", - "SET_SR_T (R[n] > R[m]);", - }, - { "", "mn", "cmp/hi <REG_M>,<REG_N>", "0011nnnnmmmm0110", - "SET_SR_T (UR[n] > UR[m]);", - }, - { "", "mn", "cmp/hs <REG_M>,<REG_N>", "0011nnnnmmmm0010", - "SET_SR_T (UR[n] >= UR[m]);", - }, - { "", "n", "cmp/pl <REG_N>", "0100nnnn00010101", - "SET_SR_T (R[n] > 0);", - }, - { "", "n", "cmp/pz <REG_N>", "0100nnnn00010001", - "SET_SR_T (R[n] >= 0);", - }, - { "", "mn", "cmp/str <REG_M>,<REG_N>", "0010nnnnmmmm1100", - "ult = R[n] ^ R[m];", - "SET_SR_T (((ult & 0xff000000) == 0)", - " | ((ult & 0xff0000) == 0)", - " | ((ult & 0xff00) == 0)", - " | ((ult & 0xff) == 0));", - }, - - { "", "mn", "div0s <REG_M>,<REG_N>", "0010nnnnmmmm0111", - "SET_SR_Q ((R[n] & sbit) != 0);", - "SET_SR_M ((R[m] & sbit) != 0);", - "SET_SR_T (M != Q);", - }, - - { "", "", "div0u", "0000000000011001", - "SET_SR_M (0);", - "SET_SR_Q (0);", - "SET_SR_T (0);", - }, - - { "n", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", - "div1 (&R0, m, n/*, T*/);", - }, - - { "", "nm", "dmuls.l <REG_M>,<REG_N>", "0011nnnnmmmm1101", - "dmul (1/*signed*/, R[n], R[m]);", - }, - - { "", "nm", "dmulu.l <REG_M>,<REG_N>", "0011nnnnmmmm0101", - "dmul (0/*unsigned*/, R[n], R[m]);", - }, - - { "n", "n", "dt <REG_N>", "0100nnnn00010000", - "R[n]--;", - "SET_SR_T (R[n] == 0);", - }, - - { "n", "m", "exts.b <REG_M>,<REG_N>", "0110nnnnmmmm1110", - "R[n] = SEXT (R[m]);", - }, - { "n", "m", "exts.w <REG_M>,<REG_N>", "0110nnnnmmmm1111", - "R[n] = SEXTW (R[m]);", - }, - - { "n", "m", "extu.b <REG_M>,<REG_N>", "0110nnnnmmmm1100", - "R[n] = (R[m] & 0xff);", - }, - { "n", "m", "extu.w <REG_M>,<REG_N>", "0110nnnnmmmm1101", - "R[n] = (R[m] & 0xffff);", - }, - - /* sh2e */ - { "", "", "fabs <FREG_N>", "1111nnnn01011101", - "FP_UNARY (n, fabs);", - "/* FIXME: FR (n) &= 0x7fffffff; */", - }, - - /* sh2e */ - { "", "", "fadd <FREG_M>,<FREG_N>", "1111nnnnmmmm0000", - "FP_OP (n, +, m);", - }, - - /* sh2e */ - { "", "", "fcmp/eq <FREG_M>,<FREG_N>", "1111nnnnmmmm0100", - "FP_CMP (n, ==, m);", - }, - /* sh2e */ - { "", "", "fcmp/gt <FREG_M>,<FREG_N>", "1111nnnnmmmm0101", - "FP_CMP (n, >, m);", - }, - - /* sh4 */ - { "", "", "fcnvds <DR_N>,FPUL", "1111nnnn10111101", - "if (! FPSCR_PR || n & 1)", - " RAISE_EXCEPTION (SIGILL);", - "else", - "{", - " union", - " {", - " int i;", - " float f;", - " } u;", - " u.f = DR (n);", - " FPUL = u.i;", - "}", - }, - - /* sh4 */ - { "", "", "fcnvsd FPUL,<DR_N>", "1111nnnn10101101", - "if (! FPSCR_PR || n & 1)", - " RAISE_EXCEPTION (SIGILL);", - "else", - "{", - " union", - " {", - " int i;", - " float f;", - " } u;", - " u.i = FPUL;", - " SET_DR (n, u.f);", - "}", - }, - - /* sh2e */ - { "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011", - "FP_OP (n, /, m);", - "/* FIXME: check for DP and (n & 1) == 0? */", - }, - - /* sh4 */ - { "", "", "fipr <FV_M>,<FV_N>", "1111vvVV11101101", - "if (FPSCR_PR)", - " RAISE_EXCEPTION (SIGILL);", - "else", - "{", - " double fsum = 0;", - " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", - " RAISE_EXCEPTION (SIGILL);", - " /* FIXME: check for nans and infinities. */", - " fsum += FR (v1+0) * FR (v2+0);", - " fsum += FR (v1+1) * FR (v2+1);", - " fsum += FR (v1+2) * FR (v2+2);", - " fsum += FR (v1+3) * FR (v2+3);", - " SET_FR (v1+3, fsum);", - "}", - }, - - /* sh2e */ - { "", "", "fldi0 <FREG_N>", "1111nnnn10001101", - "SET_FR (n, (float) 0.0);", - "/* FIXME: check for DP and (n & 1) == 0? */", - }, - - /* sh2e */ - { "", "", "fldi1 <FREG_N>", "1111nnnn10011101", - "SET_FR (n, (float) 1.0);", - "/* FIXME: check for DP and (n & 1) == 0? */", - }, - - /* sh2e */ - { "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101", - " union", - " {", - " int i;", - " float f;", - " } u;", - " u.f = FR (n);", - " FPUL = u.i;", - }, - - /* sh2e */ - { "", "", "float FPUL,<FREG_N>", "1111nnnn00101101", - /* sh4 */ - "if (FPSCR_PR)", - " SET_DR (n, (double) FPUL);", - "else", - "{", - " SET_FR (n, (float) FPUL);", - "}", - }, - - /* sh2e */ - { "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110", - "SET_FR (n, FR (m) * FR (0) + FR (n));", - "/* FIXME: check for DP and (n & 1) == 0? */", - }, - - /* sh2e */ - { "", "", "fmov <FREG_M>,<FREG_N>", "1111nnnnmmmm1100", - /* sh4 */ - "if (FPSCR_SZ) {", - " int ni = XD_TO_XF (n);", - " int mi = XD_TO_XF (m);", - " SET_XF (ni + 0, XF (mi + 0));", - " SET_XF (ni + 1, XF (mi + 1));", - "}", - "else", - "{", - " SET_FR (n, FR (m));", - "}", - }, - /* sh2e */ - { "", "n", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " WDAT (R[n], m);", - "}", - "else", - "{", - " MA (1);", - " WLAT (R[n], FI (m));", - "}", - }, - /* sh2e */ - { "", "m", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " RDAT (R[m], n);", - "}", - "else", - "{", - " MA (1);", - " SET_FI (n, RLAT (R[m]));", - "}", - }, - /* sh2a */ - { "", "n", "fmov.s @(disp12,<REG_N>), <FREG_M>", "0011nnnnmmmm0001", - "/* and fmov.s <FREG_N>, @(disp12,<FREG_M>)", - " and mov.bwl <REG_N>, @(disp12,<REG_M>)", - " and mov.bwl @(disp12,<REG_N>),<REG_M>", - " and movu.bw @(disp12,<REG_N>),<REG_M>. */", - "int word2 = RIAT (nip);", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (nip + 2); /* Consume 2 more bytes. */", - "MA (1);", - "do_long_move_insn (word2 & 0xf000, word2 & 0x0fff, m, n, &thislock);", - }, - /* sh2e */ - { "m", "m", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " RDAT (R[m], n);", - " R[m] += 8;", - "}", - "else", - "{", - " MA (1);", - " SET_FI (n, RLAT (R[m]));", - " R[m] += 4;", - "}", - }, - /* sh2e */ - { "n", "n", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " R[n] -= 8;", - " WDAT (R[n], m);", - "}", - "else", - "{", - " MA (1);", - " R[n] -= 4;", - " WLAT (R[n], FI (m));", - "}", - }, - /* sh2e */ - { "", "0m", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " RDAT (R[0]+R[m], n);", - "}", - "else", - "{", - " MA (1);", - " SET_FI (n, RLAT (R[0] + R[m]));", - "}", - }, - /* sh2e */ - { "", "0n", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111", - /* sh4 */ - "if (FPSCR_SZ) {", - " MA (2);", - " WDAT (R[0]+R[n], m);", - "}", - "else", - "{", - " MA (1);", - " WLAT ((R[0]+R[n]), FI (m));", - "}", - }, - - /* sh4: - See fmov instructions above for move to/from extended fp registers. */ - - /* sh2e */ - { "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010", - "FP_OP (n, *, m);", - }, - - /* sh2e */ - { "", "", "fneg <FREG_N>", "1111nnnn01001101", - "FP_UNARY (n, -);", - }, - - /* sh4a */ - { "", "", "fpchg", "1111011111111101", - "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_PR);", - }, - - /* sh4 */ - { "", "", "frchg", "1111101111111101", - "if (FPSCR_PR)", - " RAISE_EXCEPTION (SIGILL);", - "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", - " RAISE_EXCEPTION (SIGILL);", - "else", - " SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_FR);", - }, - - /* sh4 */ - { "", "", "fsca", "1111eeee11111101", - "if (FPSCR_PR)", - " RAISE_EXCEPTION (SIGILL);", - "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", - " RAISE_EXCEPTION (SIGILL);", - "else", - " {", - " SET_FR (n, fsca_s (FPUL, &sin));", - " SET_FR (n+1, fsca_s (FPUL, &cos));", - " }", - }, - - /* sh4 */ - { "", "", "fschg", "1111001111111101", - "SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_SZ);", - }, - - /* sh3e */ - { "", "", "fsqrt <FREG_N>", "1111nnnn01101101", - "FP_UNARY (n, sqrt);", - }, - - /* sh4 */ - { "", "", "fsrra <FREG_N>", "1111nnnn01111101", - "if (FPSCR_PR)", - " RAISE_EXCEPTION (SIGILL);", - "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", - " RAISE_EXCEPTION (SIGILL);", - "else", - " SET_FR (n, fsrra_s (FR (n)));", - }, - - /* sh2e */ - { "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001", - "FP_OP (n, -, m);", - }, - - /* sh2e */ - { "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101", - /* sh4 */ - "if (FPSCR_PR) {", - " if (DR (n) != DR (n)) /* NaN */", - " FPUL = 0x80000000;", - " else", - " FPUL = (int) DR (n);", - "}", - "else", - "if (FR (n) != FR (n)) /* NaN */", - " FPUL = 0x80000000;", - "else", - " FPUL = (int) FR (n);", - }, - - /* sh4 */ - { "", "", "ftrv <FV_N>", "1111vv0111111101", - "if (FPSCR_PR)", - " RAISE_EXCEPTION (SIGILL);", - "else", - "{", - " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", - " RAISE_EXCEPTION (SIGILL);", - " /* FIXME not implemented. */", - " printf (\"ftrv xmtrx, FV%d\\n\", v1);", - "}", - }, - - /* sh2e */ - { "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101", - " union", - " {", - " int i;", - " float f;", - " } u;", - " u.i = FPUL;", - " SET_FR (n, u.f);", - }, - - { "", "n", "jmp @<REG_N>", "0100nnnn00101011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (PT2H (R[n]));", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - - { "", "n", "jsr @<REG_N>", "0100nnnn00001011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "PR = PH2T (PC + 4);", - "if (~doprofile)", - " gotcall (PR, R[n]);", - "SET_NIP (PT2H (R[n]));", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - { "", "n", "jsr/n @<REG_N>", "0100nnnn01001011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "PR = PH2T (PC + 2);", - "if (~doprofile)", - " gotcall (PR, R[n]);", - "SET_NIP (PT2H (R[n]));", - }, - { "", "", "jsr/n @@(<disp>,TBR)", "10000011i8p4....", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "PR = PH2T (PC + 2);", - "if (~doprofile)", - " gotcall (PR, i + TBR);", - "SET_NIP (PT2H (i + TBR));", - }, - - { "", "n", "ldc <REG_N>,<CREG_M>", "0100nnnnmmmm1110", - "CREG (m) = R[n];", - "/* FIXME: user mode */", - }, - { "", "n", "ldc <REG_N>,SR", "0100nnnn00001110", - "SET_SR (R[n]);", - "/* FIXME: user mode */", - }, - { "", "n", "ldc <REG_N>,MOD", "0100nnnn01011110", - "SET_MOD (R[n]);", - }, - { "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010", - "if (SR_MD)", - " DBR = R[n]; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "", "n", "ldc <REG_N>,SGR", "0100nnnn00111010", - "if (SR_MD)", - " SGR = R[n]; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "", "n", "ldc <REG_N>,TBR", "0100nnnn01001010", - "if (SR_MD)", /* FIXME? */ - " TBR = R[n]; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111", - "MA (1);", - "CREG (m) = RLAT (R[n]);", - "R[n] += 4;", - "/* FIXME: user mode */", - }, - { "n", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111", - "MA (1);", - "SET_SR (RLAT (R[n]));", - "R[n] += 4;", - "/* FIXME: user mode */", - }, - { "n", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111", - "MA (1);", - "SET_MOD (RLAT (R[n]));", - "R[n] += 4;", - }, - { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110", - "if (SR_MD)", - "{ /* priv mode */", - " MA (1);", - " DBR = RLAT (R[n]);", - " R[n] += 4;", - "}", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "n", "ldc.l @<REG_N>+,SGR", "0100nnnn00110110", - "if (SR_MD)", - "{ /* priv mode */", - " MA (1);", - " SGR = RLAT (R[n]);", - " R[n] += 4;", - "}", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - - /* sh-dsp */ - { "", "", "ldre @(<disp>,PC)", "10001110i8p1....", - "RE = SEXT (i) * 2 + 4 + PH2T (PC);", - }, - { "", "", "ldrs @(<disp>,PC)", "10001100i8p1....", - "RS = SEXT (i) * 2 + 4 + PH2T (PC);", - }, - - /* sh4a */ - { "", "n", "ldrc <REG_N>", "0100nnnn00110100", - "SET_RC (R[n]);", - "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);", - "CHECK_INSN_PTR (insn_ptr);", - "RE |= 1;", - }, - { "", "", "ldrc #<imm>", "10001010i8*1....", - "SET_RC (i);", - "loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);", - "CHECK_INSN_PTR (insn_ptr);", - "RE |= 1;", - }, - - { "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010", - "SREG (m) = R[n];", - }, - { "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110", - "MA (1);", - "SREG (m) = RLAT (R[n]);", - "R[n] += 4;", - }, - /* sh2e / sh-dsp (lds <REG_N>,DSR) */ - { "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010", - "SET_FPSCR (R[n]);", - }, - /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */ - { "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110", - "MA (1);", - "SET_FPSCR (RLAT (R[n]));", - "R[n] += 4;", - }, - - { "", "", "ldtlb", "0000000000111000", - "/* We don't implement cache or tlb, so this is a noop. */", - }, - - { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111", - "macl (&R0, memory, n, m);", - }, - - { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", - "macw (&R0, memory, n, m, endianw);", - }, - - { "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....", - "R[n] = SEXT (i);", - }, - { "n", "", "movi20 #<imm20>,<REG_N>", "0000nnnni8*10000", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "R[n] = ((i << 24) >> 12) | RIAT (nip);", - "SET_NIP (nip + 2); /* Consume 2 more bytes. */", - }, - { "n", "", "movi20s #<imm20>,<REG_N>", "0000nnnni8*10001", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "R[n] = ((((i & 0xf0) << 24) >> 12) | RIAT (nip)) << 8;", - "SET_NIP (nip + 2); /* Consume 2 more bytes. */", - }, - { "n", "m", "mov <REG_M>,<REG_N>", "0110nnnnmmmm0011", - "R[n] = R[m];", - }, - - { "0", "", "mov.b @(<disp>,GBR),R0", "11000100i8*1....", - "MA (1);", - "R0 = RSBAT (i + GBR);", - "L (0);", - }, - { "0", "m", "mov.b @(<disp>,<REG_M>),R0", "10000100mmmmi4*1", - "MA (1);", - "R0 = RSBAT (i + R[m]);", - "L (0);", - }, - { "n", "0m", "mov.b @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1100", - "MA (1);", - "R[n] = RSBAT (R0 + R[m]);", - "L (n);", - }, - { "nm", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100", - "MA (1);", - "R[n] = RSBAT (R[m]);", - "R[m] += 1;", - "L (n);", - }, - { "0n", "n", "mov.b @-<REG_N>,R0", "0100nnnn11001011", - "MA (1);", - "R[n] -= 1;", - "R0 = RSBAT (R[n]);", - "L (0);", - }, - { "", "mn", "mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000", - "MA (1);", - "WBAT (R[n], R[m]);", - }, - { "", "0", "mov.b R0,@(<disp>,GBR)", "11000000i8*1....", - "MA (1);", - "WBAT (i + GBR, R0);", - }, - { "", "m0", "mov.b R0,@(<disp>,<REG_M>)", "10000000mmmmi4*1", - "MA (1);", - "WBAT (i + R[m], R0);", - }, - { "", "mn0", "mov.b <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0100", - "MA (1);", - "WBAT (R[n] + R0, R[m]);", - }, - { "n", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100", - "MA (1);", - "R[n] -= 1;", - "WBAT (R[n], R[m]);", - }, - { "n", "n0", "mov.b R0,@<REG_N>+", "0100nnnn10001011", - "MA (1);", - "WBAT (R[n], R0);", - "R[n] += 1;", - }, - { "n", "m", "mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000", - "MA (1);", - "R[n] = RSBAT (R[m]);", - "L (n);", - }, - - { "0", "", "mov.l @(<disp>,GBR),R0", "11000110i8*4....", - "MA (1);", - "R0 = RLAT (i + GBR);", - "L (0);", - }, - { "n", "", "mov.l @(<disp>,PC),<REG_N>", "1101nnnni8p4....", - "MA (1);", - "R[n] = RLAT ((PH2T (PC) & ~3) + 4 + i);", - "L (n);", - }, - { "n", "m", "mov.l @(<disp>,<REG_M>),<REG_N>", "0101nnnnmmmmi4*4", - "MA (1);", - "R[n] = RLAT (i + R[m]);", - "L (n);", - }, - { "n", "m0", "mov.l @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1110", - "MA (1);", - "R[n] = RLAT (R0 + R[m]);", - "L (n);", - }, - { "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110", - "MA (1);", - "R[n] = RLAT (R[m]);", - "R[m] += 4;", - "L (n);", - }, - { "0n", "n", "mov.l @-<REG_N>,R0", "0100nnnn11101011", - "MA (1);", - "R[n] -= 4;", - "R0 = RLAT (R[n]);", - "L (0);", - }, - { "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010", - "MA (1);", - "R[n] = RLAT (R[m]);", - "L (n);", - }, - { "", "0", "mov.l R0,@(<disp>,GBR)", "11000010i8*4....", - "MA (1);", - "WLAT (i + GBR, R0);", - }, - { "", "nm", "mov.l <REG_M>,@(<disp>,<REG_N>)", "0001nnnnmmmmi4*4", - "MA (1);", - "WLAT (i + R[n], R[m]);", - }, - { "", "nm0", "mov.l <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0110", - "MA (1);", - "WLAT (R0 + R[n], R[m]);", - }, - { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110", - "MA (1) ;", - "R[n] -= 4;", - "WLAT (R[n], R[m]);", - }, - { "n", "n0", "mov.l R0,@<REG_N>+", "0100nnnn10101011", - "MA (1) ;", - "WLAT (R[n], R0);", - "R[n] += 4;", - }, - { "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010", - "MA (1);", - "WLAT (R[n], R[m]);", - }, - - { "0", "", "mov.w @(<disp>,GBR),R0", "11000101i8*2....", - "MA (1);", - "R0 = RSWAT (i + GBR);", - "L (0);", - }, - { "n", "", "mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....", - "MA (1);", - "R[n] = RSWAT (PH2T (PC + 4 + i));", - "L (n);", - }, - { "0", "m", "mov.w @(<disp>,<REG_M>),R0", "10000101mmmmi4*2", - "MA (1);", - "R0 = RSWAT (i + R[m]);", - "L (0);", - }, - { "n", "m0", "mov.w @(R0,<REG_M>),<REG_N>", "0000nnnnmmmm1101", - "MA (1);", - "R[n] = RSWAT (R0 + R[m]);", - "L (n);", - }, - { "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101", - "MA (1);", - "R[n] = RSWAT (R[m]);", - "R[m] += 2;", - "L (n);", - }, - { "0n", "n", "mov.w @-<REG_N>,R0", "0100nnnn11011011", - "MA (1);", - "R[n] -= 2;", - "R0 = RSWAT (R[n]);", - "L (0);", - }, - { "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001", - "MA (1);", - "R[n] = RSWAT (R[m]);", - "L (n);", - }, - { "", "0", "mov.w R0,@(<disp>,GBR)", "11000001i8*2....", - "MA (1);", - "WWAT (i + GBR, R0);", - }, - { "", "0m", "mov.w R0,@(<disp>,<REG_M>)", "10000001mmmmi4*2", - "MA (1);", - "WWAT (i + R[m], R0);", - }, - { "", "m0n", "mov.w <REG_M>,@(R0,<REG_N>)", "0000nnnnmmmm0101", - "MA (1);", - "WWAT (R0 + R[n], R[m]);", - }, - { "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101", - "MA (1);", - "R[n] -= 2;", - "WWAT (R[n], R[m]);", - }, - { "n", "0n", "mov.w R0,@<REG_N>+", "0100nnnn10011011", - "MA (1);", - "WWAT (R[n], R0);", - "R[n] += 2;", - }, - { "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001", - "MA (1);", - "WWAT (R[n], R[m]);", - }, - - { "0", "", "mova @(<disp>,PC),R0", "11000111i8p4....", - "R0 = ((i + 4 + PH2T (PC)) & ~0x3);", - }, - - { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011", - "/* We don't simulate cache, so this insn is identical to mov. */", - "MA (1);", - "WLAT (R[n], R[0]);", - }, - - { "", "n0", "movco.l R0, @<REG_N>", "0000nnnn01110011", - "/* LDST -> T */", - "SET_SR_T (LDST);", - "/* if (T) R0 -> (Rn) */", - "if (T)", - " WLAT (R[n], R[0]);", - "/* 0 -> LDST */", - "SET_LDST (0);", - }, - - { "0", "n", "movli.l @<REG_N>, R0", "0000nnnn01100011", - "/* 1 -> LDST */", - "SET_LDST (1);", - "/* (Rn) -> R0 */", - "R[0] = RLAT (R[n]);", - "/* if (interrupt/exception) 0 -> LDST */", - "/* (we don't simulate asynchronous interrupts/exceptions) */", - }, - - { "n", "", "movt <REG_N>", "0000nnnn00101001", - "R[n] = T;", - }, - { "", "", "movrt <REG_N>", "0000nnnn00111001", - "R[n] = (T == 0);", - }, - { "0", "n", "movua.l @<REG_N>,R0", "0100nnnn10101001", - "int regn = R[n];", - "int e = target_little_endian ? 3 : 0;", - "MA (1);", - "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ", - " (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));", - "L (0);", - }, - { "0n", "n", "movua.l @<REG_N>+,R0", "0100nnnn11101001", - "int regn = R[n];", - "int e = target_little_endian ? 3 : 0;", - "MA (1);", - "R[0] = (RBAT (regn + (0^e)) << 24) + (RBAT (regn + (1^e)) << 16) + ", - " (RBAT (regn + (2^e)) << 8) + RBAT (regn + (3^e));", - "R[n] += 4;", - "L (0);", - }, - { "", "mn", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111", - "MACL = ((int) R[n]) * ((int) R[m]);", - }, -#if 0 /* FIXME: The above cast to int is not really portable. - It should be replaced by a SEXT32 macro. */ - { "", "nm", "mul.l <REG_M>,<REG_N>", "0000nnnnmmmm0111", - "MACL = R[n] * R[m];", - }, -#endif - - /* muls.w - see muls */ - { "", "mn", "muls <REG_M>,<REG_N>", "0010nnnnmmmm1111", - "MACL = ((int) (short) R[n]) * ((int) (short) R[m]);", - }, - - /* mulu.w - see mulu */ - { "", "mn", "mulu <REG_M>,<REG_N>", "0010nnnnmmmm1110", - "MACL = (((unsigned int) (unsigned short) R[n])", - " * ((unsigned int) (unsigned short) R[m]));", - }, - - { "n", "m", "neg <REG_M>,<REG_N>", "0110nnnnmmmm1011", - "R[n] = - R[m];", - }, - - { "n", "m", "negc <REG_M>,<REG_N>", "0110nnnnmmmm1010", - "ult = -T;", - "SET_SR_T (ult > 0);", - "R[n] = ult - R[m];", - "SET_SR_T (T || (R[n] > ult));", - }, - - { "", "", "nop", "0000000000001001", - "/* nop */", - }, - - { "n", "m", "not <REG_M>,<REG_N>", "0110nnnnmmmm0111", - "R[n] = ~R[m];", - }, - - /* sh4a */ - { "", "n", "icbi @<REG_N>", "0000nnnn11100011", - "/* Except for the effect on the cache - which is not simulated -", - " this is like a nop. */", - }, - - { "", "n", "ocbi @<REG_N>", "0000nnnn10010011", - "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */", - "/* FIXME: Cache not implemented */", - }, - - { "", "n", "ocbp @<REG_N>", "0000nnnn10100011", - "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */", - "/* FIXME: Cache not implemented */", - }, - - { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011", - "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */", - "/* FIXME: Cache not implemented */", - }, - - { "0", "", "or #<imm>,R0", "11001011i8*1....", - "R0 |= i;", - }, - { "n", "m", "or <REG_M>,<REG_N>", "0010nnnnmmmm1011", - "R[n] |= R[m];", - }, - { "", "0", "or.b #<imm>,@(R0,GBR)", "11001111i8*1....", - "MA (1);", - "WBAT (R0 + GBR, (RBAT (R0 + GBR) | i));", - }, - - { "", "n", "pref @<REG_N>", "0000nnnn10000011", - "/* Except for the effect on the cache - which is not simulated -", - " this is like a nop. */", - }, - - /* sh4a */ - { "", "n", "prefi @<REG_N>", "0000nnnn11010011", - "/* Except for the effect on the cache - which is not simulated -", - " this is like a nop. */", - }, - - /* sh4a */ - { "", "", "synco", "0000000010101011", - "/* Except for the effect on the pipeline - which is not simulated -", - " this is like a nop. */", - }, - - { "n", "n", "rotcl <REG_N>", "0100nnnn00100100", - "ult = R[n] < 0;", - "R[n] = (R[n] << 1) | T;", - "SET_SR_T (ult);", - }, - - { "n", "n", "rotcr <REG_N>", "0100nnnn00100101", - "ult = R[n] & 1;", - "R[n] = (UR[n] >> 1) | (T << 31);", - "SET_SR_T (ult);", - }, - - { "n", "n", "rotl <REG_N>", "0100nnnn00000100", - "SET_SR_T (R[n] < 0);", - "R[n] <<= 1;", - "R[n] |= T;", - }, - - { "n", "n", "rotr <REG_N>", "0100nnnn00000101", - "SET_SR_T (R[n] & 1);", - "R[n] = UR[n] >> 1;", - "R[n] |= (T << 31);", - }, - - { "", "", "rte", "0000000000101011", -#if 0 - /* SH-[12] */ - "int tmp = PC;", - "SET_NIP (PT2H (RLAT (R[15]) + 2));", - "R[15] += 4;", - "SET_SR (RLAT (R[15]) & 0x3f3);", - "R[15] += 4;", - "Delay_Slot (PC + 2);", -#else - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_SR (SSR);", - "SET_NIP (PT2H (SPC));", - "cycles += 2;", - "Delay_Slot (PC + 2);", -#endif - }, - - { "", "", "rts", "0000000000001011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (PT2H (PR));", - "cycles += 2;", - "Delay_Slot (PC + 2);", - }, - { "", "", "rts/n", "0000000001101011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "SET_NIP (PT2H (PR));", - }, - { "0", "n", "rtv/n <REG_N>", "0000nnnn01111011", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "R0 = R[n];", - "L (0);", - "SET_NIP (PT2H (PR));", - }, - - /* sh4a */ - { "", "", "setdmx", "0000000010011000", - "saved_state.asregs.cregs.named.sr |= SR_MASK_DMX;" - "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;" - }, - - /* sh4a */ - { "", "", "setdmy", "0000000011001000", - "saved_state.asregs.cregs.named.sr |= SR_MASK_DMY;" - "saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;" - }, - - /* sh-dsp */ - { "", "n", "setrc <REG_N>", "0100nnnn00010100", - "SET_RC (R[n]);", - }, - { "", "", "setrc #<imm>", "10000010i8*1....", - /* It would be more realistic to let loop_start point to some static - memory that contains an illegal opcode and then give a bus error when - the loop is eventually encountered, but it seems not only simpler, - but also more debugging-friendly to just catch the failure here. */ - "if (BUSERROR (RS | RE, maskw))", - " RAISE_EXCEPTION (SIGILL);", - "else {", - " SET_RC (i);", - " loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw);", - " CHECK_INSN_PTR (insn_ptr);", - "}", - }, - - { "", "", "sets", "0000000001011000", - "SET_SR_S (1);", - }, - - { "", "", "sett", "0000000000011000", - "SET_SR_T (1);", - }, - - { "n", "mn", "shad <REG_M>,<REG_N>", "0100nnnnmmmm1100", - "R[n] = (R[m] < 0) ? (R[m]&0x1f ? R[n] >> ((-R[m])&0x1f) : R[n] >> 31) : (R[n] << (R[m] & 0x1f));", - }, - - { "n", "n", "shal <REG_N>", "0100nnnn00100000", - "SET_SR_T (R[n] < 0);", - "R[n] <<= 1;", - }, - - { "n", "n", "shar <REG_N>", "0100nnnn00100001", - "SET_SR_T (R[n] & 1);", - "R[n] = R[n] >> 1;", - }, - - { "n", "mn", "shld <REG_M>,<REG_N>", "0100nnnnmmmm1101", - "R[n] = (R[m] < 0) ? (R[m]&0x1f ? UR[n] >> ((-R[m])&0x1f) : 0): (R[n] << (R[m] & 0x1f));", - }, - - { "n", "n", "shll <REG_N>", "0100nnnn00000000", - "SET_SR_T (R[n] < 0);", - "R[n] <<= 1;", - }, - - { "n", "n", "shll2 <REG_N>", "0100nnnn00001000", - "R[n] <<= 2;", - }, - { "n", "n", "shll8 <REG_N>", "0100nnnn00011000", - "R[n] <<= 8;", - }, - { "n", "n", "shll16 <REG_N>", "0100nnnn00101000", - "R[n] <<= 16;", - }, - - { "n", "n", "shlr <REG_N>", "0100nnnn00000001", - "SET_SR_T (R[n] & 1);", - "R[n] = UR[n] >> 1;", - }, - - { "n", "n", "shlr2 <REG_N>", "0100nnnn00001001", - "R[n] = UR[n] >> 2;", - }, - { "n", "n", "shlr8 <REG_N>", "0100nnnn00011001", - "R[n] = UR[n] >> 8;", - }, - { "n", "n", "shlr16 <REG_N>", "0100nnnn00101001", - "R[n] = UR[n] >> 16;", - }, - - { "", "", "sleep", "0000000000011011", - "nip += trap (0xc3, &R0, PC, memory, maskl, maskw, endianw);", - }, - - { "n", "", "stc <CREG_M>,<REG_N>", "0000nnnnmmmm0010", - "R[n] = CREG (m);", - }, - - { "n", "", "stc SGR,<REG_N>", "0000nnnn00111010", - "if (SR_MD)", - " R[n] = SGR; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "", "stc DBR,<REG_N>", "0000nnnn11111010", - "if (SR_MD)", - " R[n] = DBR; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "", "stc TBR,<REG_N>", "0000nnnn01001010", - "if (SR_MD)", /* FIXME? */ - " R[n] = TBR; /* priv mode */", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "n", "stc.l <CREG_M>,@-<REG_N>", "0100nnnnmmmm0011", - "MA (1);", - "R[n] -= 4;", - "WLAT (R[n], CREG (m));", - }, - { "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010", - "if (SR_MD)", - "{ /* priv mode */", - " MA (1);", - " R[n] -= 4;", - " WLAT (R[n], SGR);", - "}", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - { "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010", - "if (SR_MD)", - "{ /* priv mode */", - " MA (1);", - " R[n] -= 4;", - " WLAT (R[n], DBR);", - "}", - "else", - " RAISE_EXCEPTION (SIGILL); /* user mode */", - }, - - { "n", "", "sts <SREG_M>,<REG_N>", "0000nnnnssss1010", - "R[n] = SREG (m);", - }, - { "n", "n", "sts.l <SREG_M>,@-<REG_N>", "0100nnnnssss0010", - "MA (1);", - "R[n] -= 4;", - "WLAT (R[n], SREG (m));", - }, - - { "n", "nm", "sub <REG_M>,<REG_N>", "0011nnnnmmmm1000", - "R[n] -= R[m];", - }, - - { "n", "nm", "subc <REG_M>,<REG_N>", "0011nnnnmmmm1010", - "ult = R[n] - T;", - "SET_SR_T (ult > R[n]);", - "R[n] = ult - R[m];", - "SET_SR_T (T || (R[n] > ult));", - }, - - { "n", "nm", "subv <REG_M>,<REG_N>", "0011nnnnmmmm1011", - "ult = R[n] - R[m];", - "SET_SR_T (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31);", - "R[n] = ult;", - }, - - { "n", "nm", "swap.b <REG_M>,<REG_N>", "0110nnnnmmmm1000", - "R[n] = ((R[m] & 0xffff0000)", - " | ((R[m] << 8) & 0xff00)", - " | ((R[m] >> 8) & 0x00ff));", - }, - { "n", "nm", "swap.w <REG_M>,<REG_N>", "0110nnnnmmmm1001", - "R[n] = (((R[m] << 16) & 0xffff0000)", - " | ((R[m] >> 16) & 0x00ffff));", - }, - - { "", "n", "tas.b @<REG_N>", "0100nnnn00011011", - "MA (1);", - "ult = RBAT (R[n]);", - "SET_SR_T (ult == 0);", - "WBAT (R[n],ult|0x80);", - }, - - { "0", "", "trapa #<imm>", "11000011i8*1....", - "long imm = 0xff & i;", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "if (i < 20 || i == 33 || i == 34 || i == 0xc3)", - " nip += trap (i, &R0, PC, memory, maskl, maskw, endianw);", -#if 0 - "else {", - /* SH-[12] */ - " R[15] -= 4;", - " WLAT (R[15], GET_SR ());", - " R[15] -= 4;", - " WLAT (R[15], PH2T (PC + 2));", -#else - "else if (!SR_BL) {", - " SSR = GET_SR ();", - " SPC = PH2T (PC + 2);", - " SET_SR (GET_SR () | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);", - " /* FIXME: EXPEVT = 0x00000160; */", -#endif - " SET_NIP (PT2H (RLAT (VBR + (imm<<2))));", - "}", - }, - - { "", "mn", "tst <REG_M>,<REG_N>", "0010nnnnmmmm1000", - "SET_SR_T ((R[n] & R[m]) == 0);", - }, - { "", "0", "tst #<imm>,R0", "11001000i8*1....", - "SET_SR_T ((R0 & i) == 0);", - }, - { "", "0", "tst.b #<imm>,@(R0,GBR)", "11001100i8*1....", - "MA (1);", - "SET_SR_T ((RBAT (GBR+R0) & i) == 0);", - }, - - { "", "0", "xor #<imm>,R0", "11001010i8*1....", - "R0 ^= i;", - }, - { "n", "mn", "xor <REG_M>,<REG_N>", "0010nnnnmmmm1010", - "R[n] ^= R[m];", - }, - { "", "0", "xor.b #<imm>,@(R0,GBR)", "11001110i8*1....", - "MA (1);", - "ult = RBAT (GBR+R0);", - "ult ^= i;", - "WBAT (GBR + R0, ult);", - }, - - { "n", "nm", "xtrct <REG_M>,<REG_N>", "0010nnnnmmmm1101", - "R[n] = (((R[n] >> 16) & 0xffff)", - " | ((R[m] << 16) & 0xffff0000));", - }, - -#if 0 - { "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110", - "divl (0, R[n], R[m]);", - }, - { "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101", - "divl (0, R[n], R[m]);", - }, -#endif - - {0, 0}}; - -op movsxy_tab[] = -{ -/* If this is disabled, the simulator speeds up by about 12% on a - 450 MHz PIII - 9% with ACE_FAST. - Maybe we should have separate simulator loops? */ -#if 1 - { "n", "n", "movs.w @-<REG_N>,<DSP_REG_M>", "111101NNMMMM0000", - "MA (1);", - "R[n] -= 2;", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - }, - { "", "n", "movs.w @<REG_N>,<DSP_REG_M>", "111101NNMMMM0100", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - }, - { "n", "n", "movs.w @<REG_N>+,<DSP_REG_M>", "111101NNMMMM1000", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - "R[n] += 2;", - }, - { "n", "n8","movs.w @<REG_N>+REG_8,<DSP_REG_M>", "111101NNMMMM1100", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - "R[n] += R[8];", - }, - { "n", "n", "movs.w @-<REG_N>,<DSP_GRD_M>", "111101NNGGGG0000", - "MA (1);", - "R[n] -= 2;", - "DSP_R (m) = RSWAT (R[n]);", - }, - { "", "n", "movs.w @<REG_N>,<DSP_GRD_M>", "111101NNGGGG0100", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]);", - }, - { "n", "n", "movs.w @<REG_N>+,<DSP_GRD_M>", "111101NNGGGG1000", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]);", - "R[n] += 2;", - }, - { "n", "n8","movs.w @<REG_N>+REG_8,<DSP_GRD_M>", "111101NNGGGG1100", - "MA (1);", - "DSP_R (m) = RSWAT (R[n]);", - "R[n] += R[8];", - }, - { "n", "n", "movs.w <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0001", - "MA (1);", - "R[n] -= 2;", - "WWAT (R[n], DSP_R (m) >> 16);", - }, - { "", "n", "movs.w <DSP_REG_M>,@<REG_N>", "111101NNMMMM0101", - "MA (1);", - "WWAT (R[n], DSP_R (m) >> 16);", - }, - { "n", "n", "movs.w <DSP_REG_M>,@<REG_N>+", "111101NNMMMM1001", - "MA (1);", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += 2;", - }, - { "n", "n8","movs.w <DSP_REG_M>,@<REG_N>+REG_8", "111101NNMMMM1101", - "MA (1);", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += R[8];", - }, - { "n", "n", "movs.w <DSP_GRD_M>,@-<REG_N>", "111101NNGGGG0001", - "MA (1);", - "R[n] -= 2;", - "WWAT (R[n], SEXT (DSP_R (m)));", - }, - { "", "n", "movs.w <DSP_GRD_M>,@<REG_N>", "111101NNGGGG0101", - "MA (1);", - "WWAT (R[n], SEXT (DSP_R (m)));", - }, - { "n", "n", "movs.w <DSP_GRD_M>,@<REG_N>+", "111101NNGGGG1001", - "MA (1);", - "WWAT (R[n], SEXT (DSP_R (m)));", - "R[n] += 2;", - }, - { "n", "n8","movs.w <DSP_GRD_M>,@<REG_N>+REG_8", "111101NNGGGG1101", - "MA (1);", - "WWAT (R[n], SEXT (DSP_R (m)));", - "R[n] += R[8];", - }, - { "n", "n", "movs.l @-<REG_N>,<DSP_REG_M>", "111101NNMMMM0010", - "MA (1);", - "R[n] -= 4;", - "DSP_R (m) = RLAT (R[n]);", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - }, - { "", "n", "movs.l @<REG_N>,<DSP_REG_M>", "111101NNMMMM0110", - "MA (1);", - "DSP_R (m) = RLAT (R[n]);", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - }, - { "n", "n", "movs.l @<REG_N>+,<DSP_REG_M>", "111101NNMMMM1010", - "MA (1);", - "DSP_R (m) = RLAT (R[n]);", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - "R[n] += 4;", - }, - { "n", "n8","movs.l @<REG_N>+REG_8,<DSP_REG_M>", "111101NNMMMM1110", - "MA (1);", - "DSP_R (m) = RLAT (R[n]);", - "DSP_GRD (m) = SIGN32 (DSP_R (m));", - "R[n] += R[8];", - }, - { "n", "n", "movs.l <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0011", - "MA (1);", - "R[n] -= 4;", - "WLAT (R[n], DSP_R (m));", - }, - { "", "n", "movs.l <DSP_REG_M>,@<REG_N>", "111101NNMMMM0111", - "MA (1);", - "WLAT (R[n], DSP_R (m));", - }, - { "n", "n", "movs.l <DSP_REG_M>,@<REG_N>+", "111101NNMMMM1011", - "MA (1);", - "WLAT (R[n], DSP_R (m));", - "R[n] += 4;", - }, - { "n", "n8","movs.l <DSP_REG_M>,@<REG_N>+REG_8", "111101NNMMMM1111", - "MA (1);", - "WLAT (R[n], DSP_R (m));", - "R[n] += R[8];", - }, - { "n", "n", "movs.l <DSP_GRD_M>,@-<REG_N>", "111101NNGGGG0011", - "MA (1);", - "R[n] -= 4;", - "WLAT (R[n], SEXT (DSP_R (m)));", - }, - { "", "n", "movs.l <DSP_GRD_M>,@<REG_N>", "111101NNGGGG0111", - "MA (1);", - "WLAT (R[n], SEXT (DSP_R (m)));", - }, - { "n", "n", "movs.l <DSP_GRD_M>,@<REG_N>+", "111101NNGGGG1011", - "MA (1);", - "WLAT (R[n], SEXT (DSP_R (m)));", - "R[n] += 4;", - }, - { "n", "n8","movs.l <DSP_GRD_M>,@<REG_N>+REG_8", "111101NNGGGG1111", - "MA (1);", - "WLAT (R[n], SEXT (DSP_R (m)));", - "R[n] += R[8];", - }, - { "", "n", "movx.w @<REG_xy>,<DSP_XY>", "111100xyXY0001??", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "", "n", "movx.l @<REG_xy>,<DSP_XY>", "111100xyXY010100", - "DSP_R (m) = RLAT (R[n]);", - }, - { "n", "n", "movx.w @<REG_xy>+,<DSP_XY>", "111100xyXY0010??", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "n", "n", "movx.l @<REG_xy>+,<DSP_XY>", "111100xyXY011000", - "DSP_R (m) = RLAT (R[n]);", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;", - }, - { "n", "n8","movx.w @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY0011??", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "n", "n8","movx.l @<REG_xy>+REG_8,<DSP_XY>", "111100xyXY011100", - "DSP_R (m) = RLAT (R[n]);", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];", - }, - { "", "n", "movx.w <DSP_Ax>,@<REG_xy>", "111100xyax1001??", - "WWAT (R[n], DSP_R (m) >> 16);", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "", "n", "movx.l <DSP_Ax>,@<REG_xy>", "111100xyax110100", - "WLAT (R[n], DSP_R (m));", - }, - { "n", "n", "movx.w <DSP_Ax>,@<REG_xy>+", "111100xyax1010??", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "n", "n", "movx.l <DSP_Ax>,@<REG_xy>+", "111100xyax111000", - "WLAT (R[n], DSP_R (m));", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 4;", - }, - { "n", "n8","movx.w <DSP_Ax>,@<REG_xy>+REG_8","111100xyax1011??", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];", - "if (iword & 3)", - " {", - " iword &= 0xfd53; goto top;", - " }", - }, - { "n", "n8","movx.l <DSP_Ax>,@<REG_xy>+REG_8","111100xyax111100", - "WLAT (R[n], DSP_R (m));", - "R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];", - }, - { "", "n", "movy.w @<REG_yx>,<DSP_YX>", "111100yxYX000001", - "DSP_R (m) = RSWAT (R[n]) << 16;", - }, - { "n", "n", "movy.w @<REG_yx>+,<DSP_YX>", "111100yxYX000010", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;", - }, - { "n", "n9","movy.w @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX000011", - "DSP_R (m) = RSWAT (R[n]) << 16;", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];", - }, - { "", "n", "movy.w <DSP_Ay>,@<REG_yx>", "111100yxAY010001", - "WWAT (R[n], DSP_R (m) >> 16);", - }, - { "n", "n", "movy.w <DSP_Ay>,@<REG_yx>+", "111100yxAY010010", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;", - }, - { "n", "n9", "movy.w <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY010011", - "WWAT (R[n], DSP_R (m) >> 16);", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];", - }, - { "", "n", "movy.l @<REG_yx>,<DSP_YX>", "111100yxYX100001", - "DSP_R (m) = RLAT (R[n]);", - }, - { "n", "n", "movy.l @<REG_yx>+,<DSP_YX>", "111100yxYX100010", - "DSP_R (m) = RLAT (R[n]);", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;", - }, - { "n", "n9","movy.l @<REG_yx>+REG_9,<DSP_YX>", "111100yxYX100011", - "DSP_R (m) = RLAT (R[n]);", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];", - }, - { "", "n", "movy.l <DSP_Ay>,@<REG_yx>", "111100yxAY110001", - "WLAT (R[n], DSP_R (m));", - }, - { "n", "n", "movy.l <DSP_Ay>,@<REG_yx>+", "111100yxAY110010", - "WLAT (R[n], DSP_R (m));", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 4;", - }, - { "n", "n9", "movy.l <DSP_Ay>,@<REG_yx>+REG_9", "111100yxAY110011", - "WLAT (R[n], DSP_R (m));", - "R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];", - }, - { "", "", "nopx nopy", "1111000000000000", - "/* nop */", - }, - { "", "", "ppi", "1111100000000000", - "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", - "ppi_insn (RIAT (nip));", - "SET_NIP (nip + 2);", - "iword &= 0xf7ff; goto top;", - }, -#endif - {0, 0}}; - -op ppi_tab[] = -{ - { "","", "pshl #<imm>,dz", "00000iiim16.zzzz", - "int Sz = DSP_R (z) & 0xffff0000;", - "", - "if (i <= 16)", - " res = Sz << i;", - "else if (i >= 128 - 16)", - " res = (unsigned) Sz >> 128 - i; /* no sign extension */", - "else", - " {", - " RAISE_EXCEPTION (SIGILL);", - " return;", - " }", - "res &= 0xffff0000;", - "res_grd = 0;", - "goto logical;", - }, - { "","", "psha #<imm>,dz", "00010iiim32.zzzz", - "int Sz = DSP_R (z);", - "int Sz_grd = GET_DSP_GRD (z);", - "", - "if (i <= 32)", - " {", - " if (i == 32)", - " {", - " res = 0;", - " res_grd = Sz;", - " }", - " else", - " {", - " res = Sz << i;", - " res_grd = Sz_grd << i | (unsigned) Sz >> 32 - i;", - " }", - " res_grd = SEXT (res_grd);", - " carry = res_grd & 1;", - " }", - "else if (i >= 96)", - " {", - " i = 128 - i;", - " if (i == 32)", - " {", - " res_grd = SIGN32 (Sz_grd);", - " res = Sz_grd;", - " }", - " else", - " {", - " res = Sz >> i | Sz_grd << 32 - i;", - " res_grd = Sz_grd >> i;", - " }", - " carry = Sz >> (i - 1) & 1;", - " }", - "else", - " {", - " RAISE_EXCEPTION (SIGILL);", - " return;", - " }", - "COMPUTE_OVERFLOW;", - "greater_equal = 0;", - }, - { "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu", - "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;", - "if (res == 0x80000000)", - " res = 0x7fffffff;", - "DSP_R (g) = res;", - "DSP_GRD (g) = SIGN32 (res);", - "return;", - }, - { "","", "psub Sx,Sy,Du pmuls Se,Sf,Dg", "0110eeffxxyygguu", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;", - "if (res == 0x80000000)", - " res = 0x7fffffff;", - "DSP_R (g) = res;", - "DSP_GRD (g) = SIGN32 (res);", - "", - "z = u;", - "res = Sx - Sy;", - "carry = (unsigned) res > (unsigned) Sx;", - "res_grd = Sx_grd - Sy_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "padd Sx,Sy,Du pmuls Se,Sf,Dg", "0111eeffxxyygguu", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;", - "if (res == 0x80000000)", - " res = 0x7fffffff;", - "DSP_R (g) = res;", - "DSP_GRD (g) = SIGN32 (res);", - "", - "z = u;", - "res = Sx + Sy;", - "carry = (unsigned) res < (unsigned) Sx;", - "res_grd = Sx_grd + Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - }, - { "","", "psubc Sx,Sy,Dz", "10100000xxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sx - Sy - (DSR & 1);", - "carry = (unsigned) res > (unsigned) Sx || (res == Sx && Sy);", - "res_grd = Sx_grd + Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "DSR &= ~0xf1;\n", - "if (res || res_grd)\n", - " DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n", - "else\n", - " DSR |= DSR_MASK_Z | overflow;\n", - "DSR |= carry;\n", - "goto assign_z;\n", - }, - { "","", "paddc Sx,Sy,Dz", "10110000xxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sx + Sy + (DSR & 1);", - "carry = (unsigned) res < (unsigned) Sx || (res == Sx && Sy);", - "res_grd = Sx_grd + Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "DSR &= ~0xf1;\n", - "if (res || res_grd)\n", - " DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n", - "else\n", - " DSR |= DSR_MASK_Z | overflow;\n", - "DSR |= carry;\n", - "goto assign_z;\n", - }, - { "","", "pcmp Sx,Sy", "10000100xxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "z = 17; /* Ignore result. */", - "res = Sx - Sy;", - "carry = (unsigned) res > (unsigned) Sx;", - "res_grd = Sx_grd - Sy_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "pwsb Sx,Sy,Dz", "10100100xxyyzzzz", - }, - { "","", "pwad Sx,Sy,Dz", "10110100xxyyzzzz", - }, - { "","", "(if cc) pabs Sx,Dz", "100010ccxx01zzzz", - "/* FIXME: duplicate code pabs. */", - "res = DSP_R (x);", - "res_grd = GET_DSP_GRD (x);", - "if (res >= 0)", - " carry = 0;", - "else", - " {", - " res = -res;", - " carry = (res != 0); /* The manual has a bug here. */", - " res_grd = -res_grd - carry;", - " }", - "COMPUTE_OVERFLOW;", - "/* ??? The re-computing of overflow after", - " saturation processing is specific to pabs. */", - "overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;", - "ADD_SUB_GE;", - }, - { "","", "pabs Sx,Dz", "10001000xx..zzzz", - "res = DSP_R (x);", - "res_grd = GET_DSP_GRD (x);", - "if (res >= 0)", - " carry = 0;", - "else", - " {", - " res = -res;", - " carry = (res != 0); /* The manual has a bug here. */", - " res_grd = -res_grd - carry;", - " }", - "COMPUTE_OVERFLOW;", - "/* ??? The re-computing of overflow after", - " saturation processing is specific to pabs. */", - "overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0;", - "ADD_SUB_GE;", - }, - - { "","", "(if cc) prnd Sx,Dz", "100110ccxx01zzzz", - "/* FIXME: duplicate code prnd. */", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "", - "res = (Sx + 0x8000) & 0xffff0000;", - "carry = (unsigned) res < (unsigned) Sx;", - "res_grd = Sx_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "prnd Sx,Dz", "10011000xx..zzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "", - "res = (Sx + 0x8000) & 0xffff0000;", - "carry = (unsigned) res < (unsigned) Sx;", - "res_grd = Sx_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - - { "","", "(if cc) pabs Sy,Dz", "101010cc01yyzzzz", - "/* FIXME: duplicate code pabs. */", - "res = DSP_R (y);", - "res_grd = 0;", - "overflow = 0;", - "greater_equal = DSR_MASK_G;", - "if (res >= 0)", - " carry = 0;", - "else", - " {", - " res = -res;", - " carry = 1;", - " if (res < 0)", - " {", - " if (S)", - " res = 0x7fffffff;", - " else", - " {", - " overflow = DSR_MASK_V;", - " greater_equal = 0;", - " }", - " }", - " }", - }, - { "","", "pabs Sy,Dz", "10101000..yyzzzz", - "res = DSP_R (y);", - "res_grd = 0;", - "overflow = 0;", - "greater_equal = DSR_MASK_G;", - "if (res >= 0)", - " carry = 0;", - "else", - " {", - " res = -res;", - " carry = 1;", - " if (res < 0)", - " {", - " if (S)", - " res = 0x7fffffff;", - " else", - " {", - " overflow = DSR_MASK_V;", - " greater_equal = 0;", - " }", - " }", - " }", - }, - { "","", "(if cc) prnd Sy,Dz", "101110cc01yyzzzz", - "/* FIXME: duplicate code prnd. */", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = (Sy + 0x8000) & 0xffff0000;", - "carry = (unsigned) res < (unsigned) Sy;", - "res_grd = Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "prnd Sy,Dz", "10111000..yyzzzz", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = (Sy + 0x8000) & 0xffff0000;", - "carry = (unsigned) res < (unsigned) Sy;", - "res_grd = Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pshl Sx,Sy,Dz", "100000ccxxyyzzzz", - "int Sx = DSP_R (x) & 0xffff0000;", - "int Sy = DSP_R (y) >> 16 & 0x7f;", - "", - "if (Sy <= 16)", - " res = Sx << Sy;", - "else if (Sy >= 128 - 16)", - " res = (unsigned) Sx >> 128 - Sy; /* no sign extension */", - "else", - " {", - " RAISE_EXCEPTION (SIGILL);", - " return;", - " }", - "goto cond_logical;", - }, - { "","", "(if cc) psha Sx,Sy,Dz", "100100ccxxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y) >> 16 & 0x7f;", - "", - "if (Sy <= 32)", - " {", - " if (Sy == 32)", - " {", - " res = 0;", - " res_grd = Sx;", - " }", - " else", - " {", - " res = Sx << Sy;", - " res_grd = Sx_grd << Sy | (unsigned) Sx >> 32 - Sy;", - " }", - " res_grd = SEXT (res_grd);", - " carry = res_grd & 1;", - " }", - "else if (Sy >= 96)", - " {", - " Sy = 128 - Sy;", - " if (Sy == 32)", - " {", - " res_grd = SIGN32 (Sx_grd);", - " res = Sx_grd;", - " }", - " else", - " {", - " res = Sx >> Sy | Sx_grd << 32 - Sy;", - " res_grd = Sx_grd >> Sy;", - " }", - " carry = Sx >> (Sy - 1) & 1;", - " }", - "else", - " {", - " RAISE_EXCEPTION (SIGILL);", - " return;", - " }", - "COMPUTE_OVERFLOW;", - "greater_equal = 0;", - }, - { "","", "(if cc) psub Sx,Sy,Dz", "101000ccxxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sx - Sy;", - "carry = (unsigned) res > (unsigned) Sx;", - "res_grd = Sx_grd - Sy_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) psub Sy,Sx,Dz", "100001ccxxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sy - Sx;", - "carry = (unsigned) res > (unsigned) Sy;", - "res_grd = Sy_grd - Sx_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) padd Sx,Sy,Dz", "101100ccxxyyzzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sx + Sy;", - "carry = (unsigned) res < (unsigned) Sx;", - "res_grd = Sx_grd + Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pand Sx,Sy,Dz", "100101ccxxyyzzzz", - "res = DSP_R (x) & DSP_R (y);", - "cond_logical:", - "res &= 0xffff0000;", - "res_grd = 0;", - "if (iword & 0x200)\n", - " goto assign_z;\n", - "logical:", - "carry = 0;", - "overflow = 0;", - "greater_equal = 0;", - "DSR &= ~0xf1;\n", - "if (res)\n", - " DSR |= res >> 26 & DSR_MASK_N;\n", - "else\n", - " DSR |= DSR_MASK_Z;\n", - "goto assign_dc;\n", - }, - { "","", "(if cc) pxor Sx,Sy,Dz", "101001ccxxyyzzzz", - "res = DSP_R (x) ^ DSP_R (y);", - "goto cond_logical;", - }, - { "","", "(if cc) por Sx,Sy,Dz", "101101ccxxyyzzzz", - "res = DSP_R (x) | DSP_R (y);", - "goto cond_logical;", - }, - { "","", "(if cc) pdec Sx,Dz", "100010ccxx..zzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "", - "res = Sx - 0x10000;", - "carry = res > Sx;", - "res_grd = Sx_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "res &= 0xffff0000;", - }, - { "","", "(if cc) pinc Sx,Dz", "100110ccxx..zzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "", - "res = Sx + 0x10000;", - "carry = res < Sx;", - "res_grd = Sx_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "res &= 0xffff0000;", - }, - { "","", "(if cc) pdec Sy,Dz", "101010cc..yyzzzz", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sy - 0x10000;", - "carry = res > Sy;", - "res_grd = Sy_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "res &= 0xffff0000;", - }, - { "","", "(if cc) pinc Sy,Dz", "101110cc..yyzzzz", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = Sy + 0x10000;", - "carry = res < Sy;", - "res_grd = Sy_grd + carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - "res &= 0xffff0000;", - }, - { "","", "(if cc) pclr Dz", "100011cc....zzzz", - "res = 0;", - "res_grd = 0;", - "carry = 0;", - "overflow = 0;", - "greater_equal = 1;", - }, - { "","", "pclr Du pmuls Se,Sf,Dg", "0100eeff0001gguu", - "/* Do multiply. */", - "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;", - "if (res == 0x80000000)", - " res = 0x7fffffff;", - "DSP_R (g) = res;", - "DSP_GRD (g) = SIGN32 (res);", - "/* FIXME: update DSR based on results of multiply! */", - "", - "/* Do clr. */", - "z = u;", - "res = 0;", - "res_grd = 0;", - "goto assign_z;", - }, - { "","", "(if cc) pdmsb Sx,Dz", "100111ccxx..zzzz", - "unsigned Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "int i = 16;", - "", - "if (Sx_grd < 0)", - " {", - " Sx_grd = ~Sx_grd;", - " Sx = ~Sx;", - " }", - "if (Sx_grd)", - " {", - " Sx = Sx_grd;", - " res = -2;", - " }", - "else if (Sx)", - " res = 30;", - "else", - " res = 31;", - "do", - " {", - " if (Sx & ~0 << i)", - " {", - " res -= i;", - " Sx >>= i;", - " }", - " }", - "while (i >>= 1);", - "res <<= 16;", - "res_grd = SIGN32 (res);", - "carry = 0;", - "overflow = 0;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pdmsb Sy,Dz", "101111cc..yyzzzz", - "unsigned Sy = DSP_R (y);", - "int i;", - "", - "if (Sy < 0)", - " Sy = ~Sy;", - "Sy <<= 1;", - "res = 31;", - "do", - " {", - " if (Sy & ~0 << i)", - " {", - " res -= i;", - " Sy >>= i;", - " }", - " }", - "while (i >>= 1);", - "res <<= 16;", - "res_grd = SIGN32 (res);", - "carry = 0;", - "overflow = 0;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pneg Sx,Dz", "110010ccxx..zzzz", - "int Sx = DSP_R (x);", - "int Sx_grd = GET_DSP_GRD (x);", - "", - "res = 0 - Sx;", - "carry = res != 0;", - "res_grd = 0 - Sx_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pcopy Sx,Dz", "110110ccxx..zzzz", - "res = DSP_R (x);", - "res_grd = GET_DSP_GRD (x);", - "carry = 0;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pneg Sy,Dz", "111010cc..yyzzzz", - "int Sy = DSP_R (y);", - "int Sy_grd = SIGN32 (Sy);", - "", - "res = 0 - Sy;", - "carry = res != 0;", - "res_grd = 0 - Sy_grd - carry;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) pcopy Sy,Dz", "111110cc..yyzzzz", - "res = DSP_R (y);", - "res_grd = SIGN32 (res);", - "carry = 0;", - "COMPUTE_OVERFLOW;", - "ADD_SUB_GE;", - }, - { "","", "(if cc) psts MACH,Dz", "110011cc....zzzz", - "res = MACH;", - "res_grd = SIGN32 (res);", - "goto assign_z;", - }, - { "","", "(if cc) psts MACL,Dz", "110111cc....zzzz", - "res = MACL;", - "res_grd = SIGN32 (res);", - "goto assign_z;", - }, - { "","", "(if cc) plds Dz,MACH", "111011cc....zzzz", - "if (0xa05f >> z & 1)", - " RAISE_EXCEPTION (SIGILL);", - "else", - " MACH = DSP_R (z);", - "return;", - }, - { "","", "(if cc) plds Dz,MACL", "111111cc....zzzz", - "if (0xa05f >> z & 1)", - " RAISE_EXCEPTION (SIGILL);", - "else", - " MACL = DSP_R (z) = res;", - "return;", - }, - /* sh4a */ - { "","", "(if cc) pswap Sx,Dz", "100111ccxx01zzzz", - "int Sx = DSP_R (x);", - "", - "res = ((Sx & 0xffff) * 65536) + ((Sx >> 16) & 0xffff);", - "res_grd = GET_DSP_GRD (x);", - "carry = 0;", - "overflow = 0;", - "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;", - }, - /* sh4a */ - { "","", "(if cc) pswap Sy,Dz", "101111cc01yyzzzz", - "int Sy = DSP_R (y);", - "", - "res = ((Sy & 0xffff) * 65536) + ((Sy >> 16) & 0xffff);", - "res_grd = SIGN32 (Sy);", - "carry = 0;", - "overflow = 0;", - "greater_equal = res & 0x80000000 ? 0 : DSR_MASK_G;", - }, - - {0, 0} -}; - -/* Tables of things to put into enums for sh-opc.h */ -static char *nibble_type_list[] = -{ - "HEX_0", - "HEX_1", - "HEX_2", - "HEX_3", - "HEX_4", - "HEX_5", - "HEX_6", - "HEX_7", - "HEX_8", - "HEX_9", - "HEX_A", - "HEX_B", - "HEX_C", - "HEX_D", - "HEX_E", - "HEX_F", - "REG_N", - "REG_M", - "BRANCH_12", - "BRANCH_8", - "DISP_8", - "DISP_4", - "IMM_4", - "IMM_4BY2", - "IMM_4BY4", - "PCRELIMM_8BY2", - "PCRELIMM_8BY4", - "IMM_8", - "IMM_8BY2", - "IMM_8BY4", - 0 -}; -static -char *arg_type_list[] = -{ - "A_END", - "A_BDISP12", - "A_BDISP8", - "A_DEC_M", - "A_DEC_N", - "A_DISP_GBR", - "A_DISP_PC", - "A_DISP_REG_M", - "A_DISP_REG_N", - "A_GBR", - "A_IMM", - "A_INC_M", - "A_INC_N", - "A_IND_M", - "A_IND_N", - "A_IND_R0_REG_M", - "A_IND_R0_REG_N", - "A_MACH", - "A_MACL", - "A_PR", - "A_R0", - "A_R0_GBR", - "A_REG_M", - "A_REG_N", - "A_SR", - "A_VBR", - "A_SSR", - "A_SPC", - 0, -}; - -static void -make_enum_list (name, s) - char *name; - char **s; -{ - int i = 1; - printf ("typedef enum {\n"); - while (*s) - { - printf ("\t%s,\n", *s); - s++; - i++; - } - printf ("} %s;\n", name); -} - -static int -qfunc (a, b) - op *a; - op *b; -{ - char bufa[9]; - char bufb[9]; - int diff; - - memcpy (bufa, a->code, 4); - memcpy (bufa + 4, a->code + 12, 4); - bufa[8] = 0; - - memcpy (bufb, b->code, 4); - memcpy (bufb + 4, b->code + 12, 4); - bufb[8] = 0; - diff = strcmp (bufa, bufb); - /* Stabilize the sort, so that later entries can override more general - preceding entries. */ - return diff ? diff : a - b; -} - -static void -sorttab () -{ - op *p = tab; - int len = 0; - - while (p->name) - { - p++; - len++; - } - qsort (tab, len, sizeof (*p), qfunc); -} - -static void -gengastab () -{ - op *p; - sorttab (); - for (p = tab; p->name; p++) - { - printf ("%s %-30s\n", p->code, p->name); - } -} - -static unsigned short table[1 << 16]; - -static int warn_conflicts = 0; - -static void -conflict_warn (val, i) - int val; - int i; -{ - int ix, key; - int j = table[val]; - - fprintf (stderr, "Warning: opcode table conflict: 0x%04x (idx %d && %d)\n", - val, i, table[val]); - - for (ix = sizeof (tab) / sizeof (tab[0]); ix >= 0; ix--) - if (tab[ix].index == i || tab[ix].index == j) - { - key = ((tab[ix].code[0] - '0') << 3) + - ((tab[ix].code[1] - '0') << 2) + - ((tab[ix].code[2] - '0') << 1) + - ((tab[ix].code[3] - '0')); - - if (val >> 12 == key) - fprintf (stderr, " %s -- %s\n", tab[ix].code, tab[ix].name); - } - - for (ix = sizeof (movsxy_tab) / sizeof (movsxy_tab[0]); ix >= 0; ix--) - if (movsxy_tab[ix].index == i || movsxy_tab[ix].index == j) - { - key = ((movsxy_tab[ix].code[0] - '0') << 3) + - ((movsxy_tab[ix].code[1] - '0') << 2) + - ((movsxy_tab[ix].code[2] - '0') << 1) + - ((movsxy_tab[ix].code[3] - '0')); - - if (val >> 12 == key) - fprintf (stderr, " %s -- %s\n", - movsxy_tab[ix].code, movsxy_tab[ix].name); - } - - for (ix = sizeof (ppi_tab) / sizeof (ppi_tab[0]); ix >= 0; ix--) - if (ppi_tab[ix].index == i || ppi_tab[ix].index == j) - { - key = ((ppi_tab[ix].code[0] - '0') << 3) + - ((ppi_tab[ix].code[1] - '0') << 2) + - ((ppi_tab[ix].code[2] - '0') << 1) + - ((ppi_tab[ix].code[3] - '0')); - - if (val >> 12 == key) - fprintf (stderr, " %s -- %s\n", - ppi_tab[ix].code, ppi_tab[ix].name); - } -} - -/* Take an opcode, expand all varying fields in it out and fill all the - right entries in 'table' with the opcode index. */ - -static void -expand_opcode (val, i, s) - int val; - int i; - char *s; -{ - if (*s == 0) - { - if (warn_conflicts && table[val] != 0) - conflict_warn (val, i); - table[val] = i; - } - else - { - int j = 0, m = 0; - - switch (s[0]) - { - default: - fprintf (stderr, "expand_opcode: illegal char '%c'\n", s[0]); - exit (1); - case '0': - case '1': - /* Consume an arbitrary number of ones and zeros. */ - do { - j = (j << 1) + (s[m++] - '0'); - } while (s[m] == '0' || s[m] == '1'); - expand_opcode ((val << m) | j, i, s + m); - break; - case 'N': /* NN -- four-way fork */ - for (j = 0; j < 4; j++) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'x': /* xx or xy -- two-way or four-way fork */ - for (j = 0; j < 4; j += (s[1] == 'x' ? 2 : 1)) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'y': /* yy or yx -- two-way or four-way fork */ - for (j = 0; j < (s[1] == 'x' ? 4 : 2); j++) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case '?': /* Seven-way "wildcard" fork for movxy */ - expand_opcode ((val << 2), i, s + 2); - for (j = 1; j < 4; j++) - { - expand_opcode ((val << 2) | j, i, s + 2); - expand_opcode ((val << 2) | (j + 16), i, s + 2); - } - break; - case 'i': /* eg. "i8*1" */ - case '.': /* "...." is a wildcard */ - case 'n': - case 'm': - /* nnnn, mmmm, i#*#, .... -- 16-way fork. */ - for (j = 0; j < 16; j++) - expand_opcode ((val << 4) | j, i, s + 4); - break; - case 'e': - /* eeee -- even numbered register: - 8 way fork. */ - for (j = 0; j < 15; j += 2) - expand_opcode ((val << 4) | j, i, s + 4); - break; - case 'M': - /* A0, A1, X0, X1, Y0, Y1, M0, M1, A0G, A1G: - MMMM -- 10-way fork */ - expand_opcode ((val << 4) | 5, i, s + 4); - for (j = 7; j < 16; j++) - expand_opcode ((val << 4) | j, i, s + 4); - break; - case 'G': - /* A1G, A0G: - GGGG -- two-way fork */ - for (j = 13; j <= 15; j +=2) - expand_opcode ((val << 4) | j, i, s + 4); - break; - case 's': - /* ssss -- 10-way fork */ - /* System registers mach, macl, pr: */ - for (j = 0; j < 3; j++) - expand_opcode ((val << 4) | j, i, s + 4); - /* System registers fpul, fpscr/dsr, a0, x0, x1, y0, y1: */ - for (j = 5; j < 12; j++) - expand_opcode ((val << 4) | j, i, s + 4); - break; - case 'X': - /* XX/XY -- 2/4 way fork. */ - for (j = 0; j < 4; j += (s[1] == 'X' ? 2 : 1)) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'a': - /* aa/ax -- 2/4 way fork. */ - for (j = 0; j < 4; j += (s[1] == 'a' ? 2 : 1)) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'Y': - /* YY/YX -- 2/4 way fork. */ - for (j = 0; j < (s[1] == 'Y' ? 2 : 4); j += 1) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'A': - /* AA/AY: 2/4 way fork. */ - for (j = 0; j < (s[1] == 'A' ? 2 : 4); j += 1) - expand_opcode ((val << 2) | j, i, s + 2); - break; - case 'v': - /* vv(VV) -- 4(16) way fork. */ - /* Vector register fv0/4/8/12. */ - if (s[2] == 'V') - { - /* 2 vector registers. */ - for (j = 0; j < 15; j++) - expand_opcode ((val << 4) | j, i, s + 4); - } - else - { - /* 1 vector register. */ - for (j = 0; j < 4; j += 1) - expand_opcode ((val << 2) | j, i, s + 2); - } - break; - } - } -} - -/* Print the jump table used to index an opcode into a switch - statement entry. */ - -static void -dumptable (name, size, start) - char *name; - int size; - int start; -{ - int lump = 256; - int online = 16; - - int i = start; - - printf ("unsigned short %s[%d]={\n", name, size); - while (i < start + size) - { - int j = 0; - - printf ("/* 0x%x */\n", i); - - while (j < lump) - { - int k = 0; - while (k < online) - { - printf ("%2d", table[i + j + k]); - if (j + k < lump) - printf (","); - - k++; - } - j += k; - printf ("\n"); - } - i += j; - } - printf ("};\n"); -} - - -static void -filltable (p) - op *p; -{ - static int index = 1; - - sorttab (); - for (; p->name; p++) - { - p->index = index++; - expand_opcode (0, p->index, p->code); - } -} - -/* Table already contains all the switch case tags for 16-bit opcode double - data transfer (ddt) insns, and the switch case tag for processing parallel - processing insns (ppi) for code 0xf800 (ppi nopx nopy). Copy the - latter tag to represent all combinations of ppi with ddt. */ -static void -expand_ppi_movxy () -{ - int i; - - for (i = 0xf000; i < 0xf400; i++) - if (table[i]) - table[i + 0x800] = table[0xf800]; -} - -static void -gensim_caselist (p) - op *p; -{ - for (; p->name; p++) - { - int j; - int sextbit = -1; - int needm = 0; - int needn = 0; - - char *s = p->code; - - printf (" /* %s %s */\n", p->name, p->code); - printf (" case %d: \n", p->index); - - printf (" {\n"); - while (*s) - { - switch (*s) - { - default: - fprintf (stderr, "gencode/gensim_caselist: illegal char '%c'\n", - *s); - exit (1); - break; - case '?': - /* Wildcard expansion, nothing to do here. */ - s += 2; - break; - case 'v': - printf (" int v1 = ((iword >> 10) & 3) * 4;\n"); - s += 2; - break; - case 'V': - printf (" int v2 = ((iword >> 8) & 3) * 4;\n"); - s += 2; - break; - case '0': - case '1': - s += 2; - break; - case '.': - s += 4; - break; - case 'n': - case 'e': - printf (" int n = (iword >> 8) & 0xf;\n"); - needn = 1; - s += 4; - break; - case 'N': - printf (" int n = (((iword >> 8) - 2) & 0x3) + 2;\n"); - s += 2; - break; - case 'x': - if (s[1] == 'y') /* xy */ - { - printf (" int n = (iword & 3) ? \n"); - printf (" ((iword >> 9) & 1) + 4 : \n"); - printf (" REG_xy ((iword >> 8) & 3);\n"); - } - else - printf (" int n = ((iword >> 9) & 1) + 4;\n"); - needn = 1; - s += 2; - break; - case 'y': - if (s[1] == 'x') /* yx */ - { - printf (" int n = (iword & 0xc) ? \n"); - printf (" ((iword >> 8) & 1) + 6 : \n"); - printf (" REG_yx ((iword >> 8) & 3);\n"); - } - else - printf (" int n = ((iword >> 8) & 1) + 6;\n"); - needn = 1; - s += 2; - break; - case 'm': - needm = 1; - case 's': - case 'M': - case 'G': - printf (" int m = (iword >> 4) & 0xf;\n"); - s += 4; - break; - case 'X': - if (s[1] == 'Y') /* XY */ - { - printf (" int m = (iword & 3) ? \n"); - printf (" ((iword >> 7) & 1) + 8 : \n"); - printf (" DSP_xy ((iword >> 6) & 3);\n"); - } - else - printf (" int m = ((iword >> 7) & 1) + 8;\n"); - s += 2; - break; - case 'a': - if (s[1] == 'x') /* ax */ - { - printf (" int m = (iword & 3) ? \n"); - printf (" 7 - ((iword >> 6) & 2) : \n"); - printf (" DSP_ax ((iword >> 6) & 3);\n"); - } - else - printf (" int m = 7 - ((iword >> 6) & 2);\n"); - s += 2; - break; - case 'Y': - if (s[1] == 'X') /* YX */ - { - printf (" int m = (iword & 0xc) ? \n"); - printf (" ((iword >> 6) & 1) + 10 : \n"); - printf (" DSP_yx ((iword >> 6) & 3);\n"); - } - else - printf (" int m = ((iword >> 6) & 1) + 10;\n"); - s += 2; - break; - case 'A': - if (s[1] == 'Y') /* AY */ - { - printf (" int m = (iword & 0xc) ? \n"); - printf (" 7 - ((iword >> 5) & 2) : \n"); - printf (" DSP_ay ((iword >> 6) & 3);\n"); - } - else - printf (" int m = 7 - ((iword >> 5) & 2);\n"); - s += 2; - break; - - case 'i': - printf (" int i = (iword & 0x"); - - switch (s[1]) - { - default: - fprintf (stderr, - "gensim_caselist: Unknown char '%c' in %s\n", - s[1], s); - exit (1); - break; - case '4': - printf ("f"); - break; - case '8': - printf ("ff"); - break; - case '1': - sextbit = 12; - printf ("fff"); - break; - } - printf (")"); - - switch (s[3]) - { - default: - fprintf (stderr, - "gensim_caselist: Unknown char '%c' in %s\n", - s[3], s); - exit (1); - break; - case '.': /* eg. "i12." */ - break; - case '1': - break; - case '2': - printf (" << 1"); - break; - case '4': - printf (" << 2"); - break; - } - printf (";\n"); - s += 4; - } - } - if (sextbit > 0) - { - printf (" i = (i ^ (1 << %d)) - (1 << %d);\n", - sextbit - 1, sextbit - 1); - } - - if (needm && needn) - printf (" TB (m,n);\n"); - else if (needm) - printf (" TL (m);\n"); - else if (needn) - printf (" TL (n);\n"); - - { - /* Do the refs. */ - char *r; - for (r = p->refs; *r; r++) - { - if (*r == 'f') printf (" CREF (15);\n"); - if (*r == '-') - { - printf (" {\n"); - printf (" int i = n;\n"); - printf (" do {\n"); - printf (" CREF (i);\n"); - printf (" } while (i-- > 0);\n"); - printf (" }\n"); - } - if (*r == '+') - { - printf (" {\n"); - printf (" int i = n;\n"); - printf (" do {\n"); - printf (" CREF (i);\n"); - printf (" } while (i++ < 14);\n"); - printf (" }\n"); - } - if (*r == '0') printf (" CREF (0);\n"); - if (*r == '8') printf (" CREF (8);\n"); - if (*r == '9') printf (" CREF (9);\n"); - if (*r == 'n') printf (" CREF (n);\n"); - if (*r == 'm') printf (" CREF (m);\n"); - } - } - - printf (" {\n"); - for (j = 0; j < MAX_NR_STUFF; j++) - { - if (p->stuff[j]) - { - printf (" %s\n", p->stuff[j]); - } - } - printf (" }\n"); - - { - /* Do the defs. */ - char *r; - for (r = p->defs; *r; r++) - { - if (*r == 'f') printf (" CDEF (15);\n"); - if (*r == '-') - { - printf (" {\n"); - printf (" int i = n;\n"); - printf (" do {\n"); - printf (" CDEF (i);\n"); - printf (" } while (i-- > 0);\n"); - printf (" }\n"); - } - if (*r == '+') - { - printf (" {\n"); - printf (" int i = n;\n"); - printf (" do {\n"); - printf (" CDEF (i);\n"); - printf (" } while (i++ < 14);\n"); - printf (" }\n"); - } - if (*r == '0') printf (" CDEF (0);\n"); - if (*r == 'n') printf (" CDEF (n);\n"); - if (*r == 'm') printf (" CDEF (m);\n"); - } - } - - printf (" break;\n"); - printf (" }\n"); - } -} - -static void -gensim () -{ - printf ("{\n"); - printf ("/* REG_xy = [r4, r5, r0, r1]. */\n"); - printf ("#define REG_xy(R) ((R)==0 ? 4 : (R)==2 ? 5 : (R)==1 ? 0 : 1)\n"); - printf ("/* REG_yx = [r6, r7, r2, r3]. */\n"); - printf ("#define REG_yx(R) ((R)==0 ? 6 : (R)==1 ? 7 : (R)==2 ? 2 : 3)\n"); - printf ("/* DSP_ax = [a0, a1, x0, x1]. */\n"); - printf ("#define DSP_ax(R) ((R)==0 ? 7 : (R)==2 ? 5 : (R)==1 ? 8 : 9)\n"); - printf ("/* DSP_ay = [a0, a1, y0, y1]. */\n"); - printf ("#define DSP_ay(R) ((R)==0 ? 7 : (R)==1 ? 5 : (R)==2 ? 10 : 11)\n"); - printf ("/* DSP_xy = [x0, x1, y0, y1]. */\n"); - printf ("#define DSP_xy(R) ((R)==0 ? 8 : (R)==2 ? 9 : (R)==1 ? 10 : 11)\n"); - printf ("/* DSP_yx = [y0, y1, x0, x1]. */\n"); - printf ("#define DSP_yx(R) ((R)==0 ? 10 : (R)==1 ? 11 : (R)==2 ? 8 : 9)\n"); - printf (" switch (jump_table[iword]) {\n"); - - gensim_caselist (tab); - gensim_caselist (movsxy_tab); - - printf (" default:\n"); - printf (" {\n"); - printf (" RAISE_EXCEPTION (SIGILL);\n"); - printf (" }\n"); - printf (" }\n"); - printf ("}\n"); -} - -static void -gendefines () -{ - op *p; - filltable (tab); - for (p = tab; p->name; p++) - { - char *s = p->name; - printf ("#define OPC_"); - while (*s) { - if (isupper (*s)) - *s = tolower (*s); - if (isalpha (*s)) - printf ("%c", *s); - if (*s == ' ') - printf ("_"); - if (*s == '@') - printf ("ind_"); - if (*s == ',') - printf ("_"); - s++; - } - printf (" %d\n",p->index); - } -} - -static int ppi_index; - -/* Take a ppi code, expand all varying fields in it and fill all the - right entries in 'table' with the opcode index. - NOTE: tail recursion optimization removed for simplicity. */ - -static void -expand_ppi_code (val, i, s) - int val; - int i; - char *s; -{ - int j; - - switch (s[0]) - { - default: - fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n", s[0]); - exit (2); - break; - case 'g': - case 'z': - if (warn_conflicts && table[val] != 0) - conflict_warn (val, i); - - /* The last four bits are disregarded for the switch table. */ - table[val] = i; - return; - case 'm': - /* Four-bit expansion. */ - for (j = 0; j < 16; j++) - expand_ppi_code ((val << 4) + j, i, s + 4); - break; - case '.': - case '0': - expand_ppi_code ((val << 1), i, s + 1); - break; - case '1': - expand_ppi_code ((val << 1) + 1, i, s + 1); - break; - case 'i': - case 'e': case 'f': - case 'x': case 'y': - expand_ppi_code ((val << 1), i, s + 1); - expand_ppi_code ((val << 1) + 1, i, s + 1); - break; - case 'c': - expand_ppi_code ((val << 2) + 1, ppi_index++, s + 2); - expand_ppi_code ((val << 2) + 2, i, s + 2); - expand_ppi_code ((val << 2) + 3, i, s + 2); - break; - } -} - -static void -ppi_filltable () -{ - op *p; - ppi_index = 1; - - for (p = ppi_tab; p->name; p++) - { - p->index = ppi_index++; - expand_ppi_code (0, p->index, p->code); - } -} - -static void -ppi_gensim () -{ - op *p = ppi_tab; - - printf ("#define DSR_MASK_G 0x80\n"); - printf ("#define DSR_MASK_Z 0x40\n"); - printf ("#define DSR_MASK_N 0x20\n"); - printf ("#define DSR_MASK_V 0x10\n"); - printf ("\n"); - printf ("#define COMPUTE_OVERFLOW do {\\\n"); - printf (" overflow = res_grd != SIGN32 (res) ? DSR_MASK_V : 0; \\\n"); - printf (" if (overflow && S) \\\n"); - printf (" { \\\n"); - printf (" if (res_grd & 0x80) \\\n"); - printf (" { \\\n"); - printf (" res = 0x80000000; \\\n"); - printf (" res_grd |= 0xff; \\\n"); - printf (" } \\\n"); - printf (" else \\\n"); - printf (" { \\\n"); - printf (" res = 0x7fffffff; \\\n"); - printf (" res_grd &= ~0xff; \\\n"); - printf (" } \\\n"); - printf (" overflow = 0; \\\n"); - printf (" } \\\n"); - printf ("} while (0)\n"); - printf ("\n"); - printf ("#define ADD_SUB_GE \\\n"); - printf (" (greater_equal = ~(overflow << 3 & res_grd) & DSR_MASK_G)\n"); - printf ("\n"); - printf ("static void\n"); - printf ("ppi_insn (iword)\n"); - printf (" int iword;\n"); - printf ("{\n"); - printf (" /* 'ee' = [x0, x1, y0, a1] */\n"); - printf (" static char e_tab[] = { 8, 9, 10, 5};\n"); - printf (" /* 'ff' = [y0, y1, x0, a1] */\n"); - printf (" static char f_tab[] = {10, 11, 8, 5};\n"); - printf (" /* 'xx' = [x0, x1, a0, a1] */\n"); - printf (" static char x_tab[] = { 8, 9, 7, 5};\n"); - printf (" /* 'yy' = [y0, y1, m0, m1] */\n"); - printf (" static char y_tab[] = {10, 11, 12, 14};\n"); - printf (" /* 'gg' = [m0, m1, a0, a1] */\n"); - printf (" static char g_tab[] = {12, 14, 7, 5};\n"); - printf (" /* 'uu' = [x0, y0, a0, a1] */\n"); - printf (" static char u_tab[] = { 8, 10, 7, 5};\n"); - printf ("\n"); - printf (" int z;\n"); - printf (" int res, res_grd;\n"); - printf (" int carry, overflow, greater_equal;\n"); - printf ("\n"); - printf (" switch (ppi_table[iword >> 4]) {\n"); - - for (; p->name; p++) - { - int shift, j; - int cond = 0; - int havedecl = 0; - - char *s = p->code; - - printf (" /* %s %s */\n", p->name, p->code); - printf (" case %d: \n", p->index); - - printf (" {\n"); - for (shift = 16; *s; ) - { - switch (*s) - { - case 'i': - printf (" int i = (iword >> 4) & 0x7f;\n"); - s += 6; - break; - case 'e': - case 'f': - case 'x': - case 'y': - case 'g': - case 'u': - shift -= 2; - printf (" int %c = %c_tab[(iword >> %d) & 3];\n", - *s, *s, shift); - havedecl = 1; - s += 2; - break; - case 'c': - printf (" if ((((iword >> 8) ^ DSR) & 1) == 0)\n"); - printf ("\treturn;\n"); - printf (" }\n"); - printf (" case %d: \n", p->index + 1); - printf (" {\n"); - cond = 1; - case '0': - case '1': - case '.': - shift -= 2; - s += 2; - break; - case 'z': - if (havedecl) - printf ("\n"); - printf (" z = iword & 0xf;\n"); - havedecl = 2; - s += 4; - break; - } - } - if (havedecl == 1) - printf ("\n"); - else if (havedecl == 2) - printf (" {\n"); - for (j = 0; j < MAX_NR_STUFF; j++) - { - if (p->stuff[j]) - { - printf (" %s%s\n", - (havedecl == 2 ? " " : ""), - p->stuff[j]); - } - } - if (havedecl == 2) - printf (" }\n"); - if (cond) - { - printf (" if (iword & 0x200)\n"); - printf (" goto assign_z;\n"); - } - printf (" break;\n"); - printf (" }\n"); - } - - printf (" default:\n"); - printf (" {\n"); - printf (" RAISE_EXCEPTION (SIGILL);\n"); - printf (" return;\n"); - printf (" }\n"); - printf (" }\n"); - printf (" DSR &= ~0xf1;\n"); - printf (" if (res || res_grd)\n"); - printf (" DSR |= greater_equal | res_grd >> 2 & DSR_MASK_N | overflow;\n"); - printf (" else\n"); - printf (" DSR |= DSR_MASK_Z | overflow;\n"); - printf (" assign_dc:\n"); - printf (" switch (DSR >> 1 & 7)\n"); - printf (" {\n"); - printf (" case 0: /* Carry Mode */\n"); - printf (" DSR |= carry;\n"); - printf (" case 1: /* Negative Value Mode */\n"); - printf (" DSR |= res_grd >> 7 & 1;\n"); - printf (" case 2: /* Zero Value Mode */\n"); - printf (" DSR |= DSR >> 6 & 1;\n"); - printf (" case 3: /* Overflow mode\n"); - printf (" DSR |= overflow >> 4;\n"); - printf (" case 4: /* Signed Greater Than Mode */\n"); - printf (" DSR |= DSR >> 7 & 1;\n"); - printf (" case 4: /* Signed Greater Than Or Equal Mode */\n"); - printf (" DSR |= greater_equal >> 7;\n"); - printf (" }\n"); - printf (" assign_z:\n"); - printf (" if (0xa05f >> z & 1)\n"); - printf (" {\n"); - printf (" RAISE_EXCEPTION (SIGILL);\n"); - printf (" return;\n"); - printf (" }\n"); - printf (" DSP_R (z) = res;\n"); - printf (" DSP_GRD (z) = res_grd;\n"); - printf ("}\n"); -} - -int -main (ac, av) - int ac; - char **av; -{ - /* Verify the table before anything else. */ - { - op *p; - for (p = tab; p->name; p++) - { - /* Check that the code field contains 16 bits. */ - if (strlen (p->code) != 16) - { - fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n", - p->code, strlen (p->code), p->name); - abort (); - } - } - } - - /* Now generate the requested data. */ - if (ac > 1) - { - if (ac > 2 && strcmp (av[2], "-w") == 0) - { - warn_conflicts = 1; - } - if (strcmp (av[1], "-t") == 0) - { - gengastab (); - } - else if (strcmp (av[1], "-d") == 0) - { - gendefines (); - } - else if (strcmp (av[1], "-s") == 0) - { - filltable (tab); - dumptable ("sh_jump_table", 1 << 16, 0); - - memset (table, 0, sizeof table); - filltable (movsxy_tab); - expand_ppi_movxy (); - dumptable ("sh_dsp_table", 1 << 12, 0xf000); - - memset (table, 0, sizeof table); - ppi_filltable (); - dumptable ("ppi_table", 1 << 12, 0); - } - else if (strcmp (av[1], "-x") == 0) - { - filltable (tab); - filltable (movsxy_tab); - gensim (); - } - else if (strcmp (av[1], "-p") == 0) - { - ppi_filltable (); - ppi_gensim (); - } - } - else - fprintf (stderr, "Opcode table generation no longer supported.\n"); - return 0; -} diff --git a/sim/sh/interp.c b/sim/sh/interp.c deleted file mode 100644 index d89b0dc..0000000 --- a/sim/sh/interp.c +++ /dev/null @@ -1,2777 +0,0 @@ -/* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture. - - Written by Steve Chamberlain of Cygnus Support. - sac@cygnus.com - - This file is part of SH sim - - - THIS SOFTWARE IS NOT COPYRIGHTED - - Cygnus offers the following for use in the public domain. Cygnus - makes no warranty with regard to the software or it's performance - and the user accepts the software "AS IS" with all faults. - - CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO - THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -*/ - -#include "config.h" - -#include <signal.h> -#ifdef HAVE_UNISTD_H -#include <unistd.h> -#endif -#ifdef HAVE_MMAP -#include <sys/mman.h> -# ifndef MAP_FAILED -# define MAP_FAILED -1 -# endif -# if !defined (MAP_ANONYMOUS) && defined (MAP_ANON) -# define MAP_ANONYMOUS MAP_ANON -# endif -#endif - -#include "sysdep.h" -#include "bfd.h" -#include "gdb/callback.h" -#include "gdb/remote-sim.h" -#include "gdb/sim-sh.h" - -/* This file is local - if newlib changes, then so should this. */ -#include "syscall.h" - -#include <math.h> - -#ifdef _WIN32 -#include <float.h> /* Needed for _isnan() */ -#define isnan _isnan -#endif - -#ifndef SIGBUS -#define SIGBUS SIGSEGV -#endif - -#ifndef SIGQUIT -#define SIGQUIT SIGTERM -#endif - -#ifndef SIGTRAP -#define SIGTRAP 5 -#endif - -extern unsigned short sh_jump_table[], sh_dsp_table[0x1000], ppi_table[]; - -int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size); - -#define O_RECOMPILE 85 -#define DEFINE_TABLE -#define DISASSEMBLER_TABLE - -/* Define the rate at which the simulator should poll the host - for a quit. */ -#define POLL_QUIT_INTERVAL 0x60000 - -typedef struct -{ - int regs[20]; -} regstacktype; - -typedef union -{ - - struct - { - int regs[16]; - int pc; - - /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1 - which are located in fregs, i.e. strictly speaking, these are - out-of-bounds accesses of sregs.i . This wart of the code could be - fixed by making fregs part of sregs, and including pc too - to avoid - alignment repercussions - but this would cause very onerous union / - structure nesting, which would only be managable with anonymous - unions and structs. */ - union - { - struct - { - int mach; - int macl; - int pr; - int dummy3, dummy4; - int fpul; /* A1 for sh-dsp - but only for movs etc. */ - int fpscr; /* dsr for sh-dsp */ - } named; - int i[7]; - } sregs; - - /* sh3e / sh-dsp */ - union fregs_u - { - float f[16]; - double d[8]; - int i[16]; - } - fregs[2]; - - /* Control registers; on the SH4, ldc / stc is privileged, except when - accessing gbr. */ - union - { - struct - { - int sr; - int gbr; - int vbr; - int ssr; - int spc; - int mod; - /* sh-dsp */ - int rs; - int re; - /* sh3 */ - int bank[8]; - int dbr; /* debug base register */ - int sgr; /* saved gr15 */ - int ldst; /* load/store flag (boolean) */ - int tbr; - int ibcr; /* sh2a bank control register */ - int ibnr; /* sh2a bank number register */ - } named; - int i[16]; - } cregs; - - unsigned char *insn_end; - - int ticks; - int stalls; - int memstalls; - int cycles; - int insts; - - int prevlock; - int thislock; - int exception; - - int end_of_registers; - - int msize; -#define PROFILE_FREQ 1 -#define PROFILE_SHIFT 2 - int profile; - unsigned short *profile_hist; - unsigned char *memory; - int xyram_select, xram_start, yram_start; - unsigned char *xmem; - unsigned char *ymem; - unsigned char *xmem_offset; - unsigned char *ymem_offset; - unsigned long bfd_mach; - regstacktype *regstack; - } - asregs; - int asints[40]; -} saved_state_type; - -saved_state_type saved_state; - -struct loop_bounds { unsigned char *start, *end; }; - -/* These variables are at file scope so that functions other than - sim_resume can use the fetch/store macros */ - -static int target_little_endian; -static int global_endianw, endianb; -static int target_dsp; -static int host_little_endian; -static char **prog_argv; - -static int maskw = 0; -static int maskl = 0; - -static SIM_OPEN_KIND sim_kind; -static char *myname; -static int tracing = 0; - - -/* Short hand definitions of the registers */ - -#define SBIT(x) ((x)&sbit) -#define R0 saved_state.asregs.regs[0] -#define Rn saved_state.asregs.regs[n] -#define Rm saved_state.asregs.regs[m] -#define UR0 (unsigned int) (saved_state.asregs.regs[0]) -#define UR (unsigned int) R -#define UR (unsigned int) R -#define SR0 saved_state.asregs.regs[0] -#define CREG(n) (saved_state.asregs.cregs.i[(n)]) -#define GBR saved_state.asregs.cregs.named.gbr -#define VBR saved_state.asregs.cregs.named.vbr -#define DBR saved_state.asregs.cregs.named.dbr -#define TBR saved_state.asregs.cregs.named.tbr -#define IBCR saved_state.asregs.cregs.named.ibcr -#define IBNR saved_state.asregs.cregs.named.ibnr -#define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff) -#define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3) -#define SSR saved_state.asregs.cregs.named.ssr -#define SPC saved_state.asregs.cregs.named.spc -#define SGR saved_state.asregs.cregs.named.sgr -#define SREG(n) (saved_state.asregs.sregs.i[(n)]) -#define MACH saved_state.asregs.sregs.named.mach -#define MACL saved_state.asregs.sregs.named.macl -#define PR saved_state.asregs.sregs.named.pr -#define FPUL saved_state.asregs.sregs.named.fpul - -#define PC insn_ptr - - - -/* Alternate bank of registers r0-r7 */ - -/* Note: code controling SR handles flips between BANK0 and BANK1 */ -#define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)]) -#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0) - - -/* Manipulate SR */ - -#define SR_MASK_BO (1 << 14) -#define SR_MASK_CS (1 << 13) -#define SR_MASK_DMY (1 << 11) -#define SR_MASK_DMX (1 << 10) -#define SR_MASK_M (1 << 9) -#define SR_MASK_Q (1 << 8) -#define SR_MASK_I (0xf << 4) -#define SR_MASK_S (1 << 1) -#define SR_MASK_T (1 << 0) - -#define SR_MASK_BL (1 << 28) -#define SR_MASK_RB (1 << 29) -#define SR_MASK_MD (1 << 30) -#define SR_MASK_RC 0x0fff0000 -#define SR_RC_INCREMENT -0x00010000 - -#define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0) -#define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0) -#define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0) -#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0) -#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0) -#define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0) -#define LDST ((saved_state.asregs.cregs.named.ldst) != 0) - -#define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0) -#define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0) -#define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0) -#define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0) -#define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0) -#define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC)) - -/* Note: don't use this for privileged bits */ -#define SET_SR_BIT(EXP, BIT) \ -do { \ - if ((EXP) & 1) \ - saved_state.asregs.cregs.named.sr |= (BIT); \ - else \ - saved_state.asregs.cregs.named.sr &= ~(BIT); \ -} while (0) - -#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO) -#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS) -#define SET_BANKN(EXP) \ -do { \ - IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \ -} while (0) -#define SET_ME(EXP) \ -do { \ - IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \ -} while (0) -#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M) -#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q) -#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S) -#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T) -#define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0)) - -/* stc currently relies on being able to read SR without modifications. */ -#define GET_SR() (saved_state.asregs.cregs.named.sr - 0) - -#define SET_SR(x) set_sr (x) - -#define SET_RC(x) \ - (saved_state.asregs.cregs.named.sr \ - = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16) - -/* Manipulate FPSCR */ - -#define FPSCR_MASK_FR (1 << 21) -#define FPSCR_MASK_SZ (1 << 20) -#define FPSCR_MASK_PR (1 << 19) - -#define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0) -#define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0) -#define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0) - -/* Count the number of arguments in an argv. */ -static int -count_argc (char **argv) -{ - int i; - - if (! argv) - return -1; - - for (i = 0; argv[i] != NULL; ++i) - continue; - return i; -} - -static void -set_fpscr1 (x) - int x; -{ - int old = saved_state.asregs.sregs.named.fpscr; - saved_state.asregs.sregs.named.fpscr = (x); - /* swap the floating point register banks */ - if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR - /* Ignore bit change if simulating sh-dsp. */ - && ! target_dsp) - { - union fregs_u tmpf = saved_state.asregs.fregs[0]; - saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1]; - saved_state.asregs.fregs[1] = tmpf; - } -} - -/* sts relies on being able to read fpscr directly. */ -#define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr) -#define SET_FPSCR(x) \ -do { \ - set_fpscr1 (x); \ -} while (0) - -#define DSR (saved_state.asregs.sregs.named.fpscr) - -int -fail () -{ - abort (); -} - -#define RAISE_EXCEPTION(x) \ - (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0) - -#define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \ - if (in_delay_slot) RAISE_EXCEPTION (SIGILL) - -/* This function exists mainly for the purpose of setting a breakpoint to - catch simulated bus errors when running the simulator under GDB. */ - -void -raise_exception (x) - int x; -{ - RAISE_EXCEPTION (x); -} - -void -raise_buserror () -{ - raise_exception (SIGBUS); -} - -#define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \ - forbidden_addr_bits, data, retval) \ -do { \ - if (addr & forbidden_addr_bits) \ - { \ - raise_buserror (); \ - return retval; \ - } \ - else if ((addr & saved_state.asregs.xyram_select) \ - == saved_state.asregs.xram_start) \ - ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \ - else if ((addr & saved_state.asregs.xyram_select) \ - == saved_state.asregs.yram_start) \ - ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \ - else if ((unsigned) addr >> 24 == 0xf0 \ - && bits_written == 32 && (data & 1) == 0) \ - /* This invalidates (if not associative) or might invalidate \ - (if associative) an instruction cache line. This is used for \ - trampolines. Since we don't simulate the cache, this is a no-op \ - as far as the simulator is concerned. */ \ - return retval; \ - else \ - { \ - if (bits_written == 8 && addr > 0x5000000) \ - IOMEM (addr, 1, data); \ - /* We can't do anything useful with the other stuff, so fail. */ \ - raise_buserror (); \ - return retval; \ - } \ -} while (0) - -/* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume - being implemented by ../common/sim_resume.c and the below should - make a call to sim_engine_halt */ - -#define BUSERROR(addr, mask) ((addr) & (mask)) - -#define WRITE_BUSERROR(addr, mask, data, addr_func) \ - do \ - { \ - if (addr & mask) \ - { \ - addr_func (addr, data); \ - return; \ - } \ - } \ - while (0) - -#define READ_BUSERROR(addr, mask, addr_func) \ - do \ - { \ - if (addr & mask) \ - return addr_func (addr); \ - } \ - while (0) - -/* Define this to enable register lifetime checking. - The compiler generates "add #0,rn" insns to mark registers as invalid, - the simulator uses this info to call fail if it finds a ref to an invalid - register before a def - - #define PARANOID -*/ - -#ifdef PARANOID -int valid[16]; -#define CREF(x) if (!valid[x]) fail (); -#define CDEF(x) valid[x] = 1; -#define UNDEF(x) valid[x] = 0; -#else -#define CREF(x) -#define CDEF(x) -#define UNDEF(x) -#endif - -static void parse_and_set_memory_size PARAMS ((char *str)); -static int IOMEM PARAMS ((int addr, int write, int value)); -static struct loop_bounds get_loop_bounds PARAMS ((int, int, unsigned char *, - unsigned char *, int, int)); -static void process_wlat_addr PARAMS ((int, int)); -static void process_wwat_addr PARAMS ((int, int)); -static void process_wbat_addr PARAMS ((int, int)); -static int process_rlat_addr PARAMS ((int)); -static int process_rwat_addr PARAMS ((int)); -static int process_rbat_addr PARAMS ((int)); -static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int)); -static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int)); -static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int)); -static int INLINE rlat_fast PARAMS ((unsigned char *, int, int)); -static int INLINE rwat_fast PARAMS ((unsigned char *, int, int, int)); -static int INLINE rbat_fast PARAMS ((unsigned char *, int, int)); - -static host_callback *callback; - - - -/* Floating point registers */ - -#define DR(n) (get_dr (n)) -static double -get_dr (n) - int n; -{ - n = (n & ~1); - if (host_little_endian) - { - union - { - int i[2]; - double d; - } dr; - dr.i[1] = saved_state.asregs.fregs[0].i[n + 0]; - dr.i[0] = saved_state.asregs.fregs[0].i[n + 1]; - return dr.d; - } - else - return (saved_state.asregs.fregs[0].d[n >> 1]); -} - -#define SET_DR(n, EXP) set_dr ((n), (EXP)) -static void -set_dr (n, exp) - int n; - double exp; -{ - n = (n & ~1); - if (host_little_endian) - { - union - { - int i[2]; - double d; - } dr; - dr.d = exp; - saved_state.asregs.fregs[0].i[n + 0] = dr.i[1]; - saved_state.asregs.fregs[0].i[n + 1] = dr.i[0]; - } - else - saved_state.asregs.fregs[0].d[n >> 1] = exp; -} - -#define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP)) -#define FI(n) (saved_state.asregs.fregs[0].i[(n)]) - -#define FR(n) (saved_state.asregs.fregs[0].f[(n)]) -#define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP)) - -#define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e)) -#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f]) -#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP)) - -#define RS saved_state.asregs.cregs.named.rs -#define RE saved_state.asregs.cregs.named.re -#define MOD (saved_state.asregs.cregs.named.mod) -#define SET_MOD(i) \ -(MOD = (i), \ - MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \ - MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16)) - -#define DSP_R(n) saved_state.asregs.sregs.i[(n)] -#define DSP_GRD(n) DSP_R ((n) + 8) -#define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n))) -#define A1 DSP_R (5) -#define A0 DSP_R (7) -#define X0 DSP_R (8) -#define X1 DSP_R (9) -#define Y0 DSP_R (10) -#define Y1 DSP_R (11) -#define M0 DSP_R (12) -#define A1G DSP_R (13) -#define M1 DSP_R (14) -#define A0G DSP_R (15) -/* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */ -#define MOD_ME DSP_GRD (17) -#define MOD_DELTA DSP_GRD (18) - -#define FP_OP(n, OP, m) \ -{ \ - if (FPSCR_PR) \ - { \ - if (((n) & 1) || ((m) & 1)) \ - RAISE_EXCEPTION (SIGILL); \ - else \ - SET_DR (n, (DR (n) OP DR (m))); \ - } \ - else \ - SET_FR (n, (FR (n) OP FR (m))); \ -} while (0) - -#define FP_UNARY(n, OP) \ -{ \ - if (FPSCR_PR) \ - { \ - if ((n) & 1) \ - RAISE_EXCEPTION (SIGILL); \ - else \ - SET_DR (n, (OP (DR (n)))); \ - } \ - else \ - SET_FR (n, (OP (FR (n)))); \ -} while (0) - -#define FP_CMP(n, OP, m) \ -{ \ - if (FPSCR_PR) \ - { \ - if (((n) & 1) || ((m) & 1)) \ - RAISE_EXCEPTION (SIGILL); \ - else \ - SET_SR_T (DR (n) OP DR (m)); \ - } \ - else \ - SET_SR_T (FR (n) OP FR (m)); \ -} while (0) - -static void -set_sr (new_sr) - int new_sr; -{ - /* do we need to swap banks */ - int old_gpr = SR_MD && SR_RB; - int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB); - if (old_gpr != new_gpr) - { - int i, tmp; - for (i = 0; i < 8; i++) - { - tmp = saved_state.asregs.cregs.named.bank[i]; - saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i]; - saved_state.asregs.regs[i] = tmp; - } - } - saved_state.asregs.cregs.named.sr = new_sr; - SET_MOD (MOD); -} - -static void INLINE -wlat_fast (memory, x, value, maskl) - unsigned char *memory; -{ - int v = value; - unsigned int *p = (unsigned int *) (memory + x); - WRITE_BUSERROR (x, maskl, v, process_wlat_addr); - *p = v; -} - -static void INLINE -wwat_fast (memory, x, value, maskw, endianw) - unsigned char *memory; -{ - int v = value; - unsigned short *p = (unsigned short *) (memory + (x ^ endianw)); - WRITE_BUSERROR (x, maskw, v, process_wwat_addr); - *p = v; -} - -static void INLINE -wbat_fast (memory, x, value, maskb) - unsigned char *memory; -{ - unsigned char *p = memory + (x ^ endianb); - WRITE_BUSERROR (x, maskb, value, process_wbat_addr); - - p[0] = value; -} - -/* Read functions */ - -static int INLINE -rlat_fast (memory, x, maskl) - unsigned char *memory; -{ - unsigned int *p = (unsigned int *) (memory + x); - READ_BUSERROR (x, maskl, process_rlat_addr); - - return *p; -} - -static int INLINE -rwat_fast (memory, x, maskw, endianw) - unsigned char *memory; - int x, maskw, endianw; -{ - unsigned short *p = (unsigned short *) (memory + (x ^ endianw)); - READ_BUSERROR (x, maskw, process_rwat_addr); - - return *p; -} - -static int INLINE -riat_fast (insn_ptr, endianw) - unsigned char *insn_ptr; -{ - unsigned short *p = (unsigned short *) ((size_t) insn_ptr ^ endianw); - - return *p; -} - -static int INLINE -rbat_fast (memory, x, maskb) - unsigned char *memory; -{ - unsigned char *p = memory + (x ^ endianb); - READ_BUSERROR (x, maskb, process_rbat_addr); - - return *p; -} - -#define RWAT(x) (rwat_fast (memory, x, maskw, endianw)) -#define RLAT(x) (rlat_fast (memory, x, maskl)) -#define RBAT(x) (rbat_fast (memory, x, maskb)) -#define RIAT(p) (riat_fast ((p), endianw)) -#define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw)) -#define WLAT(x,v) (wlat_fast (memory, x, v, maskl)) -#define WBAT(x,v) (wbat_fast (memory, x, v, maskb)) - -#define RUWAT(x) (RWAT (x) & 0xffff) -#define RSWAT(x) ((short) (RWAT (x))) -#define RSLAT(x) ((long) (RLAT (x))) -#define RSBAT(x) (SEXT (RBAT (x))) - -#define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl))) -static int -do_rdat (memory, x, n, maskl) - char *memory; - int x; - int n; - int maskl; -{ - int f0; - int f1; - int i = (n & 1); - int j = (n & ~1); - f0 = rlat_fast (memory, x + 0, maskl); - f1 = rlat_fast (memory, x + 4, maskl); - saved_state.asregs.fregs[i].i[(j + 0)] = f0; - saved_state.asregs.fregs[i].i[(j + 1)] = f1; - return 0; -} - -#define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl))) -static int -do_wdat (memory, x, n, maskl) - char *memory; - int x; - int n; - int maskl; -{ - int f0; - int f1; - int i = (n & 1); - int j = (n & ~1); - f0 = saved_state.asregs.fregs[i].i[(j + 0)]; - f1 = saved_state.asregs.fregs[i].i[(j + 1)]; - wlat_fast (memory, (x + 0), f0, maskl); - wlat_fast (memory, (x + 4), f1, maskl); - return 0; -} - -static void -process_wlat_addr (addr, value) - int addr; - int value; -{ - unsigned int *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, ); - *ptr = value; -} - -static void -process_wwat_addr (addr, value) - int addr; - int value; -{ - unsigned short *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, ); - *ptr = value; -} - -static void -process_wbat_addr (addr, value) - int addr; - int value; -{ - unsigned char *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, ); - *ptr = value; -} - -static int -process_rlat_addr (addr) - int addr; -{ - unsigned char *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0); - return *ptr; -} - -static int -process_rwat_addr (addr) - int addr; -{ - unsigned char *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0); - return *ptr; -} - -static int -process_rbat_addr (addr) - int addr; -{ - unsigned char *ptr; - - PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0); - return *ptr; -} - -#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80) -#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800) -#define SEXTW(y) ((int) ((short) y)) -#if 0 -#define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1) -#else -#define SEXT32(x) ((int) (x)) -#endif -#define SIGN32(x) (SEXT32 (x) >> 31) - -/* convert pointer from target to host value. */ -#define PT2H(x) ((x) + memory) -/* convert pointer from host to target value. */ -#define PH2T(x) ((x) - memory) - -#define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2)) - -#define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip); - -static int in_delay_slot = 0; -#define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top; - -#define CHECK_INSN_PTR(p) \ -do { \ - if (saved_state.asregs.exception || PH2T (p) & maskw) \ - saved_state.asregs.insn_end = 0; \ - else if (p < loop.end) \ - saved_state.asregs.insn_end = loop.end; \ - else \ - saved_state.asregs.insn_end = mem_end; \ -} while (0) - -#ifdef ACE_FAST - -#define MA(n) -#define L(x) -#define TL(x) -#define TB(x) - -#else - -#define MA(n) \ - do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0) - -#define L(x) thislock = x; -#define TL(x) if ((x) == prevlock) stalls++; -#define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++; - -#endif - -#if defined(__GO32__) -int sim_memory_size = 19; -#else -int sim_memory_size = 24; -#endif - -static int sim_profile_size = 17; -static int nsamples; - -#undef TB -#define TB(x,y) - -#define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */ -#define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */ -#define SCR1 (0x05FFFECA) /* Channel 1 serial control register */ -#define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */ -#define SSR1 (0x05FFFECC) /* Channel 1 serial status register */ -#define RDR1 (0x05FFFECD) /* Channel 1 receive data register */ - -#define SCI_RDRF 0x40 /* Recieve data register full */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ - -static int -IOMEM (addr, write, value) - int addr; - int write; - int value; -{ - if (write) - { - switch (addr) - { - case TDR1: - if (value != '\r') - { - putchar (value); - fflush (stdout); - } - break; - } - } - else - { - switch (addr) - { - case RDR1: - return getchar (); - } - } - return 0; -} - -static int -get_now () -{ - return time ((long *) 0); -} - -static int -now_persec () -{ - return 1; -} - -static FILE *profile_file; - -static unsigned INLINE -swap (n) - unsigned n; -{ - if (endianb) - n = (n << 24 | (n & 0xff00) << 8 - | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24); - return n; -} - -static unsigned short INLINE -swap16 (n) - unsigned short n; -{ - if (endianb) - n = n << 8 | (n & 0xff00) >> 8; - return n; -} - -static void -swapout (n) - int n; -{ - if (profile_file) - { - union { char b[4]; int n; } u; - u.n = swap (n); - fwrite (u.b, 4, 1, profile_file); - } -} - -static void -swapout16 (n) - int n; -{ - union { char b[4]; int n; } u; - u.n = swap16 (n); - fwrite (u.b, 2, 1, profile_file); -} - -/* Turn a pointer in a register into a pointer into real memory. */ - -static char * -ptr (x) - int x; -{ - return (char *) (x + saved_state.asregs.memory); -} - -/* STR points to a zero-terminated string in target byte order. Return - the number of bytes that need to be converted to host byte order in order - to use this string as a zero-terminated string on the host. - (Not counting the rounding up needed to operate on entire words.) */ -static int -strswaplen (str) - int str; -{ - unsigned char *memory = saved_state.asregs.memory; - int start, end; - int endian = endianb; - - if (! endian) - return 0; - end = str; - for (end = str; memory[end ^ endian]; end++) ; - return end - str + 1; -} - -static void -strnswap (str, len) - int str; - int len; -{ - int *start, *end; - - if (! endianb || ! len) - return; - start = (int *) ptr (str & ~3); - end = (int *) ptr (str + len); - do - { - int old = *start; - *start = (old << 24 | (old & 0xff00) << 8 - | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24); - start++; - } - while (start < end); -} - -/* Simulate a monitor trap, put the result into r0 and errno into r1 - return offset by which to adjust pc. */ - -static int -trap (i, regs, insn_ptr, memory, maskl, maskw, endianw) - int i; - int *regs; - unsigned char *insn_ptr; - unsigned char *memory; -{ - switch (i) - { - case 1: - printf ("%c", regs[0]); - break; - case 2: - raise_exception (SIGQUIT); - break; - case 3: /* FIXME: for backwards compat, should be removed */ - case 33: - { - unsigned int countp = * (unsigned int *) (insn_ptr + 4); - - WLAT (countp, RLAT (countp) + 1); - return 6; - } - case 34: - { - extern int errno; - int perrno = errno; - errno = 0; - - switch (regs[4]) - { - -#if !defined(__GO32__) && !defined(_WIN32) - case SYS_fork: - regs[0] = fork (); - break; -/* This would work only if endianness matched between host and target. - Besides, it's quite dangerous. */ -#if 0 - case SYS_execve: - regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), - (char **) ptr (regs[7])); - break; - case SYS_execv: - regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0); - break; -#endif - case SYS_pipe: - { - regs[0] = (BUSERROR (regs[5], maskl) - ? -EINVAL - : pipe ((int *) ptr (regs[5]))); - } - break; - - case SYS_wait: - regs[0] = wait (ptr (regs[5])); - break; -#endif /* !defined(__GO32__) && !defined(_WIN32) */ - - case SYS_read: - strnswap (regs[6], regs[7]); - regs[0] - = callback->read (callback, regs[5], ptr (regs[6]), regs[7]); - strnswap (regs[6], regs[7]); - break; - case SYS_write: - strnswap (regs[6], regs[7]); - if (regs[5] == 1) - regs[0] = (int) callback->write_stdout (callback, - ptr (regs[6]), regs[7]); - else - regs[0] = (int) callback->write (callback, regs[5], - ptr (regs[6]), regs[7]); - strnswap (regs[6], regs[7]); - break; - case SYS_lseek: - regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]); - break; - case SYS_close: - regs[0] = callback->close (callback,regs[5]); - break; - case SYS_open: - { - int len = strswaplen (regs[5]); - strnswap (regs[5], len); - regs[0] = callback->open (callback, ptr (regs[5]), regs[6]); - strnswap (regs[5], len); - break; - } - case SYS_exit: - /* EXIT - caller can look in r5 to work out the reason */ - raise_exception (SIGQUIT); - regs[0] = regs[5]; - break; - - case SYS_stat: /* added at hmsi */ - /* stat system call */ - { - struct stat host_stat; - int buf; - int len = strswaplen (regs[5]); - - strnswap (regs[5], len); - regs[0] = stat (ptr (regs[5]), &host_stat); - strnswap (regs[5], len); - - buf = regs[6]; - - WWAT (buf, host_stat.st_dev); - buf += 2; - WWAT (buf, host_stat.st_ino); - buf += 2; - WLAT (buf, host_stat.st_mode); - buf += 4; - WWAT (buf, host_stat.st_nlink); - buf += 2; - WWAT (buf, host_stat.st_uid); - buf += 2; - WWAT (buf, host_stat.st_gid); - buf += 2; - WWAT (buf, host_stat.st_rdev); - buf += 2; - WLAT (buf, host_stat.st_size); - buf += 4; - WLAT (buf, host_stat.st_atime); - buf += 4; - WLAT (buf, 0); - buf += 4; - WLAT (buf, host_stat.st_mtime); - buf += 4; - WLAT (buf, 0); - buf += 4; - WLAT (buf, host_stat.st_ctime); - buf += 4; - WLAT (buf, 0); - buf += 4; - WLAT (buf, 0); - buf += 4; - WLAT (buf, 0); - buf += 4; - } - break; - -#ifndef _WIN32 - case SYS_chown: - { - int len = strswaplen (regs[5]); - - strnswap (regs[5], len); - regs[0] = chown (ptr (regs[5]), regs[6], regs[7]); - strnswap (regs[5], len); - break; - } -#endif /* _WIN32 */ - case SYS_chmod: - { - int len = strswaplen (regs[5]); - - strnswap (regs[5], len); - regs[0] = chmod (ptr (regs[5]), regs[6]); - strnswap (regs[5], len); - break; - } - case SYS_utime: - { - /* Cast the second argument to void *, to avoid type mismatch - if a prototype is present. */ - int len = strswaplen (regs[5]); - - strnswap (regs[5], len); - regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6])); - strnswap (regs[5], len); - break; - } - case SYS_argc: - regs[0] = count_argc (prog_argv); - break; - case SYS_argnlen: - if (regs[5] < count_argc (prog_argv)) - regs[0] = strlen (prog_argv[regs[5]]); - else - regs[0] = -1; - break; - case SYS_argn: - if (regs[5] < count_argc (prog_argv)) - { - /* Include the termination byte. */ - int i = strlen (prog_argv[regs[5]]) + 1; - regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i); - } - else - regs[0] = -1; - break; - case SYS_time: - regs[0] = get_now (); - break; - case SYS_ftruncate: - regs[0] = callback->ftruncate (callback, regs[5], regs[6]); - break; - case SYS_truncate: - { - int len = strswaplen (regs[5]); - strnswap (regs[5], len); - regs[0] = callback->truncate (callback, ptr (regs[5]), regs[6]); - strnswap (regs[5], len); - break; - } - default: - regs[0] = -1; - break; - } - regs[1] = callback->get_errno (callback); - errno = perrno; - } - break; - - case 13: /* Set IBNR */ - IBNR = regs[0] & 0xffff; - break; - case 14: /* Set IBCR */ - IBCR = regs[0] & 0xffff; - break; - case 0xc3: - case 255: - raise_exception (SIGTRAP); - if (i == 0xc3) - return -2; - break; - } - return 0; -} - -void -control_c (sig, code, scp, addr) - int sig; - int code; - char *scp; - char *addr; -{ - raise_exception (SIGINT); -} - -static int -div1 (R, iRn2, iRn1/*, T*/) - int *R; - int iRn1; - int iRn2; - /* int T;*/ -{ - unsigned long tmp0; - unsigned char old_q, tmp1; - - old_q = Q; - SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0)); - R[iRn1] <<= 1; - R[iRn1] |= (unsigned long) T; - - switch (old_q) - { - case 0: - switch (M) - { - case 0: - tmp0 = R[iRn1]; - R[iRn1] -= R[iRn2]; - tmp1 = (R[iRn1] > tmp0); - switch (Q) - { - case 0: - SET_SR_Q (tmp1); - break; - case 1: - SET_SR_Q ((unsigned char) (tmp1 == 0)); - break; - } - break; - case 1: - tmp0 = R[iRn1]; - R[iRn1] += R[iRn2]; - tmp1 = (R[iRn1] < tmp0); - switch (Q) - { - case 0: - SET_SR_Q ((unsigned char) (tmp1 == 0)); - break; - case 1: - SET_SR_Q (tmp1); - break; - } - break; - } - break; - case 1: - switch (M) - { - case 0: - tmp0 = R[iRn1]; - R[iRn1] += R[iRn2]; - tmp1 = (R[iRn1] < tmp0); - switch (Q) - { - case 0: - SET_SR_Q (tmp1); - break; - case 1: - SET_SR_Q ((unsigned char) (tmp1 == 0)); - break; - } - break; - case 1: - tmp0 = R[iRn1]; - R[iRn1] -= R[iRn2]; - tmp1 = (R[iRn1] > tmp0); - switch (Q) - { - case 0: - SET_SR_Q ((unsigned char) (tmp1 == 0)); - break; - case 1: - SET_SR_Q (tmp1); - break; - } - break; - } - break; - } - /*T = (Q == M);*/ - SET_SR_T (Q == M); - /*return T;*/ -} - -static void -dmul (sign, rm, rn) - int sign; - unsigned int rm; - unsigned int rn; -{ - unsigned long RnL, RnH; - unsigned long RmL, RmH; - unsigned long temp0, temp1, temp2, temp3; - unsigned long Res2, Res1, Res0; - - RnL = rn & 0xffff; - RnH = (rn >> 16) & 0xffff; - RmL = rm & 0xffff; - RmH = (rm >> 16) & 0xffff; - temp0 = RmL * RnL; - temp1 = RmH * RnL; - temp2 = RmL * RnH; - temp3 = RmH * RnH; - Res2 = 0; - Res1 = temp1 + temp2; - if (Res1 < temp1) - Res2 += 0x00010000; - temp1 = (Res1 << 16) & 0xffff0000; - Res0 = temp0 + temp1; - if (Res0 < temp0) - Res2 += 1; - Res2 += ((Res1 >> 16) & 0xffff) + temp3; - - if (sign) - { - if (rn & 0x80000000) - Res2 -= rm; - if (rm & 0x80000000) - Res2 -= rn; - } - - MACH = Res2; - MACL = Res0; -} - -static void -macw (regs, memory, n, m, endianw) - int *regs; - unsigned char *memory; - int m, n; - int endianw; -{ - long tempm, tempn; - long prod, macl, sum; - - tempm=RSWAT (regs[m]); regs[m]+=2; - tempn=RSWAT (regs[n]); regs[n]+=2; - - macl = MACL; - prod = (long) (short) tempm * (long) (short) tempn; - sum = prod + macl; - if (S) - { - if ((~(prod ^ macl) & (sum ^ prod)) < 0) - { - /* MACH's lsb is a sticky overflow bit. */ - MACH |= 1; - /* Store the smallest negative number in MACL if prod is - negative, and the largest positive number otherwise. */ - sum = 0x7fffffff + (prod < 0); - } - } - else - { - long mach; - /* Add to MACH the sign extended product, and carry from low sum. */ - mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod); - /* Sign extend at 10:th bit in MACH. */ - MACH = (mach & 0x1ff) | -(mach & 0x200); - } - MACL = sum; -} - -static void -macl (regs, memory, n, m) - int *regs; - unsigned char *memory; - int m, n; -{ - long tempm, tempn; - long prod, macl, mach, sum; - long long ans,ansl,ansh,t; - unsigned long long high,low,combine; - union mac64 - { - long m[2]; /* mach and macl*/ - long long m64; /* 64 bit MAC */ - }mac64; - - tempm = RSLAT (regs[m]); - regs[m] += 4; - - tempn = RSLAT (regs[n]); - regs[n] += 4; - - mach = MACH; - macl = MACL; - - mac64.m[0] = macl; - mac64.m[1] = mach; - - ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */ - - mac64.m64 += ans; /* Accumulate 64bit + 64 bit */ - - macl = mac64.m[0]; - mach = mac64.m[1]; - - if (S) /* Store only 48 bits of the result */ - { - if (mach < 0) /* Result is negative */ - { - mach = mach & 0x0000ffff; /* Mask higher 16 bits */ - mach |= 0xffff8000; /* Sign extend higher 16 bits */ - } - else - mach = mach & 0x00007fff; /* Postive Result */ - } - - MACL = macl; - MACH = mach; -} - -enum { - B_BCLR = 0, - B_BSET = 1, - B_BST = 2, - B_BLD = 3, - B_BAND = 4, - B_BOR = 5, - B_BXOR = 6, - B_BLDNOT = 11, - B_BANDNOT = 12, - B_BORNOT = 13, - - MOVB_RM = 0x0000, - MOVW_RM = 0x1000, - MOVL_RM = 0x2000, - FMOV_RM = 0x3000, - MOVB_MR = 0x4000, - MOVW_MR = 0x5000, - MOVL_MR = 0x6000, - FMOV_MR = 0x7000, - MOVU_BMR = 0x8000, - MOVU_WMR = 0x9000, -}; - -/* Do extended displacement move instructions. */ -void -do_long_move_insn (int op, int disp12, int m, int n, int *thatlock) -{ - int memstalls = 0; - int thislock = *thatlock; - int endianw = global_endianw; - int *R = &(saved_state.asregs.regs[0]); - unsigned char *memory = saved_state.asregs.memory; - int maskb = ~((saved_state.asregs.msize - 1) & ~0); - unsigned char *insn_ptr = PT2H (saved_state.asregs.pc); - - switch (op) { - case MOVB_RM: /* signed */ - WBAT (disp12 * 1 + R[n], R[m]); - break; - case MOVW_RM: - WWAT (disp12 * 2 + R[n], R[m]); - break; - case MOVL_RM: - WLAT (disp12 * 4 + R[n], R[m]); - break; - case FMOV_RM: /* floating point */ - if (FPSCR_SZ) - { - MA (1); - WDAT (R[n] + 8 * disp12, m); - } - else - WLAT (R[n] + 4 * disp12, FI (m)); - break; - case MOVB_MR: - R[n] = RSBAT (disp12 * 1 + R[m]); - L (n); - break; - case MOVW_MR: - R[n] = RSWAT (disp12 * 2 + R[m]); - L (n); - break; - case MOVL_MR: - R[n] = RLAT (disp12 * 4 + R[m]); - L (n); - break; - case FMOV_MR: - if (FPSCR_SZ) { - MA (1); - RDAT (R[m] + 8 * disp12, n); - } - else - SET_FI (n, RLAT (R[m] + 4 * disp12)); - break; - case MOVU_BMR: /* unsigned */ - R[n] = RBAT (disp12 * 1 + R[m]); - L (n); - break; - case MOVU_WMR: - R[n] = RWAT (disp12 * 2 + R[m]); - L (n); - break; - default: - RAISE_EXCEPTION (SIGINT); - exit (1); - } - saved_state.asregs.memstalls += memstalls; - *thatlock = thislock; -} - -/* Do binary logical bit-manipulation insns. */ -void -do_blog_insn (int imm, int addr, int binop, - unsigned char *memory, int maskb) -{ - int oldval = RBAT (addr); - - switch (binop) { - case B_BCLR: /* bclr.b */ - WBAT (addr, oldval & ~imm); - break; - case B_BSET: /* bset.b */ - WBAT (addr, oldval | imm); - break; - case B_BST: /* bst.b */ - if (T) - WBAT (addr, oldval | imm); - else - WBAT (addr, oldval & ~imm); - break; - case B_BLD: /* bld.b */ - SET_SR_T ((oldval & imm) != 0); - break; - case B_BAND: /* band.b */ - SET_SR_T (T && ((oldval & imm) != 0)); - break; - case B_BOR: /* bor.b */ - SET_SR_T (T || ((oldval & imm) != 0)); - break; - case B_BXOR: /* bxor.b */ - SET_SR_T (T ^ ((oldval & imm) != 0)); - break; - case B_BLDNOT: /* bldnot.b */ - SET_SR_T ((oldval & imm) == 0); - break; - case B_BANDNOT: /* bandnot.b */ - SET_SR_T (T && ((oldval & imm) == 0)); - break; - case B_BORNOT: /* bornot.b */ - SET_SR_T (T || ((oldval & imm) == 0)); - break; - } -} -float -fsca_s (int in, double (*f) (double)) -{ - double rad = ldexp ((in & 0xffff), -15) * 3.141592653589793238462643383; - double result = (*f) (rad); - double error, upper, lower, frac; - int exp; - - /* Search the value with the maximum error that is still within the - architectural spec. */ - error = ldexp (1., -21); - /* compensate for calculation inaccuracy by reducing error. */ - error = error - ldexp (1., -50); - upper = result + error; - frac = frexp (upper, &exp); - upper = ldexp (floor (ldexp (frac, 24)), exp - 24); - lower = result - error; - frac = frexp (lower, &exp); - lower = ldexp (ceil (ldexp (frac, 24)), exp - 24); - return abs (upper - result) >= abs (lower - result) ? upper : lower; -} - -float -fsrra_s (float in) -{ - double result = 1. / sqrt (in); - int exp; - double frac, upper, lower, error, eps; - - /* refine result */ - result = result - (result * result * in - 1) * 0.5 * result; - /* Search the value with the maximum error that is still within the - architectural spec. */ - frac = frexp (result, &exp); - frac = ldexp (frac, 24); - error = 4.0; /* 1 << 24-1-21 */ - /* use eps to compensate for possible 1 ulp error in our 'exact' result. */ - eps = ldexp (1., -29); - upper = floor (frac + error - eps); - if (upper > 16777216.) - upper = floor ((frac + error - eps) * 0.5) * 2.; - lower = ceil ((frac - error + eps) * 2) * .5; - if (lower > 8388608.) - lower = ceil (frac - error + eps); - upper = ldexp (upper, exp - 24); - lower = ldexp (lower, exp - 24); - return upper - result >= result - lower ? upper : lower; -} - - -/* GET_LOOP_BOUNDS {EXTENDED} - These two functions compute the actual starting and ending point - of the repeat loop, based on the RS and RE registers (repeat start, - repeat stop). The extended version is called for LDRC, and the - regular version is called for SETRC. The difference is that for - LDRC, the loop start and end instructions are literally the ones - pointed to by RS and RE -- for SETRC, they're not (see docs). */ - -static struct loop_bounds -get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw) - int rs, re; - unsigned char *memory, *mem_end; - int maskw, endianw; -{ - struct loop_bounds loop; - - /* FIXME: should I verify RS < RE? */ - loop.start = PT2H (RS); /* FIXME not using the params? */ - loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */ - SKIP_INSN (loop.end); - if (loop.end >= mem_end) - loop.end = PT2H (0); - return loop; -} - -static struct loop_bounds -get_loop_bounds (rs, re, memory, mem_end, maskw, endianw) - int rs, re; - unsigned char *memory, *mem_end; - int maskw, endianw; -{ - struct loop_bounds loop; - - if (SR_RC) - { - if (RS >= RE) - { - loop.start = PT2H (RE - 4); - SKIP_INSN (loop.start); - loop.end = loop.start; - if (RS - RE == 0) - SKIP_INSN (loop.end); - if (RS - RE <= 2) - SKIP_INSN (loop.end); - SKIP_INSN (loop.end); - } - else - { - loop.start = PT2H (RS); - loop.end = PT2H (RE - 4); - SKIP_INSN (loop.end); - SKIP_INSN (loop.end); - SKIP_INSN (loop.end); - SKIP_INSN (loop.end); - } - if (loop.end >= mem_end) - loop.end = PT2H (0); - } - else - loop.end = PT2H (0); - - return loop; -} - -static void ppi_insn (); - -#include "ppi.c" - -/* Provide calloc / free versions that use an anonymous mmap. This can - significantly cut the start-up time when a large simulator memory is - required, because pages are only zeroed on demand. */ -#ifdef MAP_ANONYMOUS -void * -mcalloc (size_t nmemb, size_t size) -{ - void *page; - - if (nmemb != 1) - size *= nmemb; - return mmap (0, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, - -1, 0); -} - -#define mfree(start,length) munmap ((start), (length)) -#else -#define mcalloc calloc -#define mfree(start,length) free(start) -#endif - -/* Set the memory size to the power of two provided. */ - -void -sim_size (power) - int power; - -{ - sim_memory_size = power; - - if (saved_state.asregs.memory) - { - mfree (saved_state.asregs.memory, saved_state.asregs.msize); - } - - saved_state.asregs.msize = 1 << power; - - saved_state.asregs.memory = - (unsigned char *) mcalloc (1, saved_state.asregs.msize); - - if (!saved_state.asregs.memory) - { - fprintf (stderr, - "Not enough VM for simulation of %d bytes of RAM\n", - saved_state.asregs.msize); - - saved_state.asregs.msize = 1; - saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1); - } -} - -static void -init_dsp (abfd) - struct bfd *abfd; -{ - int was_dsp = target_dsp; - unsigned long mach = bfd_get_mach (abfd); - - if (mach == bfd_mach_sh_dsp || - mach == bfd_mach_sh4al_dsp || - mach == bfd_mach_sh3_dsp) - { - int ram_area_size, xram_start, yram_start; - int new_select; - - target_dsp = 1; - if (mach == bfd_mach_sh_dsp) - { - /* SH7410 (orig. sh-sdp): - 4KB each for X & Y memory; - On-chip X RAM 0x0800f000-0x0800ffff - On-chip Y RAM 0x0801f000-0x0801ffff */ - xram_start = 0x0800f000; - ram_area_size = 0x1000; - } - if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp) - { - /* SH7612: - 8KB each for X & Y memory; - On-chip X RAM 0x1000e000-0x1000ffff - On-chip Y RAM 0x1001e000-0x1001ffff */ - xram_start = 0x1000e000; - ram_area_size = 0x2000; - } - yram_start = xram_start + 0x10000; - new_select = ~(ram_area_size - 1); - if (saved_state.asregs.xyram_select != new_select) - { - saved_state.asregs.xyram_select = new_select; - free (saved_state.asregs.xmem); - free (saved_state.asregs.ymem); - saved_state.asregs.xmem = - (unsigned char *) calloc (1, ram_area_size); - saved_state.asregs.ymem = - (unsigned char *) calloc (1, ram_area_size); - - /* Disable use of X / Y mmeory if not allocated. */ - if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem) - { - saved_state.asregs.xyram_select = 0; - if (saved_state.asregs.xmem) - free (saved_state.asregs.xmem); - if (saved_state.asregs.ymem) - free (saved_state.asregs.ymem); - } - } - saved_state.asregs.xram_start = xram_start; - saved_state.asregs.yram_start = yram_start; - saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start; - saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start; - } - else - { - target_dsp = 0; - if (saved_state.asregs.xyram_select) - { - saved_state.asregs.xyram_select = 0; - free (saved_state.asregs.xmem); - free (saved_state.asregs.ymem); - } - } - - if (! saved_state.asregs.xyram_select) - { - saved_state.asregs.xram_start = 1; - saved_state.asregs.yram_start = 1; - } - - if (saved_state.asregs.regstack == NULL) - saved_state.asregs.regstack = - calloc (512, sizeof *saved_state.asregs.regstack); - - if (target_dsp != was_dsp) - { - int i, tmp; - - for (i = (sizeof sh_dsp_table / sizeof sh_dsp_table[0]) - 1; i >= 0; i--) - { - tmp = sh_jump_table[0xf000 + i]; - sh_jump_table[0xf000 + i] = sh_dsp_table[i]; - sh_dsp_table[i] = tmp; - } - } -} - -static void -init_pointers () -{ - host_little_endian = 0; - * (char*) &host_little_endian = 1; - host_little_endian &= 1; - - if (saved_state.asregs.msize != 1 << sim_memory_size) - { - sim_size (sim_memory_size); - } - - if (saved_state.asregs.profile && !profile_file) - { - profile_file = fopen ("gmon.out", "wb"); - /* Seek to where to put the call arc data */ - nsamples = (1 << sim_profile_size); - - fseek (profile_file, nsamples * 2 + 12, 0); - - if (!profile_file) - { - fprintf (stderr, "Can't open gmon.out\n"); - } - else - { - saved_state.asregs.profile_hist = - (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64)); - } - } -} - -static void -dump_profile () -{ - unsigned int minpc; - unsigned int maxpc; - unsigned short *p; - int i; - - p = saved_state.asregs.profile_hist; - minpc = 0; - maxpc = (1 << sim_profile_size); - - fseek (profile_file, 0L, 0); - swapout (minpc << PROFILE_SHIFT); - swapout (maxpc << PROFILE_SHIFT); - swapout (nsamples * 2 + 12); - for (i = 0; i < nsamples; i++) - swapout16 (saved_state.asregs.profile_hist[i]); - -} - -static void -gotcall (from, to) - int from; - int to; -{ - swapout (from); - swapout (to); - swapout (1); -} - -#define MMASKB ((saved_state.asregs.msize -1) & ~0) - -int -sim_stop (sd) - SIM_DESC sd; -{ - raise_exception (SIGINT); - return 1; -} - -void -sim_resume (sd, step, siggnal) - SIM_DESC sd; - int step, siggnal; -{ - register unsigned char *insn_ptr; - unsigned char *mem_end; - struct loop_bounds loop; - register int cycles = 0; - register int stalls = 0; - register int memstalls = 0; - register int insts = 0; - register int prevlock; -#if 1 - int thislock; -#else - register int thislock; -#endif - register unsigned int doprofile; - register int pollcount = 0; - /* endianw is used for every insn fetch, hence it makes sense to cache it. - endianb is used less often. */ - register int endianw = global_endianw; - - int tick_start = get_now (); - void (*prev) (); - void (*prev_fpe) (); - - register unsigned short *jump_table = sh_jump_table; - - register int *R = &(saved_state.asregs.regs[0]); - /*register int T;*/ -#ifndef PR - register int PR; -#endif - - register int maskb = ~((saved_state.asregs.msize - 1) & ~0); - register int maskw = ~((saved_state.asregs.msize - 1) & ~1); - register int maskl = ~((saved_state.asregs.msize - 1) & ~3); - register unsigned char *memory; - register unsigned int sbit = ((unsigned int) 1 << 31); - - prev = signal (SIGINT, control_c); - prev_fpe = signal (SIGFPE, SIG_IGN); - - init_pointers (); - saved_state.asregs.exception = 0; - - memory = saved_state.asregs.memory; - mem_end = memory + saved_state.asregs.msize; - - if (RE & 1) - loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw); - else - loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw); - - insn_ptr = PT2H (saved_state.asregs.pc); - CHECK_INSN_PTR (insn_ptr); - -#ifndef PR - PR = saved_state.asregs.sregs.named.pr; -#endif - /*T = GET_SR () & SR_MASK_T;*/ - prevlock = saved_state.asregs.prevlock; - thislock = saved_state.asregs.thislock; - doprofile = saved_state.asregs.profile; - - /* If profiling not enabled, disable it by asking for - profiles infrequently. */ - if (doprofile == 0) - doprofile = ~0; - - loop: - if (step && insn_ptr < saved_state.asregs.insn_end) - { - if (saved_state.asregs.exception) - /* This can happen if we've already been single-stepping and - encountered a loop end. */ - saved_state.asregs.insn_end = insn_ptr; - else - { - saved_state.asregs.exception = SIGTRAP; - saved_state.asregs.insn_end = insn_ptr + 2; - } - } - - while (insn_ptr < saved_state.asregs.insn_end) - { - register unsigned int iword = RIAT (insn_ptr); - register unsigned int ult; - register unsigned char *nip = insn_ptr + 2; - -#ifndef ACE_FAST - insts++; -#endif - top: - if (tracing) - fprintf (stderr, "PC: %08x, insn: %04x\n", PH2T (insn_ptr), iword); - -#include "code.c" - - - in_delay_slot = 0; - insn_ptr = nip; - - if (--pollcount < 0) - { - pollcount = POLL_QUIT_INTERVAL; - if ((*callback->poll_quit) != NULL - && (*callback->poll_quit) (callback)) - { - sim_stop (sd); - } - } - -#ifndef ACE_FAST - prevlock = thislock; - thislock = 30; - cycles++; - - if (cycles >= doprofile) - { - - saved_state.asregs.cycles += doprofile; - cycles -= doprofile; - if (saved_state.asregs.profile_hist) - { - int n = PH2T (insn_ptr) >> PROFILE_SHIFT; - if (n < nsamples) - { - int i = saved_state.asregs.profile_hist[n]; - if (i < 65000) - saved_state.asregs.profile_hist[n] = i + 1; - } - - } - } -#endif - } - if (saved_state.asregs.insn_end == loop.end) - { - saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT; - if (SR_RC) - insn_ptr = loop.start; - else - { - saved_state.asregs.insn_end = mem_end; - loop.end = PT2H (0); - } - goto loop; - } - - if (saved_state.asregs.exception == SIGILL - || saved_state.asregs.exception == SIGBUS) - { - insn_ptr -= 2; - } - /* Check for SIGBUS due to insn fetch. */ - else if (! saved_state.asregs.exception) - saved_state.asregs.exception = SIGBUS; - - saved_state.asregs.ticks += get_now () - tick_start; - saved_state.asregs.cycles += cycles; - saved_state.asregs.stalls += stalls; - saved_state.asregs.memstalls += memstalls; - saved_state.asregs.insts += insts; - saved_state.asregs.pc = PH2T (insn_ptr); -#ifndef PR - saved_state.asregs.sregs.named.pr = PR; -#endif - - saved_state.asregs.prevlock = prevlock; - saved_state.asregs.thislock = thislock; - - if (profile_file) - { - dump_profile (); - } - - signal (SIGFPE, prev_fpe); - signal (SIGINT, prev); -} - -int -sim_write (sd, addr, buffer, size) - SIM_DESC sd; - SIM_ADDR addr; - unsigned char *buffer; - int size; -{ - int i; - - init_pointers (); - - for (i = 0; i < size; i++) - { - saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i]; - } - return size; -} - -int -sim_read (sd, addr, buffer, size) - SIM_DESC sd; - SIM_ADDR addr; - unsigned char *buffer; - int size; -{ - int i; - - init_pointers (); - - for (i = 0; i < size; i++) - { - buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb]; - } - return size; -} - -static int gdb_bank_number; -enum { - REGBANK_MACH = 15, - REGBANK_IVN = 16, - REGBANK_PR = 17, - REGBANK_GBR = 18, - REGBANK_MACL = 19 -}; - -int -sim_store_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; -{ - unsigned val; - - init_pointers (); - val = swap (* (int *) memory); - switch (rn) - { - case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: - case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: - case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: - case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: - case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: - case SIM_SH_R15_REGNUM: - saved_state.asregs.regs[rn] = val; - break; - case SIM_SH_PC_REGNUM: - saved_state.asregs.pc = val; - break; - case SIM_SH_PR_REGNUM: - PR = val; - break; - case SIM_SH_GBR_REGNUM: - GBR = val; - break; - case SIM_SH_VBR_REGNUM: - VBR = val; - break; - case SIM_SH_MACH_REGNUM: - MACH = val; - break; - case SIM_SH_MACL_REGNUM: - MACL = val; - break; - case SIM_SH_SR_REGNUM: - SET_SR (val); - break; - case SIM_SH_FPUL_REGNUM: - FPUL = val; - break; - case SIM_SH_FPSCR_REGNUM: - SET_FPSCR (val); - break; - case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: - case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: - case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: - case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: - case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: - case SIM_SH_FR15_REGNUM: - SET_FI (rn - SIM_SH_FR0_REGNUM, val); - break; - case SIM_SH_DSR_REGNUM: - DSR = val; - break; - case SIM_SH_A0G_REGNUM: - A0G = val; - break; - case SIM_SH_A0_REGNUM: - A0 = val; - break; - case SIM_SH_A1G_REGNUM: - A1G = val; - break; - case SIM_SH_A1_REGNUM: - A1 = val; - break; - case SIM_SH_M0_REGNUM: - M0 = val; - break; - case SIM_SH_M1_REGNUM: - M1 = val; - break; - case SIM_SH_X0_REGNUM: - X0 = val; - break; - case SIM_SH_X1_REGNUM: - X1 = val; - break; - case SIM_SH_Y0_REGNUM: - Y0 = val; - break; - case SIM_SH_Y1_REGNUM: - Y1 = val; - break; - case SIM_SH_MOD_REGNUM: - SET_MOD (val); - break; - case SIM_SH_RS_REGNUM: - RS = val; - break; - case SIM_SH_RE_REGNUM: - RE = val; - break; - case SIM_SH_SSR_REGNUM: - SSR = val; - break; - case SIM_SH_SPC_REGNUM: - SPC = val; - break; - /* The rn_bank idiosyncracies are not due to hardware differences, but to - a weird aliasing naming scheme for sh3 / sh3e / sh4. */ - case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: - case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: - case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: - case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: - if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) - { - rn -= SIM_SH_R0_BANK0_REGNUM; - saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val; - } - else - if (SR_MD && SR_RB) - Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val; - else - saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val; - break; - case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: - case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: - case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: - case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: - if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) - { - rn -= SIM_SH_R0_BANK1_REGNUM; - saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val; - } - else - if (SR_MD && SR_RB) - saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val; - else - Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val; - break; - case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: - case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: - case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: - case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: - SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val); - break; - case SIM_SH_TBR_REGNUM: - TBR = val; - break; - case SIM_SH_IBNR_REGNUM: - IBNR = val; - break; - case SIM_SH_IBCR_REGNUM: - IBCR = val; - break; - case SIM_SH_BANK_REGNUM: - /* This is a pseudo-register maintained just for gdb. - It tells us what register bank gdb would like to read/write. */ - gdb_bank_number = val; - break; - case SIM_SH_BANK_MACL_REGNUM: - saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val; - break; - case SIM_SH_BANK_GBR_REGNUM: - saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val; - break; - case SIM_SH_BANK_PR_REGNUM: - saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val; - break; - case SIM_SH_BANK_IVN_REGNUM: - saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val; - break; - case SIM_SH_BANK_MACH_REGNUM: - saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val; - break; - default: - return 0; - } - return -1; -} - -int -sim_fetch_register (sd, rn, memory, length) - SIM_DESC sd; - int rn; - unsigned char *memory; - int length; -{ - int val; - - init_pointers (); - switch (rn) - { - case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: - case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: - case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: - case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: - case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: - case SIM_SH_R15_REGNUM: - val = saved_state.asregs.regs[rn]; - break; - case SIM_SH_PC_REGNUM: - val = saved_state.asregs.pc; - break; - case SIM_SH_PR_REGNUM: - val = PR; - break; - case SIM_SH_GBR_REGNUM: - val = GBR; - break; - case SIM_SH_VBR_REGNUM: - val = VBR; - break; - case SIM_SH_MACH_REGNUM: - val = MACH; - break; - case SIM_SH_MACL_REGNUM: - val = MACL; - break; - case SIM_SH_SR_REGNUM: - val = GET_SR (); - break; - case SIM_SH_FPUL_REGNUM: - val = FPUL; - break; - case SIM_SH_FPSCR_REGNUM: - val = GET_FPSCR (); - break; - case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: - case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: - case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: - case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: - case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: - case SIM_SH_FR15_REGNUM: - val = FI (rn - SIM_SH_FR0_REGNUM); - break; - case SIM_SH_DSR_REGNUM: - val = DSR; - break; - case SIM_SH_A0G_REGNUM: - val = SEXT (A0G); - break; - case SIM_SH_A0_REGNUM: - val = A0; - break; - case SIM_SH_A1G_REGNUM: - val = SEXT (A1G); - break; - case SIM_SH_A1_REGNUM: - val = A1; - break; - case SIM_SH_M0_REGNUM: - val = M0; - break; - case SIM_SH_M1_REGNUM: - val = M1; - break; - case SIM_SH_X0_REGNUM: - val = X0; - break; - case SIM_SH_X1_REGNUM: - val = X1; - break; - case SIM_SH_Y0_REGNUM: - val = Y0; - break; - case SIM_SH_Y1_REGNUM: - val = Y1; - break; - case SIM_SH_MOD_REGNUM: - val = MOD; - break; - case SIM_SH_RS_REGNUM: - val = RS; - break; - case SIM_SH_RE_REGNUM: - val = RE; - break; - case SIM_SH_SSR_REGNUM: - val = SSR; - break; - case SIM_SH_SPC_REGNUM: - val = SPC; - break; - /* The rn_bank idiosyncracies are not due to hardware differences, but to - a weird aliasing naming scheme for sh3 / sh3e / sh4. */ - case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: - case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: - case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: - case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: - if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) - { - rn -= SIM_SH_R0_BANK0_REGNUM; - val = saved_state.asregs.regstack[gdb_bank_number].regs[rn]; - } - else - val = (SR_MD && SR_RB - ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) - : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]); - break; - case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: - case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: - case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: - case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: - if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) - { - rn -= SIM_SH_R0_BANK1_REGNUM; - val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8]; - } - else - val = (! SR_MD || ! SR_RB - ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) - : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]); - break; - case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: - case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: - case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: - case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: - val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM); - break; - case SIM_SH_TBR_REGNUM: - val = TBR; - break; - case SIM_SH_IBNR_REGNUM: - val = IBNR; - break; - case SIM_SH_IBCR_REGNUM: - val = IBCR; - break; - case SIM_SH_BANK_REGNUM: - /* This is a pseudo-register maintained just for gdb. - It tells us what register bank gdb would like to read/write. */ - val = gdb_bank_number; - break; - case SIM_SH_BANK_MACL_REGNUM: - val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL]; - break; - case SIM_SH_BANK_GBR_REGNUM: - val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR]; - break; - case SIM_SH_BANK_PR_REGNUM: - val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR]; - break; - case SIM_SH_BANK_IVN_REGNUM: - val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN]; - break; - case SIM_SH_BANK_MACH_REGNUM: - val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH]; - break; - default: - return 0; - } - * (int *) memory = swap (val); - return -1; -} - -int -sim_trace (sd) - SIM_DESC sd; -{ - tracing = 1; - sim_resume (sd, 0, 0); - tracing = 0; - return 1; -} - -void -sim_stop_reason (sd, reason, sigrc) - SIM_DESC sd; - enum sim_stop *reason; - int *sigrc; -{ - /* The SH simulator uses SIGQUIT to indicate that the program has - exited, so we must check for it here and translate it to exit. */ - if (saved_state.asregs.exception == SIGQUIT) - { - *reason = sim_exited; - *sigrc = saved_state.asregs.regs[5]; - } - else - { - *reason = sim_stopped; - *sigrc = saved_state.asregs.exception; - } -} - -void -sim_info (sd, verbose) - SIM_DESC sd; - int verbose; -{ - double timetaken = - (double) saved_state.asregs.ticks / (double) now_persec (); - double virttime = saved_state.asregs.cycles / 36.0e6; - - callback->printf_filtered (callback, "\n\n# instructions executed %10d\n", - saved_state.asregs.insts); - callback->printf_filtered (callback, "# cycles %10d\n", - saved_state.asregs.cycles); - callback->printf_filtered (callback, "# pipeline stalls %10d\n", - saved_state.asregs.stalls); - callback->printf_filtered (callback, "# misaligned load/store %10d\n", - saved_state.asregs.memstalls); - callback->printf_filtered (callback, "# real time taken %10.4f\n", - timetaken); - callback->printf_filtered (callback, "# virtual time taken %10.4f\n", - virttime); - callback->printf_filtered (callback, "# profiling size %10d\n", - sim_profile_size); - callback->printf_filtered (callback, "# profiling frequency %10d\n", - saved_state.asregs.profile); - callback->printf_filtered (callback, "# profile maxpc %10x\n", - (1 << sim_profile_size) << PROFILE_SHIFT); - - if (timetaken != 0) - { - callback->printf_filtered (callback, "# cycles/second %10d\n", - (int) (saved_state.asregs.cycles / timetaken)); - callback->printf_filtered (callback, "# simulation ratio %10.4f\n", - virttime / timetaken); - } -} - -void -sim_set_profile (n) - int n; -{ - saved_state.asregs.profile = n; -} - -void -sim_set_profile_size (n) - int n; -{ - sim_profile_size = n; -} - -SIM_DESC -sim_open (kind, cb, abfd, argv) - SIM_OPEN_KIND kind; - host_callback *cb; - struct bfd *abfd; - char **argv; -{ - char **p; - int endian_set = 0; - int i; - union - { - int i; - short s[2]; - char c[4]; - } - mem_word; - - sim_kind = kind; - myname = argv[0]; - callback = cb; - - for (p = argv + 1; *p != NULL; ++p) - { - if (strcmp (*p, "-E") == 0) - { - ++p; - if (*p == NULL) - { - /* FIXME: This doesn't use stderr, but then the rest of the - file doesn't either. */ - callback->printf_filtered (callback, "Missing argument to `-E'.\n"); - return 0; - } - target_little_endian = strcmp (*p, "big") != 0; - endian_set = 1; - } - else if (isdigit (**p)) - parse_and_set_memory_size (*p); - } - - if (abfd != NULL && ! endian_set) - target_little_endian = ! bfd_big_endian (abfd); - - if (abfd) - init_dsp (abfd); - - for (i = 4; (i -= 2) >= 0; ) - mem_word.s[i >> 1] = i; - global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff; - - for (i = 4; --i >= 0; ) - mem_word.c[i] = i; - endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff; - - /* fudge our descriptor for now */ - return (SIM_DESC) 1; -} - -static void -parse_and_set_memory_size (str) - char *str; -{ - int n; - - n = strtol (str, NULL, 10); - if (n > 0 && n <= 24) - sim_memory_size = n; - else - callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n); -} - -void -sim_close (sd, quitting) - SIM_DESC sd; - int quitting; -{ - /* nothing to do */ -} - -SIM_RC -sim_load (sd, prog, abfd, from_tty) - SIM_DESC sd; - char *prog; - bfd *abfd; - int from_tty; -{ - extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ - bfd *prog_bfd; - - prog_bfd = sim_load_file (sd, myname, callback, prog, abfd, - sim_kind == SIM_OPEN_DEBUG, - 0, sim_write); - - /* Set the bfd machine type. */ - if (prog_bfd) - saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd); - else if (abfd) - saved_state.asregs.bfd_mach = bfd_get_mach (abfd); - else - saved_state.asregs.bfd_mach = 0; - - if (prog_bfd == NULL) - return SIM_RC_FAIL; - if (abfd == NULL) - bfd_close (prog_bfd); - return SIM_RC_OK; -} - -SIM_RC -sim_create_inferior (sd, prog_bfd, argv, env) - SIM_DESC sd; - struct bfd *prog_bfd; - char **argv; - char **env; -{ - /* Clear the registers. */ - memset (&saved_state, 0, - (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state); - - /* Set the PC. */ - if (prog_bfd != NULL) - saved_state.asregs.pc = bfd_get_start_address (prog_bfd); - - /* Set the bfd machine type. */ - if (prog_bfd != NULL) - saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd); - - /* Record the program's arguments. */ - prog_argv = argv; - - return SIM_RC_OK; -} - -void -sim_do_command (sd, cmd) - SIM_DESC sd; - char *cmd; -{ - char *sms_cmd = "set-memory-size"; - int cmdsize; - - if (cmd == NULL || *cmd == '\0') - { - cmd = "help"; - } - - cmdsize = strlen (sms_cmd); - if (strncmp (cmd, sms_cmd, cmdsize) == 0 - && strchr (" \t", cmd[cmdsize]) != NULL) - { - parse_and_set_memory_size (cmd + cmdsize + 1); - } - else if (strcmp (cmd, "help") == 0) - { - (callback->printf_filtered) (callback, - "List of SH simulator commands:\n\n"); - (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n"); - (callback->printf_filtered) (callback, "\n"); - } - else - { - (callback->printf_filtered) (callback, "Error: \"%s\" is not a valid SH simulator command.\n", cmd); - } -} - -void -sim_set_callbacks (p) - host_callback *p; -{ - callback = p; -} diff --git a/sim/sh/syscall.h b/sim/sh/syscall.h deleted file mode 100644 index aebce2c..0000000 --- a/sim/sh/syscall.h +++ /dev/null @@ -1,36 +0,0 @@ - -/* !!! DANGER !!! - This was copied from newlib. */ - - -#define SYS_exit 1 -#define SYS_fork 2 -#define SYS_read 3 -#define SYS_write 4 -#define SYS_open 5 -#define SYS_close 6 -#define SYS_wait4 7 -#define SYS_creat 8 -#define SYS_link 9 -#define SYS_unlink 10 -#define SYS_execv 11 -#define SYS_chdir 12 -#define SYS_mknod 14 -#define SYS_chmod 15 -#define SYS_chown 16 -#define SYS_lseek 19 -#define SYS_getpid 20 -#define SYS_isatty 21 -#define SYS_fstat 22 -#define SYS_time 23 -#define SYS_ARG 24 -#define SYS_stat 38 -#define SYS_pipe 42 -#define SYS_execve 59 -#define SYS_truncate 129 -#define SYS_ftruncate 130 -#define SYS_argc 172 -#define SYS_argnlen 173 -#define SYS_argn 174 -#define SYS_utime 201 /* not really a system call */ -#define SYS_wait 202 /* nor is this */ diff --git a/sim/sh/tconfig.in b/sim/sh/tconfig.in deleted file mode 100644 index c5ec4fa..0000000 --- a/sim/sh/tconfig.in +++ /dev/null @@ -1,17 +0,0 @@ -/* sh target config file */ - -/* Define this if the simulator supports profiling. - See the mips simulator for an example. - This enables the `-p foo' and `-s bar' options. - The target is required to provide sim_set_profile{,_size}. */ -/* #define SIM_HAVE_PROFILE */ - -/* Define this if the simulator uses an instruction cache. - See the h8/300 simulator for an example. - This enables the `-c size' option to set the size of the cache. - The target is required to provide sim_set_simcache_size. */ -/* #define SIM_HAVE_SIMCACHE */ - -/* Define this if the target cpu is bi-endian - and the simulator supports it. */ -#define SIM_HAVE_BIENDIAN |