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-rw-r--r--sim/or1k/arch.c2
-rw-r--r--sim/or1k/arch.h2
-rw-r--r--sim/or1k/cpu.c34
-rw-r--r--sim/or1k/cpu.h16
-rw-r--r--sim/or1k/cpuall.h2
-rw-r--r--sim/or1k/decode.c2
-rw-r--r--sim/or1k/decode.h2
-rw-r--r--sim/or1k/local.mk2
-rw-r--r--sim/or1k/mloop.in2
-rw-r--r--sim/or1k/model.c2
-rw-r--r--sim/or1k/or1k-sim.h2
-rw-r--r--sim/or1k/or1k.c6
-rw-r--r--sim/or1k/sem-switch.c2
-rw-r--r--sim/or1k/sem.c2
-rw-r--r--sim/or1k/sim-if.c2
-rw-r--r--sim/or1k/sim-main.h2
-rw-r--r--sim/or1k/traps.c4
17 files changed, 69 insertions, 17 deletions
diff --git a/sim/or1k/arch.c b/sim/or1k/arch.c
index 0530fa7..22293d5 100644
--- a/sim/or1k/arch.c
+++ b/sim/or1k/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/arch.h b/sim/or1k/arch.h
index 4a4007b..1e96fd5 100644
--- a/sim/or1k/arch.h
+++ b/sim/or1k/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/cpu.c b/sim/or1k/cpu.c
index ea37481..14e43cc 100644
--- a/sim/or1k/cpu.c
+++ b/sim/or1k/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -1100,6 +1100,38 @@ or1k32bf_h_sys_esr15_set (SIM_CPU *current_cpu, USI newval)
SET_H_SYS_ESR15 (newval);
}
+/* Get the value of h-sys-coreid. */
+
+USI
+or1k32bf_h_sys_coreid_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_COREID ();
+}
+
+/* Set a value for h-sys-coreid. */
+
+void
+or1k32bf_h_sys_coreid_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_COREID (newval);
+}
+
+/* Get the value of h-sys-numcores. */
+
+USI
+or1k32bf_h_sys_numcores_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_NUMCORES ();
+}
+
+/* Set a value for h-sys-numcores. */
+
+void
+or1k32bf_h_sys_numcores_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_NUMCORES (newval);
+}
+
/* Get the value of h-sys-gpr0. */
USI
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index 1fd3305..ab2c062 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -408,6 +408,16 @@ SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR14), (x));\
do { \
SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR15), (x));\
;} while (0)
+#define GET_H_SYS_COREID() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_COREID))
+#define SET_H_SYS_COREID(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_COREID), (x));\
+;} while (0)
+#define GET_H_SYS_NUMCORES() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NUMCORES))
+#define SET_H_SYS_NUMCORES(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NUMCORES), (x));\
+;} while (0)
#define GET_H_SYS_GPR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))
#define SET_H_SYS_GPR0(x) \
do { \
@@ -3379,6 +3389,10 @@ USI or1k32bf_h_sys_esr14_get (SIM_CPU *);
void or1k32bf_h_sys_esr14_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_esr15_get (SIM_CPU *);
void or1k32bf_h_sys_esr15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_coreid_get (SIM_CPU *);
+void or1k32bf_h_sys_coreid_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_numcores_get (SIM_CPU *);
+void or1k32bf_h_sys_numcores_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_gpr0_get (SIM_CPU *);
void or1k32bf_h_sys_gpr0_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_gpr1_get (SIM_CPU *);
diff --git a/sim/or1k/cpuall.h b/sim/or1k/cpuall.h
index e899957..4879390 100644
--- a/sim/or1k/cpuall.h
+++ b/sim/or1k/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c
index 3919fa5..dd28b6a 100644
--- a/sim/or1k/decode.c
+++ b/sim/or1k/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/decode.h b/sim/or1k/decode.h
index 0ef83fc..c1d6a14 100644
--- a/sim/or1k/decode.h
+++ b/sim/or1k/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/local.mk b/sim/or1k/local.mk
index b97f96a..402caac 100644
--- a/sim/or1k/local.mk
+++ b/sim/or1k/local.mk
@@ -1,6 +1,6 @@
## See sim/Makefile.am
##
-## Copyright (C) 2017-2024 Free Software Foundation, Inc.
+## Copyright (C) 2017-2025 Free Software Foundation, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
diff --git a/sim/or1k/mloop.in b/sim/or1k/mloop.in
index 4fead61..2afd2a8 100644
--- a/sim/or1k/mloop.in
+++ b/sim/or1k/mloop.in
@@ -1,6 +1,6 @@
# Simulator main loop for or1k. -*- C -*-
#
-# Copyright (C) 2017-2024 Free Software Foundation, Inc.
+# Copyright (C) 2017-2025 Free Software Foundation, Inc.
#
# This file is part of the GNU Simulators.
#
diff --git a/sim/or1k/model.c b/sim/or1k/model.c
index 512b897..61fad33 100644
--- a/sim/or1k/model.c
+++ b/sim/or1k/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h
index ff0c96e..9a80cfe 100644
--- a/sim/or1k/or1k-sim.h
+++ b/sim/or1k/or1k-sim.h
@@ -1,5 +1,5 @@
/* OpenRISC simulator support code header
- Copyright (C) 2017-2024 Free Software Foundation, Inc.
+ Copyright (C) 2017-2025 Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger.
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index 5882ba5..73ab6f0 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -1,5 +1,5 @@
/* OpenRISC simulator support code
- Copyright (C) 2017-2024 Free Software Foundation, Inc.
+ Copyright (C) 2017-2025 Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger.
@@ -206,6 +206,10 @@ or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
/* Clear the floating point control status register. */
SET_H_SYS_FPCSR (0);
+
+ /* Set this as the one and only core. */
+ SET_H_SYS_NUMCORES (1);
+ SET_H_SYS_COREID (0);
}
void
diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
index 404c6d9..129a897 100644
--- a/sim/or1k/sem-switch.c
+++ b/sim/or1k/sem-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/sem.c b/sim/or1k/sem.c
index c913ee4..9ce94f6 100644
--- a/sim/or1k/sem.c
+++ b/sim/or1k/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright (C) 1996-2025 Free Software Foundation, Inc.
This file is part of the GNU simulators.
diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c
index a53daf6..2b075b2 100644
--- a/sim/or1k/sim-if.c
+++ b/sim/or1k/sim-if.c
@@ -1,5 +1,5 @@
/* Main simulator entry points specific to the OR1K.
- Copyright (C) 2017-2024 Free Software Foundation, Inc.
+ Copyright (C) 2017-2025 Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger.
diff --git a/sim/or1k/sim-main.h b/sim/or1k/sim-main.h
index f45bd62..de0113d 100644
--- a/sim/or1k/sim-main.h
+++ b/sim/or1k/sim-main.h
@@ -1,5 +1,5 @@
/* OpenRISC simulator main header
- Copyright (C) 2017-2024 Free Software Foundation, Inc.
+ Copyright (C) 2017-2025 Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger.
diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c
index be354eb..d1113ac 100644
--- a/sim/or1k/traps.c
+++ b/sim/or1k/traps.c
@@ -1,5 +1,5 @@
/* OpenRISC exception, interrupts, syscall and trap support
- Copyright (C) 2017-2024 Free Software Foundation, Inc.
+ Copyright (C) 2017-2025 Free Software Foundation, Inc.
This file is part of GDB, the GNU debugger.
@@ -224,6 +224,8 @@ or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
case SPR_ADDR (SYS, PPC):
case SPR_ADDR (SYS, FPCSR):
case SPR_ADDR (SYS, EPCR0):
+ case SPR_ADDR (SYS, COREID):
+ case SPR_ADDR (SYS, NUMCORES):
case SPR_ADDR (MAC, MACLO):
case SPR_ADDR (MAC, MACHI):
break;
generated by cgit v1.1 at 2025-07-01 12:37:17 +0000