diff options
Diffstat (limited to 'sim/or1k/model.c')
-rw-r--r-- | sim/or1k/model.c | 186 |
1 files changed, 178 insertions, 8 deletions
diff --git a/sim/or1k/model.c b/sim/or1k/model.c index 35c6479..bf6b00b 100644 --- a/sim/or1k/model.c +++ b/sim/or1k/model.c @@ -51,6 +51,22 @@ model_or1200_l_j (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_adrp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_adrp.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_jal (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_j.f @@ -261,7 +277,7 @@ model_or1200_l_movhi (SIM_CPU *current_cpu, void *sem_arg) static int model_or1200_l_macrc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -723,6 +739,22 @@ model_or1200_l_mul (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_muld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_mulu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -739,6 +771,22 @@ model_or1200_l_mulu (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_muldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_div (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1347,6 +1395,38 @@ model_or1200_l_mac (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_lwz.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_l_macu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1363,9 +1443,9 @@ model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_l_msbu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1763,6 +1843,22 @@ model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_adrp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_adrp.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_jal (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_j.f @@ -1973,7 +2069,7 @@ model_or1200nd_l_movhi (SIM_CPU *current_cpu, void *sem_arg) static int model_or1200nd_l_macrc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2435,6 +2531,22 @@ model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_muld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -2451,6 +2563,22 @@ model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_muldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3059,6 +3187,38 @@ model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_lwz.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_l_macu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3075,9 +3235,9 @@ model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_l_msbu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3471,6 +3631,7 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_J, model_or1200_l_j, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_ADRP, model_or1200_l_adrp, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JAL, model_or1200_l_jal, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JR, model_or1200_l_jr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JALR, model_or1200_l_jalr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3513,7 +3674,9 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_L_SUB, model_or1200_l_sub, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_ADDC, model_or1200_l_addc, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MUL, model_or1200_l_mul, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULD, model_or1200_l_muld, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MULU, model_or1200_l_mulu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULDU, model_or1200_l_muldu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIV, model_or1200_l_div, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIVU, model_or1200_l_divu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_FF1, model_or1200_l_ff1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3552,8 +3715,10 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_L_SFNE, model_or1200_l_sfne, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_SFNEI, model_or1200_l_sfnei, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MAC, model_or1200_l_mac, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_L_MSB, model_or1200_l_msb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MACI, model_or1200_l_maci, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MACU, model_or1200_l_macu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSB, model_or1200_l_msb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSBU, model_or1200_l_msbu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST1, model_or1200_l_cust1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST2, model_or1200_l_cust2, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST3, model_or1200_l_cust3, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3589,6 +3754,7 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_J, model_or1200nd_l_j, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_ADRP, model_or1200nd_l_adrp, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JAL, model_or1200nd_l_jal, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JR, model_or1200nd_l_jr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JALR, model_or1200nd_l_jalr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, @@ -3631,7 +3797,9 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_L_SUB, model_or1200nd_l_sub, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_ADDC, model_or1200nd_l_addc, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MUL, model_or1200nd_l_mul, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULD, model_or1200nd_l_muld, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MULU, model_or1200nd_l_mulu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULDU, model_or1200nd_l_muldu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIV, model_or1200nd_l_div, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIVU, model_or1200nd_l_divu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_FF1, model_or1200nd_l_ff1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, @@ -3670,8 +3838,10 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_L_SFNE, model_or1200nd_l_sfne, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_SFNEI, model_or1200nd_l_sfnei, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MAC, model_or1200nd_l_mac, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_L_MSB, model_or1200nd_l_msb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MACI, model_or1200nd_l_maci, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MACU, model_or1200nd_l_macu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSB, model_or1200nd_l_msb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSBU, model_or1200nd_l_msbu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST1, model_or1200nd_l_cust1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST2, model_or1200nd_l_cust2, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST3, model_or1200nd_l_cust3, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, |