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-rw-r--r--sim/erc32/README.erc322
-rw-r--r--sim/erc32/README.gdb2
-rw-r--r--sim/erc32/erc32.c2
-rw-r--r--sim/erc32/exec.c4
-rw-r--r--sim/erc32/float.c4
-rw-r--r--sim/erc32/func.c2
-rw-r--r--sim/erc32/help.c2
-rw-r--r--sim/erc32/interf.c2
-rw-r--r--sim/erc32/local.mk2
-rw-r--r--sim/erc32/sis.c2
-rw-r--r--sim/erc32/sis.h4
-rw-r--r--sim/erc32/startsim2
12 files changed, 15 insertions, 15 deletions
diff --git a/sim/erc32/README.erc32 b/sim/erc32/README.erc32
index f413599..45ae22b 100644
--- a/sim/erc32/README.erc32
+++ b/sim/erc32/README.erc32
@@ -59,7 +59,7 @@ register is updated accordingly. Implemeted registers are:
- Breakpoint register (0x01f800c4, write-only)
- Watchpoint register (0x01f800c8, write-only)
- System fault status register (0x01f800a0, read-write)
-- Firts failing address register (0x01f800a4, read-write)
+- First failing address register (0x01f800a4, read-write)
1.5 Memory interface
diff --git a/sim/erc32/README.gdb b/sim/erc32/README.gdb
index 619fcb3..cfad07f 100644
--- a/sim/erc32/README.gdb
+++ b/sim/erc32/README.gdb
@@ -45,7 +45,7 @@ For info on supported ERC32 functionality, see README.sis.
The GDB load command loads an aout file into the simulator
memory with the data section starting directly after the text
-section regardless of wich start address was specified for the data
+section regardless of which start address was specified for the data
at link time! This means that your applications either has to include
a routine that initialise the data segment at the proper address or
link with the data placed directly after the text section.
diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c
index 25037ce..cf9e084 100644
--- a/sim/erc32/erc32.c
+++ b/sim/erc32/erc32.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index c84371f..9b03f0d 100644
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
@@ -314,7 +314,7 @@ mul64 (uint32_t n1, uint32_t n2, uint32_t *result_hi, uint32_t *result_lo, int m
hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
+ to propagate the carries from the additions: */
reg_lo = add32 (lo, (mid1 << 16), &carry);
reg_hi = carry;
reg_lo = add32 (reg_lo, (mid2 << 16), &carry);
diff --git a/sim/erc32/float.c b/sim/erc32/float.c
index 2b851ca..99e24a6 100644
--- a/sim/erc32/float.c
+++ b/sim/erc32/float.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
@@ -20,7 +20,7 @@
FPU. IEEE trap handling is done as follows:
1. In the host, all IEEE traps are masked
2. After each simulated FPU instruction, check if any exception
- occured by reading the exception bits from the host FPU status
+ occurred by reading the exception bits from the host FPU status
register (get_accex()).
3. Propagate any exceptions to the simulated FSR.
4. Clear host exception bits.
diff --git a/sim/erc32/func.c b/sim/erc32/func.c
index 80f416d..0c4f75c 100644
--- a/sim/erc32/func.c
+++ b/sim/erc32/func.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
diff --git a/sim/erc32/help.c b/sim/erc32/help.c
index 909275c..0eb4ce7 100644
--- a/sim/erc32/help.c
+++ b/sim/erc32/help.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c
index 98b8a65..fb4edaa 100644
--- a/sim/erc32/interf.c
+++ b/sim/erc32/interf.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
diff --git a/sim/erc32/local.mk b/sim/erc32/local.mk
index 1e217a8..9ae4c8c 100644
--- a/sim/erc32/local.mk
+++ b/sim/erc32/local.mk
@@ -1,6 +1,6 @@
## See sim/Makefile.am
##
-## Copyright (C) 1993-2024 Free Software Foundation, Inc.
+## Copyright (C) 1993-2025 Free Software Foundation, Inc.
## Written by Cygnus Support
## Modified by J.Gaisler ESA/ESTEC
##
diff --git a/sim/erc32/sis.c b/sim/erc32/sis.c
index 279427d..b53eca4 100644
--- a/sim/erc32/sis.c
+++ b/sim/erc32/sis.c
@@ -1,6 +1,6 @@
/* This file is part of SIS (SPARC instruction simulator)
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
+ Copyright (C) 1995-2025 Free Software Foundation, Inc.
Contributed by Jiri Gaisler, European Space Agency
This program is free software; you can redistribute it and/or modify
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index cf44ddf..6777f69 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1995-2024 Free Software Foundation, Inc.
+/* Copyright (C) 1995-2025 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -114,7 +114,7 @@ struct pstate {
uint64_t pwdtime; /* Cycles in power-down mode */
uint64_t nstore; /* Number of load instructions */
uint64_t nload; /* Number of store instructions */
- uint64_t nannul; /* Number of annuled instructions */
+ uint64_t nannul; /* Number of annulled instructions */
uint64_t nbranch; /* Number of branch instructions */
uint32_t ildreg; /* Destination of last load instruction */
uint64_t ildtime; /* Last time point for load dependency */
diff --git a/sim/erc32/startsim b/sim/erc32/startsim
index 435c5b6..78dad84 100644
--- a/sim/erc32/startsim
+++ b/sim/erc32/startsim
@@ -1,4 +1,4 @@
-# Copyright (C) 1996-2024 Free Software Foundation, Inc.
+# Copyright (C) 1996-2025 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
generated by cgit v1.1 at 2025-07-02 01:04:58 +0000