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-rw-r--r--sim/aarch64/ChangeLog4
-rw-r--r--sim/aarch64/simulator.c20
2 files changed, 14 insertions, 10 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index 2a21fc3..7d00621 100644
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -1,5 +1,9 @@
2017-02-14 Jim Wilson <jim.wilson@linaro.org>
+ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
+ 2. Move test_false if inside loop. Fix logic for computing result
+ stored to vd.
+
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 403edb7..13a2b1f 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -4085,17 +4085,17 @@ do_vec_bit (sim_cpu *cpu)
NYI_assert (15, 10, 0x07);
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
- if (test_false)
- {
- for (i = 0; i < (full ? 16 : 8); i++)
- if (aarch64_get_vec_u32 (cpu, vn, i) == 0)
- aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i));
- }
- else
+ for (i = 0; i < (full ? 4 : 2); i++)
{
- for (i = 0; i < (full ? 16 : 8); i++)
- if (aarch64_get_vec_u32 (cpu, vn, i) != 0)
- aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i));
+ uint32_t vd_val = aarch64_get_vec_u32 (cpu, vd, i);
+ uint32_t vn_val = aarch64_get_vec_u32 (cpu, vn, i);
+ uint32_t vm_val = aarch64_get_vec_u32 (cpu, vm, i);
+ if (test_false)
+ aarch64_set_vec_u32 (cpu, vd, i,
+ (vd_val & vm_val) | (vn_val & ~vm_val));
+ else
+ aarch64_set_vec_u32 (cpu, vd, i,
+ (vd_val & ~vm_val) | (vn_val & vm_val));
}
}