diff options
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index c7be6d0..be19aea 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -752,6 +752,13 @@ QLF2(V_4S , V_4S ), \ } +/* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ +#define QL_V2SAMEH \ +{ \ + QLF2 (V_4H, V_4H), \ + QLF2 (V_8H, V_8H), \ +} + /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ #define QL_V2SAMEB \ { \ @@ -1509,21 +1516,51 @@ struct aarch64_opcode aarch64_opcode_table[] = {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC}, {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC}, {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, + {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ}, {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, + {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ}, {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, + {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ}, {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ}, {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ}, {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ}, {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ}, @@ -1542,23 +1579,51 @@ struct aarch64_opcode aarch64_opcode_table[] = {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0}, {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0}, {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS}, {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS}, {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ}, {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, + {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ}, {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ}, + {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ}, {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ}, {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ}, + {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16, + OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ}, /* AdvSIMD ZIP/UZP/TRN. */ {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ}, |