diff options
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 18 |
2 files changed, 13 insertions, 9 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index e42477d..d0b5daf 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-07-28 Alan Modra <amodra@gmail.com> + + * ld-powerpc/elfv2so.d: Update. + 2015-07-27 H.J. Lu <hongjiu.lu@intel.com> * config/default.exp (NOPIE_CFLAGS): New. diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 906b375..d6f0b7d 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -7,33 +7,33 @@ Disassembly of section \.text: -0+320 <.*\.plt_call\.f4>: +0+300 <.*\.plt_call\.f4>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+330 <.*\.plt_call\.f3>: +0+310 <.*\.plt_call\.f3>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+340 <.*\.plt_call\.f2>: +0+320 <.*\.plt_call\.f2>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+350 <.*\.plt_call\.f1>: +0+330 <.*\.plt_call\.f1>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) .*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr -0+360 <f1>: +0+340 <f1>: .*: (3c 4c 00 02|02 00 4c 3c) addis r2,r12,2 -.*: (38 42 82 a0|a0 82 42 38) addi r2,r2,-32096 +.*: (38 42 82 c0|c0 82 42 38) addi r2,r2,-32064 .*: (7c 08 02 a6|a6 02 08 7c) mflr r0 .*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\) .*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\) @@ -50,10 +50,10 @@ Disassembly of section \.text: .*: (38 21 00 20|20 00 21 38) addi r1,r1,32 .*: (7c 08 03 a6|a6 03 08 7c) mtlr r0 .*: (4e 80 00 20|20 00 80 4e) blr -.*: (00 00 00 00|60 02 01 00) .* -.*: (00 01 02 60|00 00 00 00) .* +.*: (00 00 00 00|80 02 01 00) .* +.*: (00 01 02 80|00 00 00 00) .* -0+3b0 <__glink_PLTresolve>: +0+390 <__glink_PLTresolve>: .*: (7c 08 02 a6|a6 02 08 7c) mflr r0 .*: (42 9f 00 05|05 00 9f 42) bcl .* .*: (7d 68 02 a6|a6 02 68 7d) mflr r11 |