diff options
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/ChangeLog | 14 | ||||
| -rw-r--r-- | ld/Makefile.am | 13 | ||||
| -rw-r--r-- | ld/Makefile.in | 15 | ||||
| -rw-r--r-- | ld/NEWS | 2 | ||||
| -rw-r--r-- | ld/configure.tgt | 6 | ||||
| -rw-r--r-- | ld/emulparams/elf32lriscv-defs.sh | 42 | ||||
| -rw-r--r-- | ld/emulparams/elf32lriscv.sh | 2 | ||||
| -rw-r--r-- | ld/emulparams/elf64lriscv-defs.sh | 13 | ||||
| -rw-r--r-- | ld/emulparams/elf64lriscv.sh | 2 | ||||
| -rw-r--r-- | ld/emultempl/riscvelf.em | 68 |
10 files changed, 176 insertions, 1 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index dacdf8e..a2fb4a4 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,17 @@ +2016-11-01 Palmer Dabbelt <palmer@dabbelt.com> + Andrew Waterman <andrew@sifive.com> + + Add support for RISC-V architecture. + * Makefile.am: Add riscv files. + * Makefile.in: Regenerate. + * NEWS: Mention the support for this target. + * configure.tgt: Add riscv entries. + * emulparams/elf32lriscv-defs.sh: New file. + * emulparams/elf32lriscv.sh: New file. + * emulparams/elf64lriscv-defs.sh: New file. + * emulparams/elf64lriscv.sh: New file. + * emultempl/riscvelf.em: New file. + 2016-10-31 Thomas Preud'homme <thomas.preudhomme@arm.com> * ldmain.c (add_archive_element): Initialize input->header.type. diff --git a/ld/Makefile.am b/ld/Makefile.am index 1a7fc3f..9b3de72 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -278,6 +278,7 @@ ALL_EMULATION_SOURCES = \ eelf32ppcsim.c \ eelf32ppcvxworks.c \ eelf32ppcwindiss.c \ + eelf32lriscv.c \ eelf32rl78.c \ eelf32rx.c \ eelf32tilegx.c \ @@ -494,6 +495,7 @@ ALL_64_EMULATION_SOURCES = \ eelf64btsmip_fbsd.c \ eelf64hppa.c \ eelf64lppc.c \ + eelf64lriscv.c \ eelf64ltsmip.c \ eelf64ltsmip_fbsd.c \ eelf64mmix.c \ @@ -1165,6 +1167,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ @@ -1959,6 +1966,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ + $(srcdir)/emulparams/elf64lriscv-defs.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ diff --git a/ld/Makefile.in b/ld/Makefile.in index 3511e5f..f87408e 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -647,6 +647,7 @@ ALL_EMULATION_SOURCES = \ eelf32ppcsim.c \ eelf32ppcvxworks.c \ eelf32ppcwindiss.c \ + eelf32lriscv.c \ eelf32rl78.c \ eelf32rx.c \ eelf32tilegx.c \ @@ -862,6 +863,7 @@ ALL_64_EMULATION_SOURCES = \ eelf64btsmip_fbsd.c \ eelf64hppa.c \ eelf64lppc.c \ + eelf64lriscv.c \ eelf64ltsmip.c \ eelf64ltsmip_fbsd.c \ eelf64mmix.c \ @@ -1282,6 +1284,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmip_fbsd.Po@am__quote@ @@ -1335,6 +1338,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@ @@ -2754,6 +2758,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ @@ -3548,6 +3557,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ ldemul-list.h \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +eelf64lriscv.c: $(srcdir)/emulparams/elf64lriscv.sh \ + $(srcdir)/emulparams/elf64lriscv-defs.sh \ + $(srcdir)/emulparams/elf32lriscv-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/riscvelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} + eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ @@ -1,6 +1,6 @@ -*- text -*- -Changes in 2.28: +* Add support for the RISC-V architecture. * The command line option --no-eh-frame-hdr can now be used in ELF based linkers to disable the automatic generation of .eh_frame_hdr sections. diff --git a/ld/configure.tgt b/ld/configure.tgt index 6f3cd4f..c196e68 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -679,6 +679,12 @@ powerpc-*-aix*) targ_emul=aixppc ;; powerpc-*-beos*) targ_emul=aixppc ;; powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;; powerpc-*-lynxos*) targ_emul=ppclynx ;; +riscv32*-*-*) targ_emul=elf32lriscv + targ_extra_emuls="elf64lriscv" + targ_extra_libpath=$targ_extra_emuls ;; +riscv64*-*-*) targ_emul=elf64lriscv + targ_extra_emuls="elf32lriscv" + targ_extra_libpath=$targ_extra_emuls ;; rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;; rs6000-*-aix*) targ_emul=aixrs6 ;; diff --git a/ld/emulparams/elf32lriscv-defs.sh b/ld/emulparams/elf32lriscv-defs.sh new file mode 100644 index 0000000..0e4b723 --- /dev/null +++ b/ld/emulparams/elf32lriscv-defs.sh @@ -0,0 +1,42 @@ +# This is an ELF platform. +SCRIPT_NAME=elf +ARCH=riscv +NO_REL_RELOCS=yes + +TEMPLATE_NAME=elf32 +EXTRA_EM_FILE=riscvelf + +ELFSIZE=32 + +if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then + case " $EMULATION_LIBPATH " in + *" ${EMULATION_NAME} "*) + NATIVE=yes + ;; + esac +fi + +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + +TEXT_START_ADDR=0x10000 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +SDATA_START_SYMBOLS="_gp = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)" + +# Place the data section before text section. This enables more compact +# global variable access for RVC code via linker relaxation. +INITIAL_READONLY_SECTIONS=" + .data : { *(.data) *(.data.*) *(.gnu.linkonce.d.*) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .srodata : { ${SDATA_START_SYMBOLS} } + .sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) } + .sbss : { *(.dynsbss) *(.sbss .sbss.* .gnu.linkonce.sb.*) } + .bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) } + . = ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1));" +INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}" +INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}" + +SDATA_START_SYMBOLS="${CREATE_PIE+${SDATA_START_SYMBOLS}}" diff --git a/ld/emulparams/elf32lriscv.sh b/ld/emulparams/elf32lriscv.sh new file mode 100644 index 0000000..aac08e7 --- /dev/null +++ b/ld/emulparams/elf32lriscv.sh @@ -0,0 +1,2 @@ +. ${srcdir}/emulparams/elf32lriscv-defs.sh +OUTPUT_FORMAT="elf32-littleriscv" diff --git a/ld/emulparams/elf64lriscv-defs.sh b/ld/emulparams/elf64lriscv-defs.sh new file mode 100644 index 0000000..6308714 --- /dev/null +++ b/ld/emulparams/elf64lriscv-defs.sh @@ -0,0 +1,13 @@ +. ${srcdir}/emulparams/elf32lriscv-defs.sh +ELFSIZE=64 + +# Look for 64 bit target libraries in /lib64, /usr/lib64 etc., first +# on Linux. +case "$target" in + riscv64*-linux*) + case "$EMULATION_NAME" in + *64*) + LIBPATH_SUFFIX=64 ;; + esac + ;; +esac diff --git a/ld/emulparams/elf64lriscv.sh b/ld/emulparams/elf64lriscv.sh new file mode 100644 index 0000000..3a6a652 --- /dev/null +++ b/ld/emulparams/elf64lriscv.sh @@ -0,0 +1,2 @@ +. ${srcdir}/emulparams/elf64lriscv-defs.sh +OUTPUT_FORMAT="elf64-littleriscv" diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em new file mode 100644 index 0000000..027145f --- /dev/null +++ b/ld/emultempl/riscvelf.em @@ -0,0 +1,68 @@ +# This shell script emits a C file. -*- C -*- +# Copyright 2004, 2006, 2007, 2008, 2016 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +fragment <<EOF + +#include "ldmain.h" +#include "ldctor.h" +#include "elf/riscv.h" +#include "elfxx-riscv.h" + +static void +riscv_elf_before_allocation (void) +{ + gld${EMULATION_NAME}_before_allocation (); + + if (link_info.discard == discard_sec_merge) + link_info.discard = discard_l; + + /* We always need at least some relaxation to handle code alignment. */ + if (RELAXATION_DISABLED_BY_USER) + TARGET_ENABLE_RELAXATION; + else + ENABLE_RELAXATION; + + link_info.relax_pass = 2; +} + +static void +gld${EMULATION_NAME}_after_allocation (void) +{ + int need_layout = 0; + + /* Don't attempt to discard unused .eh_frame sections until the final link, + as we can't reliably tell if they're used until after relaxation. */ + if (!bfd_link_relocatable (&link_info)) + { + need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info); + if (need_layout < 0) + { + einfo ("%X%P: .eh_frame/.stab edit: %E\n"); + return; + } + } + + gld${EMULATION_NAME}_map_segments (need_layout); +} + +EOF + +LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation |