diff options
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/ChangeLog | 6 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2exe.d | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 12 |
3 files changed, 13 insertions, 7 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index e5c85e1..6dcfe30 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,9 @@ +2019-06-23 Alan Modra <amodra@gmail.com> + + PR 24704 + * testsuite/ld-powerpc/elfv2exe.d: Update. + * testsuite/ld-powerpc/elfv2so.d: Update. + 2019-06-14 Szabolcs Nagy <szabolcs.nagy@arm.com> * testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23. diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d index 769f846..0ccfcbf 100644 --- a/ld/testsuite/ld-powerpc/elfv2exe.d +++ b/ld/testsuite/ld-powerpc/elfv2exe.d @@ -34,7 +34,7 @@ Disassembly of section \.text: .*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\) .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f2> .*: (60 00 00 00|00 00 00 60) nop -.*: (38 62 80 10|10 80 62 38) addi r3,r2,-32752 +.*: (38 62 80 18|18 80 62 38) addi r3,r2,-32744 .*: (48 .. .. ..|.. .. .. 48) bl 10008888 <f3> .*: (60 00 00 00|00 00 00 60) nop .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f4> diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 081eb49..0162bd0 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -9,35 +9,35 @@ Disassembly of section \.text: .* <.*\.plt_call\.f4>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) +.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f3>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) +.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f5>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 20|20 80 82 e9) ld r12,-32736\(r2\) +.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f1>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) +.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f2>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) +.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. @@ -52,7 +52,7 @@ Disassembly of section \.text: .*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\) .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2> .*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\) -.*: (38 62 80 48|48 80 62 38) addi r3,r2,-32696 +.*: (38 62 80 50|50 80 62 38) addi r3,r2,-32688 .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3> .*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\) .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4> |