diff options
Diffstat (limited to 'ld')
-rw-r--r-- | ld/ChangeLog | 14 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d | 3 | ||||
-rw-r--r-- | ld/testsuite/ld-riscv-elf/call-relax.d | 2 |
11 files changed, 15 insertions, 27 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index 00066c5..5b6805a 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,17 @@ +2020-06-05 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/ld-riscv-elf/attr-merge-arch-01.d: The CSR isn't used, + so ignore the -mpriv-spec setting. + * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. + * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr. + 2020-06-04 H.J. Lu <hongjiu.lu@intel.com> PR ld/26080 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d index 032f964..5baaba4 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d @@ -7,6 +7,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0" - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d index 54a7621..a7d79a1 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d @@ -7,6 +7,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0" - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d index 67f0437..d46dee8 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d @@ -7,6 +7,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d index 5585fac..e4d965a 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d @@ -8,6 +8,4 @@ Attribute Section: riscv File Attributes Tag_RISCV_stack_align: 16-bytes Tag_RISCV_arch: [a-zA-Z0-9_\"].* - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* #... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d index 91011a2..1039930 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d @@ -8,6 +8,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d index 5bdea27..12ca1c4 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d @@ -8,6 +8,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d index ac886fb..e41351d 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d @@ -8,6 +8,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d index dd45f76..ac2a766 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d @@ -7,6 +7,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d index ef0c154..608c05e 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d @@ -8,6 +8,3 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access - Tag_RISCV_priv_spec: [0-9_\"].* - Tag_RISCV_priv_spec_minor: [0-9_\"].* -#... diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d index 46d9c84..597ff67 100644 --- a/ld/testsuite/ld-riscv-elf/call-relax.d +++ b/ld/testsuite/ld-riscv-elf/call-relax.d @@ -3,7 +3,7 @@ #source: call-relax-1.s #source: call-relax-2.s #source: call-relax-3.s -#as: -march=rv32ic +#as: -march=rv32ic -mno-arch-attr #ld: -melf32lriscv #objdump: -d #pass |