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-rw-r--r--ld/testsuite/ChangeLog14
-rw-r--r--ld/testsuite/ld-arm/arm-elf.exp8
-rw-r--r--ld/testsuite/ld-arm/group-relocs-alu-bad.d4
-rw-r--r--ld/testsuite/ld-arm/group-relocs-alu-bad.s20
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldc-bad.d4
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldc-bad.s19
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldr-bad.d4
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldr-bad.s18
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldrs-bad.d4
-rw-r--r--ld/testsuite/ld-arm/group-relocs-ldrs-bad.s17
-rw-r--r--ld/testsuite/ld-arm/group-relocs.d69
-rw-r--r--ld/testsuite/ld-arm/group-relocs.s156
12 files changed, 337 insertions, 0 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index fb9b87d..19c09c9 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
+
+ * ld-arm/group-relocs-alu-bad.d: New test.
+ * ld-arm/group-relocs-alu-bad.s: New test.
+ * ld-arm/group-relocs.d: New test.
+ * ld-arm/group-relocs-ldc-bad.d: New test.
+ * ld-arm/group-relocs-ldc-bad.s: New test.
+ * ld-arm/group-relocs-ldr-bad.d: New test.
+ * ld-arm/group-relocs-ldr-bad.s: New test.
+ * ld-arm/group-relocs-ldrs-bad.d: New test.
+ * ld-arm/group-relocs-ldrs-bad.s: New test.
+ * ld-arm/group-relocs.s: New test.
+ * ld-arm/arm-elf.exp: Wire in new tests.
+
2006-06-14 Richard Sandiford <richard@codesourcery.com>
* ld-m68k/plt1.s, ld-m68k/plt1-empty.s, ld-m68k/plt1.ld: New files.
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index eedbe10..0939506 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -59,6 +59,9 @@ if { ![is_elf_format] || ![istarget "arm*-*-*"] } {
# readelf: Apply readelf options on result. Compare with regex (last arg).
set armelftests {
+ {"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s}
+ {{objdump -Dr group-relocs.d}}
+ "group-relocs"}
{"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
{{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
"arm-lib.so"}
@@ -131,3 +134,8 @@ set armelftests {
}
run_ld_link_tests $armelftests
+run_dump_test "group-relocs-alu-bad"
+run_dump_test "group-relocs-ldr-bad"
+run_dump_test "group-relocs-ldrs-bad"
+run_dump_test "group-relocs-ldc-bad"
+
diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.d b/ld/testsuite/ld-arm/group-relocs-alu-bad.d
new file mode 100644
index 0000000..0346db1
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.d
@@ -0,0 +1,4 @@
+#name: ALU group relocations failure test
+#source: group-relocs-alu-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x9010
+#error: Overflow whilst splitting 0x1010 for group relocation
diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.s b/ld/testsuite/ld-arm/group-relocs-alu-bad.s
new file mode 100644
index 0000000..e644669
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.s
@@ -0,0 +1,20 @@
+@ Test intended to fail for ALU group relocations.
+@
+@ Beware when editing this file: it is carefully crafted so that
+@ a specific PC-relative offset arises.
+
+@ We will place .text at 0x8000.
+
+ .text
+ .globl _start
+
+_start:
+ add r0, r0, #:pc_g0:(bar)
+
+@ We will place the section foo at 0x9004.
+
+ .section foo
+
+bar:
+ mov r0, #0
+
diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.d b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d
new file mode 100644
index 0000000..d4bfb2d
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d
@@ -0,0 +1,4 @@
+#name: LDC group relocations failure test
+#source: group-relocs-ldc-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x118400
+#error: Overflow whilst splitting 0x110400 for group relocation
diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.s b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s
new file mode 100644
index 0000000..611255b
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s
@@ -0,0 +1,19 @@
+@ Test intended to fail for LDC group relocations.
+
+@ We will place .text at 0x8000.
+
+ .text
+ .globl _start
+
+_start:
+ add r0, r0, #:pc_g0_nc:(bar)
+ ldc 0, c0, [r0, #:pc_g1:(bar + 4)]
+
+@ We will place the section foo at 0x118400.
+@ (The relocations above would be OK if it were at 0x118200, for example.)
+
+ .section foo
+
+bar:
+ mov r0, #0
+
diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.d b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d
new file mode 100644
index 0000000..04586af
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d
@@ -0,0 +1,4 @@
+#name: LDR group relocations failure test
+#source: group-relocs-ldr-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x8001000
+#error: .*Overflow whilst splitting 0x8001000 for group relocation.*
diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.s b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s
new file mode 100644
index 0000000..6ab4f3c
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s
@@ -0,0 +1,18 @@
+@ Test intended to fail for LDR group relocations.
+
+@ We will place .text at 0x8000.
+
+ .text
+ .globl _start
+
+_start:
+ add r0, r0, #:sb_g0_nc:(bar)
+ ldr r1, [r0, #:sb_g1:(bar)]
+
+@ We will place the section foo at 0x8001000.
+
+ .section foo
+
+bar:
+ mov r0, #0
+
diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d
new file mode 100644
index 0000000..0520184
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d
@@ -0,0 +1,4 @@
+#name: LDRS group relocations failure test
+#source: group-relocs-ldrs-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x8000100
+#error: Overflow whilst splitting 0x8000100 for group relocation
diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s
new file mode 100644
index 0000000..4480d4a
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s
@@ -0,0 +1,17 @@
+@ Test intended to fail for LDRS group relocations.
+
+@ We will place .text at 0x8000.
+
+ .text
+ .globl _start
+
+_start:
+ add r0, r0, #:sb_g0_nc:(bar)
+ ldrd r2, [r0, #:sb_g1:(bar)]
+
+@ We will place the section foo at 0x8000100.
+
+ .section foo
+
+bar:
+ mov r0, #0
diff --git a/ld/testsuite/ld-arm/group-relocs.d b/ld/testsuite/ld-arm/group-relocs.d
new file mode 100644
index 0000000..d1fdc7d
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs.d
@@ -0,0 +1,69 @@
+
+tmpdir/group-relocs: file format elf32-(little|big)arm
+
+Disassembly of section .text:
+
+00008000 <_start>:
+ 8000: e28f00bc add r0, pc, #188 ; 0xbc
+ 8004: e28f0c6e add r0, pc, #28160 ; 0x6e00
+ 8008: e28000ec add r0, r0, #236 ; 0xec
+ 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000
+ 8010: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8014: e28000e4 add r0, r0, #228 ; 0xe4
+ 8018: e2800000 add r0, r0, #0 ; 0x0
+ 801c: e28f0cee add r0, pc, #60928 ; 0xee00
+ 8020: e28000f0 add r0, r0, #240 ; 0xf0
+ 8024: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 8028: e2800cee add r0, r0, #60928 ; 0xee00
+ 802c: e28000f0 add r0, r0, #240 ; 0xf0
+ 8030: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8034: e59010c0 ldr r1, \[r0, #192\]
+ 8038: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 803c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8040: e59010b8 ldr r1, \[r0, #184\]
+ 8044: e5901000 ldr r1, \[r0\]
+ 8048: e2800cee add r0, r0, #60928 ; 0xee00
+ 804c: e59010f0 ldr r1, \[r0, #240\]
+ 8050: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 8054: e2800cee add r0, r0, #60928 ; 0xee00
+ 8058: e59010f0 ldr r1, \[r0, #240\]
+ 805c: e1c026d0 ldrd r2, \[r0, #96\]
+ 8060: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8064: e1c029d0 ldrd r2, \[r0, #144\]
+ 8068: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 806c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8070: e1c028d8 ldrd r2, \[r0, #136\]
+ 8074: e1c020d0 ldrd r2, \[r0\]
+ 8078: e2800cee add r0, r0, #60928 ; 0xee00
+ 807c: e1c02fd0 ldrd r2, \[r0, #240\]
+ 8080: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 8084: e2800cee add r0, r0, #60928 ; 0xee00
+ 8088: e1c02fd0 ldrd r2, \[r0, #240\]
+ 808c: ed90000c ldc 0, cr0, \[r0, #48\]
+ 8090: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8094: ed900018 ldc 0, cr0, \[r0, #96\]
+ 8098: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 809c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 80a0: ed900016 ldc 0, cr0, \[r0, #88\]
+ 80a4: ed900000 ldc 0, cr0, \[r0\]
+ 80a8: e2800cee add r0, r0, #60928 ; 0xee00
+ 80ac: ed90003c ldc 0, cr0, \[r0, #240\]
+ 80b0: e28008ff add r0, r0, #16711680 ; 0xff0000
+ 80b4: e2800cee add r0, r0, #60928 ; 0xee00
+ 80b8: ed90003c ldc 0, cr0, \[r0, #240\]
+
+000080bc <one_group_needed_alu_pc>:
+ 80bc: e3a00000 mov r0, #0 ; 0x0
+Disassembly of section zero:
+
+00000000 <one_group_needed_alu_sb>:
+ 0: e3a00000 mov r0, #0 ; 0x0
+Disassembly of section alpha:
+
+0000eef0 <two_groups_needed_alu_pc>:
+ eef0: e3a00000 mov r0, #0 ; 0x0
+Disassembly of section beta:
+
+00ffeef0 <three_groups_needed_alu_pc>:
+ ffeef0: e3a00000 mov r0, #0 ; 0x0
+#...
diff --git a/ld/testsuite/ld-arm/group-relocs.s b/ld/testsuite/ld-arm/group-relocs.s
new file mode 100644
index 0000000..da1a150
--- /dev/null
+++ b/ld/testsuite/ld-arm/group-relocs.s
@@ -0,0 +1,156 @@
+@ Tests for group relocations.
+@
+@ Beware when editing this file: it is carefully crafted so that
+@ specific PC- and SB-relative offsets arise.
+@
+@ Note that the gas tests have already checked that group relocations are
+@ handled in the same way for local and external symbols.
+
+@ We will place .text at 0x8000.
+
+ .text
+ .globl _start
+
+_start:
+ @ ALU, PC-relative
+
+ @ Instructions start at .text + 0x0
+ add r0, r15, #:pc_g0:(one_group_needed_alu_pc)
+
+ @ Instructions start at .text + 0x4
+ add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc)
+ add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4)
+
+ @ Instructions start at .text + 0xc
+ add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc)
+ add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4)
+ add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8)
+
+ @ ALU, SB-relative
+
+ add r0, r0, #:sb_g0:(one_group_needed_alu_sb)
+
+ add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb)
+ add r0, r0, #:sb_g1:(two_groups_needed_alu_sb)
+
+ add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb)
+ add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb)
+ add r0, r0, #:sb_g2:(three_groups_needed_alu_sb)
+
+ @ LDR, PC-relative
+
+ @ Instructions start at .text + 0x30
+ add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc)
+ ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)]
+
+ @ Instructions start at .text + 0x38
+ add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc)
+ add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4)
+ ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)]
+
+ @ LDR, SB-relative
+
+ ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)]
+
+ add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb)
+ ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)]
+
+ add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb)
+ add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb)
+ ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)]
+
+ @ LDRS, PC-relative
+
+ @ Instructions start at .text + 0x5c
+ ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)]
+
+ @ Instructions start at .text + 0x60
+ add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc)
+ ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)]
+
+ @ Instructions start at .text + 0x68
+ add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc)
+ add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4)
+ ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)]
+
+ @ LDRS, SB-relative
+
+ ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)]
+
+ add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb)
+ ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)]
+
+ add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb)
+ add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb)
+ ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)]
+
+ @ LDC, PC-relative
+
+ @ Instructions start at .text + 0x8c
+ ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)]
+
+ @ Instructions start at .text + 0x90
+ add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc)
+ ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)]
+
+ @ Instructions start at .text + 0x98
+ add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc)
+ add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4)
+ ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)]
+
+ @ LDC, SB-relative
+
+ ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)]
+
+ add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb)
+ ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)]
+
+ add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb)
+ add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb)
+ ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)]
+
+@ This point in the file is .text + 0xbc.
+
+one_group_needed_alu_pc:
+one_group_needed_ldrs_pc:
+one_group_needed_ldc_pc:
+ mov r0, #0
+
+@ We will place the section zero at 0x0.
+
+ .section zero
+
+one_group_needed_alu_sb:
+one_group_needed_ldr_sb:
+one_group_needed_ldrs_sb:
+one_group_needed_ldc_sb:
+ mov r0, #0
+
+@ We will place the section alpha at 0xeef0.
+
+ .section alpha
+
+two_groups_needed_alu_sb:
+two_groups_needed_ldr_sb:
+two_groups_needed_ldrs_sb:
+two_groups_needed_ldc_sb:
+two_groups_needed_alu_pc:
+two_groups_needed_ldr_pc:
+two_groups_needed_ldrs_pc:
+two_groups_needed_ldc_pc:
+ mov r0, #0
+
+@ We will place the section beta at 0xffeef0.
+
+ .section beta
+
+three_groups_needed_alu_sb:
+three_groups_needed_ldr_sb:
+three_groups_needed_ldrs_sb:
+three_groups_needed_ldc_sb:
+three_groups_needed_alu_pc:
+three_groups_needed_ldr_pc:
+three_groups_needed_ldrs_pc:
+three_groups_needed_ldc_pc:
+ mov r0, #0
+