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-rw-r--r--ld/testsuite/ld-powerpc/ambiguousv1.d4
-rw-r--r--ld/testsuite/ld-powerpc/ambiguousv1b.d9
-rw-r--r--ld/testsuite/ld-powerpc/ambiguousv2.d4
-rw-r--r--ld/testsuite/ld-powerpc/ambiguousv2b.d9
-rw-r--r--ld/testsuite/ld-powerpc/elfv2so.d18
-rw-r--r--ld/testsuite/ld-powerpc/powerpc.exp29
-rw-r--r--ld/testsuite/ld-powerpc/tlsopt5.d12
-rw-r--r--ld/testsuite/ld-powerpc/tlsopt5.wf14
-rw-r--r--ld/testsuite/ld-powerpc/tlsopt5_32.d16
9 files changed, 57 insertions, 58 deletions
diff --git a/ld/testsuite/ld-powerpc/ambiguousv1.d b/ld/testsuite/ld-powerpc/ambiguousv1.d
index a74325a..dcff2d8 100644
--- a/ld/testsuite/ld-powerpc/ambiguousv1.d
+++ b/ld/testsuite/ld-powerpc/ambiguousv1.d
@@ -18,7 +18,7 @@ Symbol table '\.dynsym' contains 5 entries:
0: .*
1: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
#...
-Symbol table '\.symtab' contains 19 entries:
+Symbol table '\.symtab' contains .* entries:
#...
- 14: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
+.*: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
#pass
diff --git a/ld/testsuite/ld-powerpc/ambiguousv1b.d b/ld/testsuite/ld-powerpc/ambiguousv1b.d
index 7b9753a..678b8ad 100644
--- a/ld/testsuite/ld-powerpc/ambiguousv1b.d
+++ b/ld/testsuite/ld-powerpc/ambiguousv1b.d
@@ -14,11 +14,10 @@ Relocation section .* contains 1 entries:
.* R_PPC64_COPY .* my_func \+ 0
Symbol table '\.dynsym' contains 5 entries:
-.*
- 0: .*
- 1: 0+10010408 4 FUNC GLOBAL DEFAULT 12 my_func
#...
-Symbol table '\.symtab' contains 20 entries:
+.*: 0*[1-9a-f][0-9a-f]* 4 FUNC GLOBAL DEFAULT 1[23] my_func
+#...
+Symbol table '\.symtab' contains .* entries:
#...
- 15: 0+10010408 4 FUNC GLOBAL DEFAULT 12 my_func
+.*: 0*[1-9a-f][0-9a-f]* 4 FUNC GLOBAL DEFAULT 1[23] my_func
#pass
diff --git a/ld/testsuite/ld-powerpc/ambiguousv2.d b/ld/testsuite/ld-powerpc/ambiguousv2.d
index 99c8a39..fec3a2c 100644
--- a/ld/testsuite/ld-powerpc/ambiguousv2.d
+++ b/ld/testsuite/ld-powerpc/ambiguousv2.d
@@ -24,7 +24,7 @@ Symbol table '\.dynsym' contains 5 entries:
1: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
#...
-Symbol table '\.symtab' contains 21 entries:
+Symbol table '\.symtab' contains .* entries:
#...
- 16: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
+.*: 0+00000000 0 FUNC GLOBAL DEFAULT UND my_func
#pass
diff --git a/ld/testsuite/ld-powerpc/ambiguousv2b.d b/ld/testsuite/ld-powerpc/ambiguousv2b.d
index 859a3ea..c93cd11 100644
--- a/ld/testsuite/ld-powerpc/ambiguousv2b.d
+++ b/ld/testsuite/ld-powerpc/ambiguousv2b.d
@@ -15,11 +15,10 @@ Relocation section .* contains 1 entries:
.* R_PPC64_JMP_SLOT .* my_func \+ 0
Symbol table '\.dynsym' contains 5 entries:
-.*
- 0: .*
- 1: 0+100002b8 0 FUNC GLOBAL DEFAULT UND my_func
#...
-Symbol table '\.symtab' contains 21 entries:
+.*: 0*[1-9a-f][0-9a-f]* 0 FUNC GLOBAL DEFAULT UND my_func
+#...
+Symbol table '\.symtab' contains .* entries:
#...
- 16: 0+100002b8 0 FUNC GLOBAL DEFAULT UND my_func
+.*: 0*[1-9a-f][0-9a-f]* 0 FUNC GLOBAL DEFAULT UND my_func
#pass
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index f3962ac..2c1fa32 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -7,33 +7,33 @@
Disassembly of section \.text:
-0+300 <.*\.plt_call\.f4>:
+.* <.*\.plt_call\.f4>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-0+310 <.*\.plt_call\.f3>:
+.* <.*\.plt_call\.f3>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-0+320 <.*\.plt_call\.f2>:
+.* <.*\.plt_call\.f2>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-0+330 <.*\.plt_call\.f1>:
+.* <.*\.plt_call\.f1>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-0+340 <f1>:
+.* <f1>:
.*: (3c 4c 00 02|02 00 4c 3c) addis r2,r12,2
-.*: (38 42 82 c0|c0 82 42 38) addi r2,r2,-32064
+.*: (38 42 .. ..|.. .. 42 38) addi r2,r2,.*
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
@@ -50,10 +50,10 @@ Disassembly of section \.text:
.*: (38 21 00 20|20 00 21 38) addi r1,r1,32
.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
.*: (4e 80 00 20|20 00 80 4e) blr
-.*: (00 00 00 00|80 02 01 00) .*
-.*: (00 01 02 80|00 00 00 00) .*
+.*
+.*
-0+390 <__glink_PLTresolve>:
+.* <__glink_PLTresolve>:
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (42 9f 00 05|05 00 9f 42) bcl .*
.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp
index 6249ccb..4405fa3 100644
--- a/ld/testsuite/ld-powerpc/powerpc.exp
+++ b/ld/testsuite/ld-powerpc/powerpc.exp
@@ -29,33 +29,34 @@ if {[istarget "*-*-vxworks"]} {
"-mregnames" {vxworks1-lib.s}
{{readelf --segments vxworks1-lib.sd}}
"libvxworks1.so"}
- {"VxWorks shared library test 1" "-shared -Tvxworks1.ld" ""
+ {"VxWorks shared library test 1"
+ "-shared --hash-style=sysv -Tvxworks1.ld" ""
"-mregnames" {vxworks1-lib.s}
{{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
{readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
"libvxworks1.so"}
{"VxWorks executable test 1 (dynamic)" \
- "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic" ""
+ "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic --hash-style=sysv" ""
"-mregnames" {vxworks1.s}
{{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
"vxworks1"}
{"VxWorks executable test 2 (dynamic)" \
- "-Tvxworks1.ld -q --force-dynamic" ""
+ "-Tvxworks1.ld -q --force-dynamic --hash-style=sysv" ""
"-mregnames" {vxworks2.s}
{{readelf --segments vxworks2.sd}}
"vxworks2"}
{"VxWorks executable test 2 (static)"
- "-Tvxworks1.ld" ""
+ "-Tvxworks1.ld --hash-style=sysv" ""
"-mregnames" {vxworks2.s}
{{readelf --segments vxworks2-static.sd}}
"vxworks2"}
{"VxWorks relax test"
- "-Tvxworks1.ld --relax -q" ""
+ "-Tvxworks1.ld --relax -q --hash-style=sysv" ""
"-mregnames" {vxworks-relax.s}
{{readelf --relocs vxworks-relax.rd}}
"vxworks-relax"}
{"VxWorks relocatable relax test"
- "-Tvxworks1.ld -r --relax -q" ""
+ "-Tvxworks1.ld -r --relax -q --hash-style=sysv" ""
"-mregnames" {vxworks-relax-2.s}
{{readelf --relocs vxworks-relax-2.rd}}
"vxworks-relax-2"}
@@ -115,11 +116,11 @@ set ppcelftests {
"tls32"}
{"TLS32 helper shared library" "-shared -melf32ppc tmpdir/tlslib32.o" "" "" {}
{} "libtlslib32.so"}
- {"TLS32 dynamic exec" "-melf32ppc --no-ld-generated-unwind-info tmpdir/tls32.o tmpdir/libtlslib32.so" "" "" {}
+ {"TLS32 dynamic exec" "-melf32ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tls32.o tmpdir/libtlslib32.so" "" "" {}
{{readelf -WSsrl tlsexe32.r} {objdump -dr tlsexe32.d}
{objdump -sj.got tlsexe32.g} {objdump -sj.tdata tlsexe32.t}}
"tlsexe32"}
- {"TLS32 shared" "-shared -melf32ppc --no-ld-generated-unwind-info tmpdir/tls32.o" "" "" {}
+ {"TLS32 shared" "-shared -melf32ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tls32.o" "" "" {}
{{readelf -WSsrl tlsso32.r} {objdump -dr tlsso32.d}
{objdump -sj.got tlsso32.g} {objdump -sj.tdata tlsso32.t}}
"tls32.so"}
@@ -163,15 +164,15 @@ set ppc64elftests {
{} "libtlslib.so"}
{"TLS helper old shared lib" "-shared -melf64ppc" "" "-a64" {oldtlslib.s}
{} "liboldlib.so"}
- {"TLS dynamic exec" "-melf64ppc --no-ld-generated-unwind-info tmpdir/tls.o tmpdir/libtlslib.so" "" "" {}
+ {"TLS dynamic exec" "-melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tls.o tmpdir/libtlslib.so" "" "" {}
{{readelf -WSsrl tlsexe.r} {objdump -dr tlsexe.d}
{objdump -sj.got tlsexe.g} {objdump -sj.tdata tlsexe.t}}
"tlsexe"}
- {"TLS dynamic old" "-melf64ppc --no-ld-generated-unwind-info tmpdir/tls.o tmpdir/liboldlib.so" "" "" {}
+ {"TLS dynamic old" "-melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tls.o tmpdir/liboldlib.so" "" "" {}
{{readelf -WSsrl tlsexe.r} {objdump -dr tlsexe.d}
{objdump -sj.got tlsexe.g} {objdump -sj.tdata tlsexe.t}}
"tlsexeold"}
- {"TLS shared" "-shared -melf64ppc --no-ld-generated-unwind-info tmpdir/tls.o" "" "" {}
+ {"TLS shared" "-shared -melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tls.o" "" "" {}
{{readelf -WSsrl tlsso.r} {objdump -dr tlsso.d}
{objdump -sj.got tlsso.g} {objdump -sj.tdata tlsso.t}}
"tls.so"}
@@ -179,17 +180,17 @@ set ppc64elftests {
{{objdump -dr tlstoc.d} {objdump -sj.got tlstoc.g}
{objdump -sj.tdata tlstoc.t}}
"tlstoc"}
- {"TLSTOC dynamic exec" "-melf64ppc --no-ld-generated-unwind-info tmpdir/tlstoc.o tmpdir/libtlslib.so" ""
+ {"TLSTOC dynamic exec" "-melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tlstoc.o tmpdir/libtlslib.so" ""
"" {}
{{readelf -WSsrl tlsexetoc.r} {objdump -dr tlsexetoc.d}
{objdump -sj.got tlsexetoc.g} {objdump -sj.tdata tlsexetoc.t}}
"tlsexetoc"}
- {"TLSTOC dynamic old" "-melf64ppc --no-ld-generated-unwind-info tmpdir/tlstoc.o tmpdir/liboldlib.so" ""
+ {"TLSTOC dynamic old" "-melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tlstoc.o tmpdir/liboldlib.so" ""
"" {}
{{readelf -WSsrl tlsexetoc.r} {objdump -dr tlsexetoc.d}
{objdump -sj.got tlsexetoc.g} {objdump -sj.tdata tlsexetoc.t}}
"tlsexetocold"}
- {"TLSTOC shared" "-shared -melf64ppc --no-ld-generated-unwind-info tmpdir/tlstoc.o" "" "" {}
+ {"TLSTOC shared" "-shared -melf64ppc --no-ld-generated-unwind-info --hash-style=sysv tmpdir/tlstoc.o" "" "" {}
{{readelf -WSsrl tlstocso.r} {objdump -dr tlstocso.d}
{objdump -sj.got tlstocso.g} {objdump -sj.tdata tlstocso.t}}
"tlstoc.so"}
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d
index 3c85185..4521a9b 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5.d
+++ b/ld/testsuite/ld-powerpc/tlsopt5.d
@@ -8,7 +8,7 @@
Disassembly of section \.text:
-0+2c0 <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>:
+.* <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>:
.*: (00 00 63 e9|e9 63 00 00) ld r11,0\(r3\)
.*: (08 00 83 e9|e9 83 00 08) ld r12,8\(r3\)
.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3
@@ -27,14 +27,14 @@ Disassembly of section \.text:
.*: (a6 03 68 7d|7d 68 03 a6) mtlr r11
.*: (20 00 80 4e|4e 80 00 20) blr
-0+304 <_start>:
+.* <_start>:
.*: (08 80 62 38|38 62 80 08) addi r3,r2,-32760
.*: (b9 ff ff 4b|4b ff ff b9) bl .*
.*: (00 00 00 60|60 00 00 00) nop
-.*: (f8 02 01 00|00 00 00 00) .*
-.*: (00 00 00 00|00 01 02 f8) .*
+.*
+.*
-0+318 <__glink_PLTresolve>:
+.* <__glink_PLTresolve>:
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (05 00 9f 42|42 9f 00 05) bcl .*
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
@@ -50,5 +50,5 @@ Disassembly of section \.text:
.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
.*: (20 04 80 4e|4e 80 04 20) bctr
-0+350 <__tls_get_addr_opt@plt>:
+.* <__tls_get_addr_opt@plt>:
.*: (c8 ff ff 4b|4b ff ff c8) b .*
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.wf b/ld/testsuite/ld-powerpc/tlsopt5.wf
index 05ef7e0..158f650 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5.wf
+++ b/ld/testsuite/ld-powerpc/tlsopt5.wf
@@ -10,23 +10,23 @@ Contents of the \.eh_frame section:
DW_CFA_def_cfa: r1 ofs 0
-0+14 0+14 0+18 FDE cie=0+ pc=0+2c0\.\.0+304
- DW_CFA_advance_loc: 48 to 0+2f0
+0+14 0+14 0+18 FDE cie=0+ pc=.*
+ DW_CFA_advance_loc: 48 to .*
DW_CFA_offset_extended_sf: r65 at cfa\+8
- DW_CFA_advance_loc: 16 to 0+300
+ DW_CFA_advance_loc: 16 to .*
DW_CFA_restore_extended: r65
-0+2c 0+18 0+30 FDE cie=0+ pc=0+318\.\.0+354
- DW_CFA_advance_loc: 4 to 0+31c
+0+2c 0+18 0+30 FDE cie=0+ pc=.*
+ DW_CFA_advance_loc: 4 to .*
DW_CFA_register: r65 in r0
- DW_CFA_advance_loc: 28 to 0+338
+ DW_CFA_advance_loc: 28 to .*
DW_CFA_restore_extended: r65
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop
-0+48 0+10 0+4c FDE cie=0+ pc=0+304\.\.0+310
+0+48 0+10 0+4c FDE cie=0+ pc=.*
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop
diff --git a/ld/testsuite/ld-powerpc/tlsopt5_32.d b/ld/testsuite/ld-powerpc/tlsopt5_32.d
index 64acf10..4f1bf06 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5_32.d
+++ b/ld/testsuite/ld-powerpc/tlsopt5_32.d
@@ -8,7 +8,7 @@
Disassembly of section \.text:
-0+200 <_start>:
+.* <_start>:
.*: (f0 ff 21 94|94 21 ff f0) stwu r1,-16\(r1\)
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (05 00 9f 42|42 9f 00 05) bcl .*
@@ -16,9 +16,9 @@ Disassembly of section \.text:
.*: (a6 02 c8 7f|7f c8 02 a6) mflr r30
.*: (01 00 de 3f|3f de 00 01) addis r30,r30,1
.*: (14 00 01 90|90 01 00 14) stw r0,20\(r1\)
-.*: (7c 01 de 3b|3b de 01 7c) addi r30,r30,380
+.*: (.. .. de 3b|3b de .. ..) addi r30,r30,.*
.*: (f8 ff 7e 38|38 7e ff f8) addi r3,r30,-8
-.*: (1d 00 00 48|48 00 00 1d) bl 240 <.*__tls_get_addr_opt.*>
+.*: (1d 00 00 48|48 00 00 1d) bl .* <.*__tls_get_addr_opt.*>
.*: (14 00 01 80|80 01 00 14) lwz r0,20\(r1\)
.*: (08 00 c1 83|83 c1 00 08) lwz r30,8\(r1\)
.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
@@ -26,7 +26,7 @@ Disassembly of section \.text:
.*: (20 00 80 4e|4e 80 00 20) blr
.*
-0+240 <.*__tls_get_addr_opt.*>:
+.* <.*__tls_get_addr_opt.*>:
.*: (00 00 63 81|81 63 00 00) lwz r11,0\(r3\)
.*: (04 00 83 81|81 83 00 04) lwz r12,4\(r3\)
.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3
@@ -40,13 +40,13 @@ Disassembly of section \.text:
.*: (20 04 80 4e|4e 80 04 20) bctr
.*: (00 00 00 60|60 00 00 00) nop
-0+270 <__glink>:
+.* <__glink>:
.*: (00 00 00 60|60 00 00 00) nop
.*: (00 00 00 60|60 00 00 00) nop
.*: (00 00 00 60|60 00 00 00) nop
.*: (00 00 00 60|60 00 00 00) nop
-0+280 <__glink_PLTresolve>:
+.* <__glink_PLTresolve>:
.*: (00 00 6b 3d|3d 6b 00 00) addis r11,r11,0
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (05 00 9f 42|42 9f 00 05) bcl .*
@@ -55,8 +55,8 @@ Disassembly of section \.text:
.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
.*: (50 58 6c 7d|7d 6c 58 50) subf r11,r12,r11
.*: (01 00 8c 3d|3d 8c 00 01) addis r12,r12,1
-.*: (00 01 0c 80|80 0c 01 00) lwz r0,256\(r12\)
-.*: (04 01 8c 81|81 8c 01 04) lwz r12,260\(r12\)
+.*: (.. .. 0c 80|80 0c .. ..) lwz r0,.*\(r12\)
+.*: (.. .. 8c 81|81 8c .. ..) lwz r12,.*\(r12\)
.*: (a6 03 09 7c|7c 09 03 a6) mtctr r0
.*: (14 5a 0b 7c|7c 0b 5a 14) add r0,r11,r11
.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
generated by cgit v1.1 at 2024-11-19 16:16:13 +0000