diff options
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1a39640..3849fdc 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -137,6 +137,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_MASK_ALN 0x7 #define OP_SH_VSEL 21 #define OP_MASK_VSEL 0x1f +#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, + but 0x8-0xf don't select bytes. */ +#define OP_SH_VECBYTE 22 +#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ +#define OP_SH_VECALIGN 21 /* Values in the 'VSEL' field. */ #define MDMX_FMTSEL_IMM_QH 0x1d @@ -189,6 +194,7 @@ struct mips_opcode "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) + Also used for immediate operands in vr5400 vector insns. "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -221,6 +227,9 @@ struct mips_opcode "G" 5 bit destination register (OP_*_RD) "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) + "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) + see also "k" above Macro instructions: "A" General 32 bit expression @@ -241,11 +250,12 @@ struct mips_opcode Other: "()" parens surrounding optional value "," separates operands + "[]" brackets around index for vector-op scalar operand specifier (vr5400) Characters used so far, for quick reference when adding more: - "<>()," + "%[]<>()," "ABCDEFGHIJLMNOPQRSTUVWXYZ" - "abcdfhijklopqrstuvwxz" + "abcdefhijklopqrstuvwxz" */ /* These are the bits which may be set in the pinfo field of an @@ -362,6 +372,14 @@ struct mips_opcode #define INSN_10000 0x00100000 /* Broadcom SB-1 instruction. */ #define INSN_SB1 0x00200000 +/* NEC VR4111/VR4181 instruction. */ +#define INSN_4111 0x00400000 +/* NEC VR4120 instruction. */ +#define INSN_4120 0x00800000 +/* NEC VR5400 instruction. */ +#define INSN_5400 0x01000000 +/* NEC VR5500 instruction. */ +#define INSN_5500 0x02000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -383,11 +401,14 @@ struct mips_opcode #define CPU_R4010 4010 #define CPU_VR4100 4100 #define CPU_R4111 4111 +#define CPU_VR4120 4120 #define CPU_R4300 4300 #define CPU_R4400 4400 #define CPU_R4600 4600 #define CPU_R4650 4650 #define CPU_R5000 5000 +#define CPU_VR5400 5400 +#define CPU_VR5500 5500 #define CPU_R6000 6000 #define CPU_R8000 8000 #define CPU_R10000 10000 @@ -407,12 +428,15 @@ struct mips_opcode (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ - && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ && ((insn)->membership & INSN_10000) != 0) \ || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. |