diff options
Diffstat (limited to 'include/opcode/aarch64.h')
| -rw-r--r-- | include/opcode/aarch64.h | 66 |
1 files changed, 63 insertions, 3 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9daa911..bc779c9 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -183,6 +183,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_LSE128, /* ARMv8.9-A RAS Extensions. */ AARCH64_FEATURE_RASv2, + /* Delegated SError exceptions for EL3. */ + AARCH64_FEATURE_E3DSE, /* System Control Register2. */ AARCH64_FEATURE_SCTLR2, /* Fine Grained Traps. */ @@ -220,6 +222,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PMUv3_ICNTR, /* System Performance Monitors Extension */ AARCH64_FEATURE_SPMU, + /* System Performance Monitors Extension version 2 */ + AARCH64_FEATURE_SPMU2, /* Performance Monitors Synchronous-Exception-Based Event Extension. */ AARCH64_FEATURE_SEBEP, /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ @@ -230,6 +234,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SVE2p1, /* RCPC3 instructions. */ AARCH64_FEATURE_RCPC3, + /* Enhanced Software Step Extension. */ + AARCH64_FEATURE_STEP2, /* Checked Pointer Arithmetic instructions. */ AARCH64_FEATURE_CPA, /* FAMINMAX instructions. */ @@ -366,7 +372,11 @@ enum aarch64_feature_bit { #define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \ | AARCH64_FEATBIT (X, CPA) \ | AARCH64_FEATBIT (X, LUT) \ - | AARCH64_FEATBIT (X, FAMINMAX)) + | AARCH64_FEATBIT (X, FAMINMAX)\ + | AARCH64_FEATBIT (X, E3DSE) \ + | AARCH64_FEATBIT (X, SPMU2) \ + | AARCH64_FEATBIT (X, STEP2) \ + ) /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \ @@ -779,6 +789,7 @@ enum aarch64_opnd AARCH64_OPND_SME_ZA_array_vrsh_2, /* Tile to vector, four registers (H). */ AARCH64_OPND_SME_ZA_array_vrss_2, /* Tile to vector, four registers (S). */ AARCH64_OPND_SME_ZA_array_vrsd_2, /* Tile to vector, four registers (D). */ + AARCH64_OPND_SME_ZA_ARRAY4, /* Tile to vector, single (BHSDQ). */ AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ @@ -857,6 +868,14 @@ enum aarch64_opnd AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ + AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ + AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ + AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ + AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ + AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ + AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ + AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ + AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ @@ -1049,6 +1068,7 @@ enum aarch64_insn_class sme_ldr, sme_psel, sme_shift, + sme_size_12_bh, sme_size_12_bhs, sme_size_12_hs, sme_size_12_b, @@ -1090,7 +1110,8 @@ enum aarch64_insn_class sve2_urqvs, sve_index1, rcpc3, - lut + lut, + last_iclass = lut }; /* Opcode enumerators. */ @@ -1367,7 +1388,30 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_OPD_SIZE (1ULL << 34) /* RCPC3 instruction has the field of 'size'. */ #define F_RCPC3_SIZE (1ULL << 35) -/* Next bit is 36. */ +/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to + assembler. */ +#define F_VG_REQ (1ULL << 36) + +/* 4-bit flag field to indicate subclass of instructions. + Note the overlap between the set of subclass flags in each logical category + (F_LDST_*, F_ARITH_*, F_BRANCH_* etc.); The usage of flags as + iclass-specific enums is intentional. */ +#define F_SUBCLASS (15ULL << 37) + +#define F_LDST_LOAD (1ULL << 37) +#define F_LDST_STORE (2ULL << 37) +/* Subclasses to denote add, sub and mov insns. */ +#define F_ARITH_ADD (1ULL << 37) +#define F_ARITH_SUB (2ULL << 37) +#define F_ARITH_MOV (3ULL << 37) +/* Subclasses to denote call and ret insns. */ +#define F_BRANCH_CALL (1ULL << 37) +#define F_BRANCH_RET (2ULL << 37) +/* Subclass to denote that only tag update is involved. */ +#define F_DP_TAG_ONLY (1ULL << 37) + +#define F_SUBCLASS_OTHER (F_SUBCLASS) +/* Next bit is 41. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1406,6 +1450,16 @@ pseudo_opcode_p (const aarch64_opcode *opcode) return (opcode->flags & F_PSEUDO) != 0lu; } +/* Whether the opcode has the specific subclass flag. + N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* etc. subclass + flags means that the callers of this function have the responsibility of + checking for the flags appropriate for the specific iclass. */ +static inline bool +aarch64_opcode_subclass_p (const aarch64_opcode *opcode, uint64_t flag) +{ + return ((opcode->flags & F_SUBCLASS) == flag); +} + /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range [IDX, IDX + 1]. */ @@ -1431,6 +1485,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) } static inline bool +get_opcode_dependent_vg_status (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 36) & 0x1; +} + +static inline bool opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |