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-rw-r--r--gdb/pinsn.c1354
1 files changed, 698 insertions, 656 deletions
diff --git a/gdb/pinsn.c b/gdb/pinsn.c
index 94ac7f7..e7aba32 100644
--- a/gdb/pinsn.c
+++ b/gdb/pinsn.c
@@ -1,5 +1,6 @@
-/* Print m68k instructions for GDB, the GNU debugger.
+/* Print sparc instructions for GDB, the GNU debugger.
Copyright (C) 1986, 1987 Free Software Foundation, Inc.
+ Contributed by Michael Tiemann (tiemann@mcc.com)
GDB is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY. No author or distributor accepts responsibility to anyone
@@ -23,747 +24,788 @@ anyone else from sharing it farther. Help stamp out software hoarding!
#include "defs.h"
#include "param.h"
#include "symtab.h"
-#include "opcode.h"
+#include "sparc-opcode.h"
-/* 68k instructions are never longer than this many bytes. */
-#define MAXLEN 22
+/* sparc instructions are never longer than this many bytes. */
+#define MAXLEN 4
+
+/* Print the sparc instruction at address MEMADDR in debugged memory,
+ on STREAM. Returns length of the instruction, in bytes, which
+ is always 4. */
+
+struct op1_fmt
+{
+ unsigned op1 : 2;
+ unsigned dummy : 30;
+};
+
+struct op2_fmt
+{
+ unsigned dummy1 : 7;
+ unsigned op2 : 3;
+ unsigned dummy2 : 22;
+};
+
+struct op3_fmt
+{
+ unsigned dummy1 : 7;
+ unsigned op3 : 6;
+ unsigned dummy2 : 19;
+};
+
+struct call_fmt
+{
+ unsigned op : 2;
+ unsigned disp : 30;
+};
+
+struct sethi_fmt
+{
+ unsigned op : 2;
+ unsigned rd : 5;
+ unsigned op2 : 3;
+ unsigned imm : 22;
+};
+
+struct branch_fmt
+{
+ unsigned op : 2;
+ unsigned a : 1;
+ unsigned cond : 4;
+ unsigned op2 : 3;
+ unsigned disp : 22; /* this should really be signed. */
+};
+
+struct ldst_fmt
+{
+ unsigned op : 2;
+ unsigned rd : 5;
+ unsigned op3 : 6;
+ unsigned rs1 : 5;
+ unsigned i : 1;
+ unsigned asi : 8;
+ unsigned rs2 : 5;
+};
+
+struct arith_imm_fmt
+{
+ unsigned op : 2;
+ unsigned rd : 5;
+ unsigned op3 : 6;
+ unsigned rs1 : 5;
+ unsigned i : 1;
+ unsigned simm : 13;
+};
+
+struct arith_fmt
+{
+ unsigned op : 2;
+ unsigned rd : 5;
+ unsigned op3 : 6;
+ unsigned rs1 : 5;
+ unsigned i : 1;
+ unsigned opf : 8;
+ unsigned rs2 : 5;
+};
+
+union insn_fmt
+{
+ struct op1_fmt op1;
+ struct op2_fmt op2;
+ struct op3_fmt op3;
+ struct call_fmt call;
+ struct sethi_fmt sethi;
+ struct branch_fmt branch;
+ struct ldst_fmt ldst;
+ struct arith_imm_fmt arith_imm;
+ struct arith_fmt arith;
+ int intval;
+ float floatval; /* ?? */
+};
+
+typedef enum
+{
+ Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
+} branch_type;
-/* Number of elements in the opcode table. */
-#define NOPCODES (sizeof m68k_opcodes / sizeof m68k_opcodes[0])
+static char *icc_name[] =
+{ "~", "eq", "le", "lt", "leu", "ltu", "neg", "vs",
+ "", "ne", "gt", "ge", "gtu", "geu", "pos", "vc"};
-extern char *reg_names[];
-char *fpcr_names[] = { "", "fpiar", "fpsr", "fpiar/fpsr", "fpcr",
- "fpiar/fpcr", "fpsr/fpcr", "fpiar-fpcr"};
+static char *fcc_name[] =
+{ "~fb", "fbne", "fblg", "fbul", "fbl", "fbug", "fbg", "fbu",
+ "fb", "fbe", "fbue", "fbge", "fbuge", "fble", "fbule", "fbo"};
-static unsigned char *print_insn_arg ();
-static unsigned char *print_indexed ();
-static void print_base ();
-static int fetch_arg ();
+static char *ccc_name[] =
+{ "~cb", "cb123", "cb12", "cb13", "cb1", "cb23", "cb2", "cb3",
+ "cb", "cb0", "cb03", "cb02", "cb023", "cb01", "cb013", "cb012"};
-#define NEXTBYTE(p) (p += 2, ((char *)p)[-1])
+static char *arith_name[] =
+{ "add", "and", "or", "xor", "sub", "andn", "orn", "xnor",
+ "addx", 0, 0, 0, "subx", 0, 0, 0};
-#define NEXTWORD(p) \
- (p += 2, ((((char *)p)[-2]) << 8) + p[-1])
+static char *xarith_name[] =
+{ "taddcc", "tsubcc", "taddcctv", "tsubcctv", "mulscc", "sll", "srl", "sra"};
-#define NEXTLONG(p) \
- (p += 4, (((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])
+static char *state_reg_name[] =
+{ "%y", "%psr", "%wim", "%tbr", 0, 0, 0, 0};
-#define NEXTSINGLE(p) \
- (p += 4, *((float *)(p - 4)))
+static char *ldst_i_name[] =
+{ "ld", "ldub", "lduh", "ldd", "st", "stb", "sth", "std",
+ 0, "ldsb", "ldsh", 0, 0, "ldstub", 0, "swap",
+ "lda", "lduba", "lduha", "ldda", "sta", "stba", "stha", "stda",
+ 0, "ldsba", "ldsha", 0, 0, "ldstuba", 0, "swapa"};
-#define NEXTDOUBLE(p) \
- (p += 8, *((double *)(p - 8)))
+static char *ldst_f_name[] =
+{ "ldf", "ldfsr", 0, "lddf", "stf", "stfsr", "stdfq", "stdf"};
-#define NEXTEXTEND(p) \
- (p += 12, 0.0) /* Need a function to convert from extended to double
- precision... */
+static char *ldst_c_name[] =
+{ "ldc", "ldcsr", 0, "lddc", "stc", "stcsr", "stdcq", "stdc"};
-#define NEXTPACKED(p) \
- (p += 12, 0.0) /* Need a function to convert from packed to double
- precision. Actually, it's easier to print a
- packed number than a double anyway, so maybe
- there should be a special case to handle this... */
-
-/* Print the m68k instruction at address MEMADDR in debugged memory,
- on STREAM. Returns length of the instruction, in bytes. */
+static int this_sethi_target = -1;
+static int last_sethi_target = -1;
+static int sethi_value = 0;
+
+static void fprint_addr1 ();
+static void fprint_ldst ();
+static void fprint_f_ldst ();
+static void fprint_c_ldst ();
+static void fprint_fpop ();
int
print_insn (memaddr, stream)
CORE_ADDR memaddr;
FILE *stream;
{
- unsigned char buffer[MAXLEN];
- register int i;
- register unsigned char *p;
- register char *d;
- register int bestmask;
- int best;
-
- read_memory (memaddr, buffer, MAXLEN);
-
- bestmask = 0;
- best = -1;
- for (i = 0; i < NOPCODES; i++)
+ union insn_fmt insn;
+ int disp22;
+
+ read_memory (memaddr, &insn, MAXLEN);
+
+ this_sethi_target = -1;
+ switch (insn.op1.op1)
{
- register unsigned int opcode = m68k_opcodes[i].opcode;
- register unsigned int match = m68k_opcodes[i].match;
- if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
- && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
- && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
- && ((0xff & buffer[3] & match) == (0xff & opcode)))
+ case 1:
+ /* CALL format. */
+ fprintf (stream, "call ");
+ print_address (memaddr + (insn.call.disp << 2), stream);
+ break;
+ case 0:
+ /* Bicc, FBfcc, CBccc, SETHI format. */
+ switch (insn.op2.op2)
{
- /* Don't use for printout the variants of divul and divsl
- that have the same register number in two places.
- The more general variants will match instead. */
- for (d = m68k_opcodes[i].args; *d; d += 2)
- if (d[1] == 'D')
- break;
-
- /* Don't use for printout the variants of most floating
- point coprocessor instructions which use the same
- register number in two places, as above. */
- if (*d == 0)
- for (d = m68k_opcodes[i].args; *d; d += 2)
- if (d[1] == 't')
+ case 0:
+ fprintf (stream, "unimp");
+ break;
+ case 2:
+ /* Bicc. */
+ fprintf (stream, "b%s", icc_name[insn.branch.cond]);
+ if (insn.branch.a) fprintf (stream, ",a ");
+ else fprintf (stream, " ");
+ disp22 = insn.branch.disp;
+ disp22 = ((disp22 << 10) >> 10);
+ print_address (memaddr + (disp22 << 2), stream);
+ break;
+ case 4:
+ /* SETHI. */
+ fprintf (stream, "sethi %%hi(0x%x),%s",
+ insn.sethi.imm << 10, reg_names[insn.sethi.rd]);
+ this_sethi_target = insn.sethi.rd;
+ sethi_value = insn.sethi.imm << 12;
+ break;
+ case 6:
+ /* FBdfcc. */
+ fprintf (stream, "fb%s", fcc_name[insn.branch.cond]);
+ if (insn.branch.a) fprintf (stream, ",a ");
+ else fprintf (stream, " ");
+ disp22 = insn.branch.disp;
+ disp22 = ((disp22 << 10) >> 10);
+ print_address (memaddr + (disp22 << 2), stream);
+ break;
+ case 7:
+ /* CBccc. */
+ fprintf (stream, "cb%s", ccc_name[insn.branch.cond]);
+ if (insn.branch.a) fprintf (stream, ",a ");
+ else fprintf (stream, " ");
+ disp22 = insn.branch.disp;
+ disp22 = ((disp22 << 10) >> 10);
+ print_address (memaddr + (disp22 << 2), stream);
+ break;
+ default:
+ fprintf (stream, "0x%x (illegal op2 format)", insn.intval);
+ break;
+ }
+ break;
+ case 2:
+ {
+ /* vaguely arithmetic insns. */
+ char *rd = reg_names[insn.arith.rd];
+ char *rs1 = reg_names[insn.arith.rs1];
+
+ if (insn.op3.op3 <= 28)
+ {
+ /* Arithmetic insns, with a few unimplemented. */
+ register int affect_cc = insn.op3.op3 & 16;
+ char *name = arith_name[insn.op3.op3 ^ affect_cc];
+ char *tmp = affect_cc ? "cc" : "";
+
+ if (name == 0)
+ {
+ fprintf (stream, "0x%08x (unimplemented arithmetic insn)",
+ insn.intval);
+ }
+ else if (insn.arith.i)
+ {
+ fprintf (stream, "%s%s %s,0x%x,%s",
+ name, tmp, rs1, insn.arith_imm.simm, rd);
+ if (last_sethi_target == insn.arith.rd)
+ {
+ fprintf (stream, "\t! ");
+ print_address (sethi_value + insn.arith_imm.simm);
+ }
+ }
+ else
+ {
+ fprintf (stream, "%s%s %s,%s,%s",
+ name, tmp, rs1, reg_names[insn.arith.rs2], rd);
+ }
+ break;
+ }
+ if (insn.op3.op3 < 32)
+ {
+ fprintf (stream, "0x%08x (unimplemented arithmetic insn)",
+ insn.intval);
+ break;
+ }
+ else
+ {
+ int op = insn.op3.op3 ^ 32;
+
+ if (op < 8)
+ {
+ char *name = xarith_name[op];
+ /* tagged add/sub insns and shift insns. */
+ if (insn.arith.i)
+ {
+ int i = insn.arith_imm.simm;
+ if (op > 4)
+ /* Its a shift insn. */
+ i &= 31;
+
+ fprintf (stream, "%s %s,0x%x,%s",
+ name, rs1, i, rd);
+ }
+ else
+ {
+ fprintf (stream, "%s %s,%s,%s",
+ name, rs1, reg_names[insn.arith.rs2], rd);
+ }
break;
+ }
+ if (op < 20)
+ {
+ /* read/write state registers. */
+ char *sr = state_reg_name[op & 7];
+ if (sr == 0)
+ fprintf (stream, "0x%08x (unimplemented state register insn",
+ insn.intval);
+ else
+ fprintf (stream, "%s %s,%s", op & 16 ? "wr" : "rd", sr, rd);
+ break;
+ }
+ if (op < 22)
+ {
+ /* floating point insns. */
+ int opcode = insn.arith.opf;
- if (*d == 0 && match > bestmask)
- {
- best = i;
- bestmask = match;
- }
- }
- }
+ fprint_fpop (stream, insn, op & 3, opcode);
+ break;
+ }
+ if (op < 24)
+ {
+ /* coprocessor insns. */
+ char *rs2 = reg_names[insn.arith.rs2];
+ int opcode = insn.arith.opf;
- /* Handle undefined instructions. */
- if (best < 0)
- {
- fprintf (stream, "0%o", (buffer[0] << 8) + buffer[1]);
- return 2;
- }
+ fprintf (stream, "cpop%d rs1=%s,rs2=%s,op=0x%x,rd=%s",
+ op & 1, rs1, rs2, opcode, rd);
+ break;
+ }
- fprintf (stream, "%s", m68k_opcodes[best].name);
+ switch (op)
+ {
+ char *rndop_ptr;
- /* Point at first word of argument data,
- and at descriptor for first argument. */
- p = buffer + 2;
-
- /* Why do this this way? -MelloN */
- for (d = m68k_opcodes[best].args; *d; d += 2)
- {
- if (d[0] == '#')
- {
- if (d[1] == 'l' && p - buffer < 6)
- p = buffer + 6;
- else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8' )
- p = buffer + 4;
- }
- if (d[1] >= '1' && d[1] <= '3' && p - buffer < 4)
- p = buffer + 4;
- if (d[1] >= '4' && d[1] <= '6' && p - buffer < 6)
- p = buffer + 6;
- }
+ case 24:
+ fprint_addr1 (stream, "jumpl", insn);
+ break;
+ case 25:
+ fprint_addr1 (stream, "rett", insn);
+ break;
+ case 26:
+ {
+ char rndop_buf[32];
+ sprintf (rndop_buf, "t%s", icc_name[insn.branch.cond]);
+ fprint_addr1 (stream, rndop_buf, insn);
+ }
+ break;
+ case 27:
+ fprint_addr1 (stream, "iflush", insn);
+ break;
- d = m68k_opcodes[best].args;
+ case 28:
+ rndop_ptr = "save";
+ case 29:
+ if (op == 29)
+ rndop_ptr = "restore";
+
+ if (insn.arith.i)
+ {
+ fprintf (stream, "%s %s,0x%x,%s",
+ rndop_ptr, rs1,
+ ((insn.arith_imm.simm << 19) >> 19), rd);
+ }
+ else
+ {
+ fprintf (stream, "%s %s,%s,%s",
+ rndop_ptr, rs1, reg_names[insn.arith.rs2], rd);
+ }
+ break;
+ case 30:
+ case 31:
+ fprintf (stream, "0x%08x (unimplemented op3 insn)",
+ insn.intval);
+ break;
+ }
+ break;
+ }
+ }
+ case 3:
+ /* load and store insns. */
+ {
+ char *rd = reg_names[insn.arith.rd];
+ char *rs1 = reg_names[insn.arith.rs1];
+ int op = insn.arith.op3;
+
+ if ((op & 32) == 0)
+ {
+ /* Integer ops. */
+ fprint_ldst (stream, insn, op);
+ break;
+ }
+ if ((op & 16) == 0)
+ {
+ /* Float ops. */
+ op ^= 32;
+ if (op <= 7)
+ {
+ fprint_f_ldst (stream, insn, op);
+ }
+ else
+ fprintf (stream, "0x%08x (unimplemented float load/store insn)",
+ insn.intval);
+ }
+ else
+ {
+ /* Coprocessor ops. */
+ op ^= (32+16);
+ if (op <= 7)
+ {
+ fprint_c_ldst (stream, insn, op);
+ }
+ else
+ fprintf (stream, "0x%08x (unimplemented coprocessor load/store insn)",
+ insn.intval);
+ }
+ break;
+ }
+ }
+ return 4;
+}
- if (*d)
- fputc (' ', stream);
+/* It would be nice if this routine could print out a symbolic address
+ when appropriate. */
+static void
+fprint_addr1 (stream, name, insn)
+ FILE *stream;
+ char *name;
+ union insn_fmt insn;
+{
+ char *rs1 = reg_names[insn.arith.rs1];
+ char *rd = reg_names[insn.arith.rd];
- while (*d)
+ if (insn.arith.i)
+ {
+ fprintf (stream, "%s %s,0x%x,%s",
+ name, rs1, insn.arith_imm.simm, rd);
+ }
+ else
{
- p = print_insn_arg (d, buffer, p, memaddr + p - buffer, stream);
- d += 2;
- if (*d && *(d - 2) != 'I' && *d != 'k')
- fprintf (stream, ",");
+ fprintf (stream, "%s %s,%s,%s",
+ name, rs1, reg_names[insn.arith.rs2], rd);
}
- return p - buffer;
}
-static unsigned char *
-print_insn_arg (d, buffer, p, addr, stream)
- char *d;
- unsigned char *buffer;
- register unsigned char *p;
- CORE_ADDR addr; /* PC for this arg to be relative to */
+static void
+fprint_mem (stream, insn)
FILE *stream;
+ union insn_fmt insn;
{
- register int val;
- register int place = d[1];
- int regno;
- register char *regname;
- register unsigned char *p1;
- register double flval;
- int flt_p;
-
- switch (*d)
+ char *reg_name = reg_names[insn.arith.rs1];
+ if (insn.arith.i)
{
- case 'C':
- fprintf (stream, "ccr");
- break;
-
- case 'S':
- fprintf (stream, "sr");
- break;
-
- case 'U':
- fprintf (stream, "usp");
- break;
-
- case 'J':
- {
- static struct { char *name; int value; } names[]
- = {{"sfc", 0x000}, {"dfc", 0x001}, {"cacr", 0x002},
- {"usp", 0x800}, {"vbr", 0x801}, {"caar", 0x802},
- {"msp", 0x803}, {"isp", 0x804}};
-
- val = fetch_arg (buffer, place, 12);
- for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
- if (names[regno].value == val)
- {
- fprintf (stream, names[regno].name);
- break;
- }
- if (regno < 0)
- fprintf (stream, "%d", val);
- }
- break;
-
- case 'Q':
- val = fetch_arg (buffer, place, 3);
- if (val == 0) val = 8;
- fprintf (stream, "#%d", val);
- break;
-
- case 'M':
- val = fetch_arg (buffer, place, 8);
- if (val & 0x80)
- val = val - 0x100;
- fprintf (stream, "#%d", val);
- break;
-
- case 'T':
- val = fetch_arg (buffer, place, 4);
- fprintf (stream, "#%d", val);
- break;
-
- case 'D':
- fprintf (stream, "%s", reg_names[fetch_arg (buffer, place, 3)]);
- break;
-
- case 'A':
- fprintf (stream, "%s", reg_names[fetch_arg (buffer, place, 3) + 010]);
- break;
-
- case 'R':
- fprintf (stream, "%s", reg_names[fetch_arg (buffer, place, 4)]);
- break;
+ if (insn.arith_imm.simm == 0)
+ fprintf (stream, "[%s]", reg_name);
+ else if (insn.arith_imm.simm & 0x1000)
+ fprintf (stream, "[%s-0x%x]", reg_name,
+ - (insn.arith_imm.simm | 0xffffe000));
+ else
+ fprintf (stream, "[%s+0x%x]", reg_name, insn.arith_imm.simm);
+ }
+ else
+ {
+ if (insn.arith.rs2 == 0)
+ fprintf (stream, "[%s]", reg_name);
+ else
+ fprintf (stream, "[%s,%s]", reg_names[insn.arith.rs2], reg_name);
+ }
+}
- case 'F':
- fprintf (stream, "fp%d", fetch_arg (buffer, place, 3));
- break;
+static void
+fprint_ldst (stream, insn, op)
+ FILE *stream;
+ union insn_fmt insn;
+ int op;
+{
+ char *name = ldst_i_name[op];
+ char *rd = reg_names[insn.arith.rd];
- case 'O':
- val = fetch_arg (buffer, place, 6);
- if (val & 0x20)
- fprintf (stream, "%s", reg_names [val & 7]);
+ if (name)
+ {
+ if (name[0] == 's')
+ {
+ fprintf (stream, "%s %s,", name, rd);
+ fprint_mem (stream, insn);
+ }
else
- fprintf (stream, "%d", val);
- break;
-
- case '+':
- fprintf (stream, "(%s)+", reg_names[fetch_arg (buffer, place, 3) + 8]);
- break;
+ {
+ fprintf (stream, "%s ", name);
+ fprint_mem (stream, insn);
+ fprintf (stream, ",%s", rd);
+ }
+ }
+ else
+ fprintf (stream, "0x%08x (unimplemented load/store insn)", insn.intval);
+}
- case '-':
- fprintf (stream, "-(%s)", reg_names[fetch_arg (buffer, place, 3) + 8]);
- break;
+static void
+fprint_f_ldst (stream, insn, op)
+ FILE *stream;
+ union insn_fmt insn;
+ int op;
+{
+ char *name = ldst_f_name[op];
+ if (name)
+ {
+ char *rd = reg_names[insn.arith.rd + 32];
- case 'k':
- if (place == 'k')
- fprintf (stream, "{%s}", reg_names[fetch_arg (buffer, place, 3)]);
- else if (place == 'C')
+ if (name[0] == 's')
{
- val = fetch_arg (buffer, place, 7);
- if ( val > 63 ) /* This is a signed constant. */
- val -= 128;
- fprintf (stream, "{#%d}", val);
+ fprintf (stream, "%s %s,", name, rd);
+ fprint_mem (stream, insn);
}
else
- error ("Invalid arg format in opcode table: \"%c%c\".",
- *d, place);
- break;
+ {
+ fprintf (stream, "%s ", name);
+ fprint_mem (stream, insn);
+ fprintf (stream, ",%s", rd);
+ }
+ }
+ else
+ fprintf (stream, "0x%08x (unimplemented float load/store insn)", insn.intval);
+}
- case '#':
- p1 = buffer + 2;
- if (place == 's')
- val = fetch_arg (buffer, place, 4);
- else if (place == 'C')
- val = fetch_arg (buffer, place, 7);
- else if (place == '8')
- val = fetch_arg (buffer, place, 3);
- else if (place == '3')
- val = fetch_arg (buffer, place, 8);
- else if (place == 'b')
- val = NEXTBYTE (p1);
- else if (place == 'w')
- val = NEXTWORD (p1);
- else if (place == 'l')
- val = NEXTLONG (p1);
+static void
+fprint_c_ldst (stream, insn, op)
+ FILE *stream;
+ union insn_fmt insn;
+ int op;
+{
+ char *name = ldst_c_name[op];
+ if (name)
+ {
+ if (name[0] == 's')
+ {
+ fprintf (stream, "%s %%cpreg(%d),", name, insn.arith.rs1);
+ fprint_mem (stream, insn);
+ }
else
- error ("Invalid arg format in opcode table: \"%c%c\".",
- *d, place);
- fprintf (stream, "#%d", val);
- break;
+ {
+ fprintf (stream, "%s ");
+ fprint_mem (stream, insn);
+ fprintf (stream, ",%%cpreg(%d)", insn.arith.rd);
+ }
+ }
+ else
+ fprintf (stream, "0x%08x (unimplemented coprocessor load/store insn)",
+ insn.intval);
+}
- case '^':
- if (place == 's')
- val = fetch_arg (buffer, place, 4);
- else if (place == 'C')
- val = fetch_arg (buffer, place, 7);
- else if (place == '8')
- val = fetch_arg (buffer, place, 3);
- else if (place == 'b')
- val = NEXTBYTE (p);
- else if (place == 'w')
- val = NEXTWORD (p);
- else if (place == 'l')
- val = NEXTLONG (p);
- else
- error ("Invalid arg format in opcode table: \"%c%c\".",
- *d, place);
- fprintf (stream, "#%d", val);
- break;
+static void
+fprint_fpop (stream, insn, op, opcode)
+ FILE *stream;
+ union insn_fmt insn;
+ int op, opcode;
+{
+ char *name;
+ char *rs1, *rs2, *rd;
- case 'B':
- if (place == 'b')
- val = NEXTBYTE (p);
- else if (place == 'w')
- val = NEXTWORD (p);
- else if (place == 'l')
- val = NEXTLONG (p);
- else if (place == 'g')
+ switch (op)
+ {
+ case 0:
+ rs2 = reg_names[insn.arith.rs2 + 32];
+ rd = reg_names[insn.arith.rd + 32];
+ if ((opcode ^ 0x2f) <= 0x2f)
{
- val = ((char *)buffer)[1];
- if (val == 0)
- val = NEXTWORD (p);
- else if (val == -1)
- val = NEXTLONG (p);
+ switch (opcode)
+ {
+ case 0x1:
+ name = "fmovs";
+ break;
+ case 0x5:
+ name = "fnegs";
+ break;
+ case 0x9:
+ name = "fabss";
+ break;
+ case 0x29:
+ name = "fsqrts";
+ break;
+ case 0x2a:
+ name = "fsqrtd";
+ break;
+ case 0x2b:
+ name = "fsqrtx";
+ break;
+ }
+ fprintf (stream, "%s %s,%s", name, rs2, rd);
+ return;
}
- else if (place == 'c')
+ if ((opcode ^ 0x5f) <= 0x5f)
{
- if (buffer[1] & 0x40) /* If bit six is one, long offset */
- val = NEXTLONG (p);
+ rs1 = reg_names[insn.arith.rs1 + 32];
+ switch (opcode)
+ {
+ case 0x41:
+ name = "fadds";
+ break;
+ case 0x42:
+ name = "faddd";
+ break;
+ case 0x43:
+ name = "faddx";
+ break;
+ case 0x45:
+ name = "fsubs";
+ break;
+ case 0x46:
+ name = "fsubd";
+ break;
+ case 0x47:
+ name = "fsubx";
+ break;
+ case 0x49:
+ name = "fmuls";
+ break;
+ case 0x4a:
+ name = "fmuld";
+ break;
+ case 0x4b:
+ name = "fmulx";
+ break;
+ case 0x4d:
+ name = "fdivs";
+ break;
+ case 0x4e:
+ name = "fdivd";
+ break;
+ case 0x4f:
+ name = "fdivx";
+ break;
+ default:
+ goto unimplemented;
+ }
+ if ((opcode & 0x10) == 0)
+ fprintf (stream, "%s %s,%s,%s", name, rs1, rs2, rd);
else
- val = NEXTWORD (p);
+ fprintf (stream, "%s %s,%s", name, rs1, rs2);
+ return;
}
- else
- error ("Invalid arg format in opcode table: \"%c%c\".",
- *d, place);
-
- print_address (addr + val, stream);
- break;
-
- case 'd':
- val = NEXTWORD (p);
- fprintf (stream, "%d(%s)", val, reg_names[fetch_arg (buffer, place, 3)]);
- break;
-
- case 's':
- fprintf (stream, "%s", fpcr_names[fetch_arg (buffer, place, 3)]);
- break;
-
- case 'I':
- val = fetch_arg (buffer, 'd', 3); /* Get coprocessor ID... */
- if (val != 1) /* Unusual coprocessor ID? */
- fprintf (stream, "(cpid=%d) ", val);
- if (place == 'i')
- p += 2; /* Skip coprocessor extended operands */
- break;
-
- case '*':
- case '~':
- case '%':
- case ';':
- case '@':
- case '!':
- case '$':
- case '?':
- case '/':
- case '&':
-
- if (place == 'd')
+ if ((opcode ^ 0xdf) <= 0xdf)
{
- val = fetch_arg (buffer, 'x', 6);
- val = ((val & 7) << 3) + ((val >> 3) & 7);
+ switch (opcode)
+ {
+ case 0xc4:
+ name = "fitos";
+ break;
+ case 0xc8:
+ name = "fitod";
+ break;
+ case 0xcc:
+ name = "fitox";
+ break;
+ case 0xd1:
+ name = "fstoi";
+ break;
+ case 0xd2:
+ name = "fdtoi";
+ break;
+ case 0xd3:
+ name = "fxtoi";
+ break;
+ case 0xc9:
+ name = "fstod";
+ break;
+ case 0xcd:
+ name = "fstox";
+ break;
+ case 0xc6:
+ name = "fdtos";
+ break;
+ case 0xce:
+ name = "fdtox";
+ break;
+ case 0xc7:
+ name = "fxtos";
+ break;
+ case 0xcb:
+ name = "fxtod";
+ break;
+ default:
+ goto unimplemented;
+ }
+ fprintf (stream, "%s %s,%s", name, rs2, rd);
+ return;
}
- else
- val = fetch_arg (buffer, 's', 6);
+ goto unimplemented;
- /* Get register number assuming address register. */
- regno = (val & 7) + 8;
- regname = reg_names[regno];
- switch (val >> 3)
+ case 1:
+ rs1 = reg_names[insn.arith.rs1 + 32];
+ rs2 = reg_names[insn.arith.rs2 + 32];
+ if ((opcode ^ 0x57) <= 0x57)
{
- case 0:
- fprintf (stream, "%s", reg_names[val]);
- break;
-
- case 1:
- fprintf (stream, "%s", regname);
- break;
-
- case 2:
- fprintf (stream, "(%s)", regname);
- break;
-
- case 3:
- fprintf (stream, "(%s)+", regname);
- break;
-
- case 4:
- fprintf (stream, "-(%s)", regname);
- break;
-
- case 5:
- val = NEXTWORD (p);
- fprintf (stream, "%d(%s)", val, regname);
- break;
-
- case 6:
- p = print_indexed (regno, p, addr, stream);
- break;
-
- case 7:
- switch (val & 7)
+ switch (opcode)
{
- case 0:
- val = NEXTWORD (p);
- fprintf (stream, "@#");
- print_address (val, stream);
+ case 0x51:
+ name = "fcmps";
break;
-
- case 1:
- val = NEXTLONG (p);
- fprintf (stream, "@#");
- print_address (val, stream);
+ case 0x52:
+ name = "fcmpd";
break;
-
- case 2:
- val = NEXTWORD (p);
- print_address (addr + val, stream);
+ case 0x53:
+ name = "fcmpx";
break;
-
- case 3:
- p = print_indexed (-1, p, addr, stream);
+ case 0x55:
+ name = "fcmpes";
break;
-
- case 4:
- flt_p = 1; /* Assume it's a float... */
- switch( place )
- {
- case 'b':
- val = NEXTBYTE (p);
- flt_p = 0;
- break;
-
- case 'w':
- val = NEXTWORD (p);
- flt_p = 0;
- break;
-
- case 'l':
- val = NEXTLONG (p);
- flt_p = 0;
- break;
-
- case 'f':
- flval = NEXTSINGLE(p);
- break;
-
- case 'F':
- flval = NEXTDOUBLE(p);
- break;
-
- case 'x':
- flval = NEXTEXTEND(p);
- break;
-
- case 'p':
- flval = NEXTPACKED(p);
- break;
-
- default:
- error ("Invalid arg format in opcode table: \"%c%c\".",
- *d, place);
- }
- if ( flt_p ) /* Print a float? */
- fprintf (stream, "#%g", flval);
- else
- fprintf (stream, "#%d", val);
+ case 0x56:
+ name = "fcmped";
+ break;
+ case 0x57:
+ name = "fcmpex";
break;
-
default:
- fprintf (stream, "<invalid address mode 0%o>", val);
+ goto unimplemented;
}
+ fprintf (stream, "%s %s,%s", name, rs1, rs2);
+ return;
}
- break;
+ else goto unimplemented;
- default:
- error ("Invalid arg format in opcode table: \"%c\".", *d);
+ case 2:
+ case 3:
+ goto unimplemented;
}
-
- return (unsigned char *) p;
+ unimplemented:
+ fprintf (stream, "0x%08x (unimplemented fpop insn)", insn.intval);
}
-/* Fetch BITS bits from a position in the instruction specified by CODE.
- CODE is a "place to put an argument", or 'x' for a destination
- that is a general address (mode and register).
- BUFFER contains the instruction. */
-
-static int
-fetch_arg (buffer, code, bits)
- unsigned char *buffer;
- char code;
- int bits;
+/* Set *target if we find a branch */
+branch_type
+isabranch (addr, target)
+ CORE_ADDR addr, *target;
{
- register int val;
- switch (code)
+ union insn_fmt instr;
+ branch_type val = not_branch;
+ long offset; /* Must be signed for sign-extend */
+
+ *target = 0;
+ instr.intval = read_memory_integer (addr, 4);
+ /* printf("intval = %x\n",instr.intval); */
+ switch (instr.op1.op1)
{
- case 's':
- val = buffer[1];
- break;
-
- case 'd': /* Destination, for register or quick. */
- val = (buffer[0] << 8) + buffer[1];
- val >>= 9;
- break;
-
- case 'x': /* Destination, for general arg */
- val = (buffer[0] << 8) + buffer[1];
- val >>= 6;
- break;
-
- case 'k':
- val = (buffer[3] >> 4);
- break;
-
- case 'C':
- val = buffer[3];
- break;
-
- case '1':
- val = (buffer[2] << 8) + buffer[3];
- val >>= 12;
- break;
-
- case '2':
- val = (buffer[2] << 8) + buffer[3];
- val >>= 6;
- break;
-
- case '3':
- case 'j':
- val = (buffer[2] << 8) + buffer[3];
- break;
-
- case '4':
- val = (buffer[4] << 8) + buffer[5];
- val >>= 12;
- break;
-
- case '5':
- val = (buffer[4] << 8) + buffer[5];
- val >>= 6;
- break;
-
- case '6':
- val = (buffer[4] << 8) + buffer[5];
- break;
-
- case '7':
- val = (buffer[2] << 8) + buffer[3];
- val >>= 7;
- break;
-
- case '8':
- val = (buffer[2] << 8) + buffer[3];
- val >>= 10;
+ case 0: /* Format 2 */
+ switch(instr.op2.op2)
+ {
+ case 2: case 6: /* BICC & FBCC */
+ if (instr.branch.cond == 8)
+ val = instr.branch.a ? baa : ba;
+ else
+ val = instr.branch.a ? bicca : bicc;
+ /* 22 bits, sign extended */
+ offset = ((instr.branch.disp << 10) >> 10);
+ *target = addr + offset;
+ break;
+ }
break;
-
- default:
- abort ();
- }
-
- switch (bits)
- {
- case 3:
- return val & 7;
- case 4:
- return val & 017;
- case 5:
- return val & 037;
- case 6:
- return val & 077;
- case 7:
- return val & 0177;
- case 8:
- return val & 0377;
- case 12:
- return val & 07777;
- default:
- abort ();
}
+ /*printf("isabranch ret: %d\n",val); */
+ return val;
}
-/* Print an indexed argument. The base register is BASEREG (-1 for pc).
- P points to extension word, in buffer.
- ADDR is the nominal core address of that extension word. */
-
-static unsigned char *
-print_indexed (basereg, p, addr, stream)
- int basereg;
- unsigned char *p;
- FILE *stream;
- CORE_ADDR addr;
+CORE_ADDR skip_prologue (pc)
+ CORE_ADDR pc;
{
- register int word;
- static char *scales[] = {"", "*2", "*4", "*8"};
- register int base_disp;
- register int outer_disp;
- char buf[40];
-
- word = NEXTWORD (p);
-
- /* Generate the text for the index register.
- Where this will be output is not yet determined. */
- sprintf (buf, "[%s.%c%s]",
- reg_names[(word >> 12) & 0xf],
- (word & 0x800) ? 'l' : 'w',
- scales[(word >> 9) & 3]);
-
- /* Handle the 68000 style of indexing. */
-
- if ((word & 0x100) == 0)
+ union
{
- print_base (basereg,
- ((word & 0x80) ? word | 0xff00 : word & 0xff)
- + ((basereg == -1) ? addr : 0),
- stream);
- fprintf (stream, "%s", buf);
- return p;
- }
-
- /* Handle the generalized kind. */
- /* First, compute the displacement to add to the base register. */
+ struct insn_fmt insn;
+ int i;
+ } x;
+ int dest = -1;
- if (word & 0200)
- basereg = -2;
- if (word & 0100)
- buf[0] = 0;
- base_disp = 0;
- switch ((word >> 4) & 3)
+ x.i = read_memory_integer (pc, 4);
+ if (x.insn.sethi.op == 0 && x.insn.sethi.op2 == 4)
{
- case 2:
- base_disp = NEXTWORD (p);
- break;
- case 3:
- base_disp = NEXTLONG (p);
+ dest = x.insn.sethi.rd;
+ pc += 4;
+ x.i = read_memory_integer (pc, 4);
}
- if (basereg == -1)
- base_disp += addr;
-
- /* Handle single-level case (not indirect) */
-
- if ((word & 7) == 0)
+ if (x.insn.arith_imm.op == 2 && x.insn.arith_imm.i == 1
+ && (x.insn.arith_imm.rd == 1 || x.insn.arith_imm.rd == dest))
{
- print_base (basereg, base_disp, stream);
- fprintf (stream, "%s", buf);
- return p;
+ pc += 4;
+ x.i = read_memory_integer (pc, 4);
}
-
- /* Two level. Compute displacement to add after indirection. */
-
- outer_disp = 0;
- switch (word & 3)
+ if (x.insn.arith.op == 2 && (x.insn.arith.op3 ^ 32) == 28)
{
- case 2:
- outer_disp = NEXTWORD (p);
- break;
- case 3:
- outer_disp = NEXTLONG (p);
+ pc += 4;
}
-
- fprintf (stream, "%d(", outer_disp);
- print_base (basereg, base_disp, stream);
-
- /* If postindexed, print the closeparen before the index. */
- if (word & 4)
- fprintf (stream, ")%s", buf);
- /* If preindexed, print the closeparen after the index. */
- else
- fprintf (stream, "%s)", buf);
-
- return p;
+ return pc;
}
-/* Print a base register REGNO and displacement DISP, on STREAM.
- REGNO = -1 for pc, -2 for none (suppressed). */
-
-static void
-print_base (regno, disp, stream)
- int regno;
- int disp;
- FILE *stream;
+CORE_ADDR
+frame_saved_pc (frame, next_frame)
+ CORE_ADDR frame;
+ CORE_ADDR next_frame;
{
- if (regno == -2)
- fprintf (stream, "%d", disp);
- else if (regno == -1)
- fprintf (stream, "0x%x", disp);
- else
- fprintf (stream, "%d(%s)", disp, reg_names[regno]);
-}
-
-/* This is not part of insn printing, but it is machine-specific,
- so this is a convenient place to put it.
+ CORE_ADDR prev_pc;
- Convert a 68881 extended float to a double.
- FROM is the address of the extended float.
- Store the double in *TO. */
-
-convert_from_68881 (from, to)
- char *from;
- double *to;
-{
-#ifdef HPUX_ASM
- asm ("mov.l 8(%a6),%a0");
- asm ("mov.l 12(%a6),%a1");
- asm ("fmove.x (%a0),%fp0");
- asm ("fmove.d %fp0,(%a1)");
-#else /* not HPUX_ASM */
-#if 0
- asm ("movl a6@(8),a0");
- asm ("movl a6@(12),a1");
- asm ("fmovex a0@,fp0");
- asm ("fmoved fp0,a1@");
-#else
- /* Hand-assemble those insns since some assemblers lose
- and some have different syntax. */
- asm (".word 020156");
- asm (".word 8");
- asm (".word 021156");
- asm (".word 12");
- asm (".long 0xf2104800");
- asm (".long 0xf2117400");
-#endif
-#endif /* not HPUX_ASM */
-}
-
-/* The converse: convert the double *FROM to an extended float
- and store where TO points. */
+ if (next_frame)
+ prev_pc = GET_RWINDOW_REG (next_frame, rw_in[7]);
+ else if (frame)
+ prev_pc = GET_RWINDOW_REG (read_register (SP_REGNUM), rw_in[7]);
+ else
+ error ("frame_saved_pc called without a frame");
-convert_to_68881 (from, to)
- double *from;
- char *to;
-{
-#ifdef HPUX_ASM
- asm ("mov.l 8(%a6),%a0");
- asm ("mov.l 12(%a6),%a1");
- asm ("fmove.d (%a0),%fp0");
- asm ("fmove.x %fp0,(%a1)");
-#else /* not HPUX_ASM */
-#if 0
- asm ("movl a6@(8),a0");
- asm ("movl a6@(12),a1");
- asm ("fmoved a0@,fp0");
- asm ("fmovex fp0,a1@");
-#else
- /* Hand-assemble those insns since some assemblers lose. */
- asm (".word 020156");
- asm (".word 8");
- asm (".word 021156");
- asm (".word 12");
- asm (".long 0xf2105400");
- asm (".long 0xf2116800");
-#endif
-#endif /* not HPUX_ASM */
+ return PC_ADJUST (prev_pc);
}
generated by cgit v1.1 at 2024-07-13 14:56:37 +0000