diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 14 | ||||
| -rw-r--r-- | gas/config/tc-i386-intel.c | 5 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 40 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/ilp32/x86-64-opcode.d | 306 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-opcode.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-opcode.s | 4 |
6 files changed, 45 insertions, 328 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 2d8a997..bdff6e4 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,17 @@ +2019-07-16 Jan Beulich <jbeulich@suse.com> + + * config/tc-i386.c (type_names): Replace SReg entries. + (pi, check_byte_reg, build_modrm_byte, i386_att_operand, + parse_real_register): Switch to using sreg field. + (process_operands): Likewise. Extend handling of PUSH/POP of + segment registers. Drop dead setting of REX_B. + * config/tc-i386-intel.c (i386_intel_simplify_register, + i386_intel_operand): Switch to using sreg field. + * testsuite/gas/i386/x86-64-opcode.s: Add PUSH/POP of %fs/%gs. + * testsuite/gas/i386/x86-64-opcode.d: Adjust expectations. + * testsuite/gas/i386/ilp32/x86-64-opcode.d: Use parent dir + expectations. + 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src' diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c index a2cd286..8f738b9 100644 --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -283,7 +283,7 @@ i386_intel_simplify_register (expressionS *e) as_bad (_("invalid use of register")); return 0; } - if (i386_regtab[reg_num].reg_type.bitfield.sreg3 + if (i386_regtab[reg_num].reg_type.bitfield.sreg && i386_regtab[reg_num].reg_num == RegFlat) { as_bad (_("invalid use of pseudo-register")); @@ -984,8 +984,7 @@ i386_intel_operand (char *operand_string, int got_a_float) as_bad (_("segment register name expected")); return 0; } - if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg2 - && !i386_regtab[expP->X_add_number].reg_type.bitfield.sreg3) + if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg) { as_bad (_("invalid use of register")); return 0; diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 2e60561..1f2b298 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3031,8 +3031,7 @@ pi (const char *line, i386_insn *x) if (x->types[j].bitfield.reg || x->types[j].bitfield.regmmx || x->types[j].bitfield.regsimd - || x->types[j].bitfield.sreg2 - || x->types[j].bitfield.sreg3 + || x->types[j].bitfield.sreg || x->types[j].bitfield.control || x->types[j].bitfield.debug || x->types[j].bitfield.test) @@ -3129,8 +3128,7 @@ const type_names[] = { OPERAND_TYPE_DEBUG, "debug reg" }, { OPERAND_TYPE_FLOATREG, "FReg" }, { OPERAND_TYPE_FLOATACC, "FAcc" }, - { OPERAND_TYPE_SREG2, "SReg2" }, - { OPERAND_TYPE_SREG3, "SReg3" }, + { OPERAND_TYPE_SREG, "SReg" }, { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, { OPERAND_TYPE_REGMMX, "rMMX" }, { OPERAND_TYPE_REGXMM, "rXMM" }, @@ -6575,8 +6573,7 @@ check_byte_reg (void) if (i.types[op].bitfield.reg || i.types[op].bitfield.regmmx || i.types[op].bitfield.regsimd - || i.types[op].bitfield.sreg2 - || i.types[op].bitfield.sreg3 + || i.types[op].bitfield.sreg || i.types[op].bitfield.control || i.types[op].bitfield.debug || i.types[op].bitfield.test) @@ -6994,18 +6991,24 @@ duplicate: if (i.tm.opcode_modifier.shortform) { - if (i.types[0].bitfield.sreg2 - || i.types[0].bitfield.sreg3) + if (i.types[0].bitfield.sreg) { - if (i.tm.base_opcode == POP_SEG_SHORT - && i.op[0].regs->reg_num == 1) + if (flag_code != CODE_64BIT + ? i.tm.base_opcode == POP_SEG_SHORT + && i.op[0].regs->reg_num == 1 + : (i.tm.base_opcode | 1) == POP_SEG_SHORT + && i.op[0].regs->reg_num < 4) { - as_bad (_("you can't `pop %scs'"), register_prefix); + as_bad (_("you can't `%s %s%s'"), + i.tm.name, register_prefix, i.op[0].regs->reg_name); return 0; } + if ( i.op[0].regs->reg_num > 3 ) + { + i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; + i.tm.opcode_length = 2; + } i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); - if ((i.op[0].regs->reg_flags & RegRex) != 0) - i.rex |= REX_B; } else { @@ -7652,8 +7655,7 @@ build_modrm_byte (void) if (i.types[op].bitfield.reg || i.types[op].bitfield.regbnd || i.types[op].bitfield.regmask - || i.types[op].bitfield.sreg2 - || i.types[op].bitfield.sreg3 + || i.types[op].bitfield.sreg || i.types[op].bitfield.control || i.types[op].bitfield.debug || i.types[op].bitfield.test) @@ -10029,9 +10031,7 @@ i386_att_operand (char *operand_string) op_string = end_op; if (is_space_char (*op_string)) ++op_string; - if (*op_string == ':' - && (r->reg_type.bitfield.sreg2 - || r->reg_type.bitfield.sreg3)) + if (*op_string == ':' && r->reg_type.bitfield.sreg) { switch (r->reg_num) { @@ -10894,7 +10894,7 @@ parse_real_register (char *reg_string, char **end_op) return (const reg_entry *) NULL; if ((r->reg_type.bitfield.dword - || r->reg_type.bitfield.sreg3 + || (r->reg_type.bitfield.sreg && r->reg_num > 3) || r->reg_type.bitfield.control || r->reg_type.bitfield.debug || r->reg_type.bitfield.test) @@ -10942,7 +10942,7 @@ parse_real_register (char *reg_string, char **end_op) && flag_code != CODE_64BIT) return (const reg_entry *) NULL; - if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) + if (r->reg_type.bitfield.sreg && r->reg_num == RegFlat && !intel_syntax) return (const reg_entry *) NULL; return r; diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d index f087252..bd67122 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d @@ -2,308 +2,4 @@ #as: -J #objdump: -drw #name: x86-64 (ILP32) opcode - -.*: +file format .* - -Disassembly of section .text: - -0+ <.text>: -[ ]*[a-f0-9]+: 41 ff 10 callq \*\(%r8\) -[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) -[ ]*[a-f0-9]+: 41 ff 10 callq \*\(%r8\) -[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) -[ ]*[a-f0-9]+: cb lret -[ ]*[a-f0-9]+: c3 retq -[ ]*[a-f0-9]+: cf iret -[ ]*[a-f0-9]+: 66 cf iretw -[ ]*[a-f0-9]+: 48 cf iretq -[ ]*[a-f0-9]+: 41 8c 08 mov %cs,\(%r8\) -[ ]*[a-f0-9]+: 8c 08 mov %cs,\(%rax\) -[ ]*[a-f0-9]+: 41 8c 10 mov %ss,\(%r8\) -[ ]*[a-f0-9]+: 8c 10 mov %ss,\(%rax\) -[ ]*[a-f0-9]+: 41 8c 20 mov %fs,\(%r8\) -[ ]*[a-f0-9]+: 8c 20 mov %fs,\(%rax\) -[ ]*[a-f0-9]+: 41 8e 10 mov \(%r8\),%ss -[ ]*[a-f0-9]+: 8e 10 mov \(%rax\),%ss -[ ]*[a-f0-9]+: 41 8e 20 mov \(%r8\),%fs -[ ]*[a-f0-9]+: 8e 20 mov \(%rax\),%fs -[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\) -[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\) -[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\) -[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\) -[ ]*[a-f0-9]+: 41 c7 00 00 00 00 70 movl \$0x70000000,\(%r8\) -[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\) -[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\) -[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\) -[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\) -[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\) -[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\) -[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\) -[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\) -[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\) -[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\) -[ ]*[a-f0-9]+: 41 c7 00 00 00 00 70 movl \$0x70000000,\(%r8\) -[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\) -[ ]*[a-f0-9]+: 49 c7 00 00 00 00 70 movq \$0x70000000,\(%r8\) -[ ]*[a-f0-9]+: 48 c7 00 00 00 00 70 movq \$0x70000000,\(%rax\) -[ ]*[a-f0-9]+: 41 0f c3 00 movnti %eax,\(%r8\) -[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\) -[ ]*[a-f0-9]+: 49 0f c3 00 movnti %rax,\(%r8\) -[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\) -[ ]*[a-f0-9]+: 4d 0f c3 00 movnti %r8,\(%r8\) -[ ]*[a-f0-9]+: 4c 0f c3 00 movnti %r8,\(%rax\) -[ ]*[a-f0-9]+: e2 fe loop 0x[0-9a-f]+ -[ ]*[a-f0-9]+: e2 fe loop 0x[0-9a-f]+ -[ ]*[a-f0-9]+: 67 e2 fd loopl 0x[0-9a-f]+ -[ ]*[a-f0-9]+: e3 fe jrcxz 0x[0-9a-f]+ -[ ]*[a-f0-9]+: 67 e3 fd jecxz 0x[0-9a-f]+ -[ ]*[a-f0-9]+: 41 f6 38 idivb \(%r8\) -[ ]*[a-f0-9]+: f6 38 idivb \(%rax\) -[ ]*[a-f0-9]+: 66 41 f7 38 idivw \(%r8\) -[ ]*[a-f0-9]+: 66 f7 38 idivw \(%rax\) -[ ]*[a-f0-9]+: 41 f7 38 idivl \(%r8\) -[ ]*[a-f0-9]+: f7 38 idivl \(%rax\) -[ ]*[a-f0-9]+: 49 f7 38 idivq \(%r8\) -[ ]*[a-f0-9]+: 48 f7 38 idivq \(%rax\) -[ ]*[a-f0-9]+: 41 f6 28 imulb \(%r8\) -[ ]*[a-f0-9]+: f6 28 imulb \(%rax\) -[ ]*[a-f0-9]+: 66 41 f7 28 imulw \(%r8\) -[ ]*[a-f0-9]+: 66 f7 28 imulw \(%rax\) -[ ]*[a-f0-9]+: 41 f7 28 imull \(%r8\) -[ ]*[a-f0-9]+: f7 28 imull \(%rax\) -[ ]*[a-f0-9]+: 49 f7 28 imulq \(%r8\) -[ ]*[a-f0-9]+: 48 f7 28 imulq \(%rax\) -[ ]*[a-f0-9]+: 66 41 0f 58 00 addpd \(%r8\),%xmm0 -[ ]*[a-f0-9]+: 66 0f 58 00 addpd \(%rax\),%xmm0 -[ ]*[a-f0-9]+: 66 45 0f 58 38 addpd \(%r8\),%xmm15 -[ ]*[a-f0-9]+: 66 44 0f 58 38 addpd \(%rax\),%xmm15 -[ ]*[a-f0-9]+: 66 45 0f 58 00 addpd \(%r8\),%xmm8 -[ ]*[a-f0-9]+: 66 44 0f 58 00 addpd \(%rax\),%xmm8 -[ ]*[a-f0-9]+: 66 41 0f 58 38 addpd \(%r8\),%xmm7 -[ ]*[a-f0-9]+: 66 0f 58 38 addpd \(%rax\),%xmm7 -[ ]*[a-f0-9]+: 66 0f 58 c0 addpd %xmm0,%xmm0 -[ ]*[a-f0-9]+: 66 45 0f 58 ff addpd %xmm15,%xmm15 -[ ]*[a-f0-9]+: 66 45 0f 58 c7 addpd %xmm15,%xmm8 -[ ]*[a-f0-9]+: f2 49 0f 2d 00 cvtsd2si \(%r8\),%rax -[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax -[ ]*[a-f0-9]+: f2 4d 0f 2d 00 cvtsd2si \(%r8\),%r8 -[ ]*[a-f0-9]+: f2 4c 0f 2d 00 cvtsd2si \(%rax\),%r8 -[ ]*[a-f0-9]+: f2 48 0f 2d c0 cvtsd2si %xmm0,%rax -[ ]*[a-f0-9]+: f2 4d 0f 2d c7 cvtsd2si %xmm15,%r8 -[ ]*[a-f0-9]+: f2 49 0f 2d c7 cvtsd2si %xmm15,%rax -[ ]*[a-f0-9]+: f2 4d 0f 2d c0 cvtsd2si %xmm8,%r8 -[ ]*[a-f0-9]+: f2 49 0f 2d c0 cvtsd2si %xmm8,%rax -[ ]*[a-f0-9]+: f2 4c 0f 2d c7 cvtsd2si %xmm7,%r8 -[ ]*[a-f0-9]+: f2 48 0f 2d c7 cvtsd2si %xmm7,%rax -[ ]*[a-f0-9]+: f2 4c 0f 2d c0 cvtsd2si %xmm0,%r8 -[ ]*[a-f0-9]+: f2 49 0f 2c 00 cvttsd2si \(%r8\),%rax -[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax -[ ]*[a-f0-9]+: f2 4d 0f 2c 00 cvttsd2si \(%r8\),%r8 -[ ]*[a-f0-9]+: f2 4c 0f 2c 00 cvttsd2si \(%rax\),%r8 -[ ]*[a-f0-9]+: f2 48 0f 2c c0 cvttsd2si %xmm0,%rax -[ ]*[a-f0-9]+: f2 4d 0f 2c c7 cvttsd2si %xmm15,%r8 -[ ]*[a-f0-9]+: f2 49 0f 2c c7 cvttsd2si %xmm15,%rax -[ ]*[a-f0-9]+: f2 4d 0f 2c c0 cvttsd2si %xmm8,%r8 -[ ]*[a-f0-9]+: f2 49 0f 2c c0 cvttsd2si %xmm8,%rax -[ ]*[a-f0-9]+: f2 4c 0f 2c c7 cvttsd2si %xmm7,%r8 -[ ]*[a-f0-9]+: f2 48 0f 2c c7 cvttsd2si %xmm7,%rax -[ ]*[a-f0-9]+: f2 4c 0f 2c c0 cvttsd2si %xmm0,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2d 00 cvtss2si \(%r8\),%rax -[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax -[ ]*[a-f0-9]+: f3 4d 0f 2d 00 cvtss2si \(%r8\),%r8 -[ ]*[a-f0-9]+: f3 4c 0f 2d 00 cvtss2si \(%rax\),%r8 -[ ]*[a-f0-9]+: f3 48 0f 2d c0 cvtss2si %xmm0,%rax -[ ]*[a-f0-9]+: f3 4d 0f 2d c7 cvtss2si %xmm15,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2d c7 cvtss2si %xmm15,%rax -[ ]*[a-f0-9]+: f3 4d 0f 2d c0 cvtss2si %xmm8,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2d c0 cvtss2si %xmm8,%rax -[ ]*[a-f0-9]+: f3 4c 0f 2d c7 cvtss2si %xmm7,%r8 -[ ]*[a-f0-9]+: f3 48 0f 2d c7 cvtss2si %xmm7,%rax -[ ]*[a-f0-9]+: f3 4c 0f 2d c0 cvtss2si %xmm0,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2c 00 cvttss2si \(%r8\),%rax -[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax -[ ]*[a-f0-9]+: f3 4d 0f 2c 00 cvttss2si \(%r8\),%r8 -[ ]*[a-f0-9]+: f3 4c 0f 2c 00 cvttss2si \(%rax\),%r8 -[ ]*[a-f0-9]+: f3 48 0f 2c c0 cvttss2si %xmm0,%rax -[ ]*[a-f0-9]+: f3 4d 0f 2c c7 cvttss2si %xmm15,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2c c7 cvttss2si %xmm15,%rax -[ ]*[a-f0-9]+: f3 4d 0f 2c c0 cvttss2si %xmm8,%r8 -[ ]*[a-f0-9]+: f3 49 0f 2c c0 cvttss2si %xmm8,%rax -[ ]*[a-f0-9]+: f3 4c 0f 2c c7 cvttss2si %xmm7,%r8 -[ ]*[a-f0-9]+: f3 48 0f 2c c7 cvttss2si %xmm7,%rax -[ ]*[a-f0-9]+: f3 4c 0f 2c c0 cvttss2si %xmm0,%r8 -[ ]*[a-f0-9]+: f3 41 0f 2a 00 cvtsi2ssl \(%r8\),%xmm0 -[ ]*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0 -[ ]*[a-f0-9]+: f3 45 0f 2a 38 cvtsi2ssl \(%r8\),%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 2a 38 cvtsi2ssl \(%rax\),%xmm15 -[ ]*[a-f0-9]+: f3 45 0f 2a 00 cvtsi2ssl \(%r8\),%xmm8 -[ ]*[a-f0-9]+: f3 44 0f 2a 00 cvtsi2ssl \(%rax\),%xmm8 -[ ]*[a-f0-9]+: f3 41 0f 2a 38 cvtsi2ssl \(%r8\),%xmm7 -[ ]*[a-f0-9]+: f3 0f 2a 38 cvtsi2ssl \(%rax\),%xmm7 -[ ]*[a-f0-9]+: f3 0f 2a c0 cvtsi2ss %eax,%xmm0 -[ ]*[a-f0-9]+: f3 44 0f 2a f8 cvtsi2ss %eax,%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 2a c0 cvtsi2ss %eax,%xmm8 -[ ]*[a-f0-9]+: f3 0f 2a f8 cvtsi2ss %eax,%xmm7 -[ ]*[a-f0-9]+: f3 41 0f 2a 00 cvtsi2ssl \(%r8\),%xmm0 -[ ]*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0 -[ ]*[a-f0-9]+: f3 45 0f 2a 38 cvtsi2ssl \(%r8\),%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 2a 38 cvtsi2ssl \(%rax\),%xmm15 -[ ]*[a-f0-9]+: f3 45 0f 2a 00 cvtsi2ssl \(%r8\),%xmm8 -[ ]*[a-f0-9]+: f3 44 0f 2a 00 cvtsi2ssl \(%rax\),%xmm8 -[ ]*[a-f0-9]+: f3 41 0f 2a 38 cvtsi2ssl \(%r8\),%xmm7 -[ ]*[a-f0-9]+: f3 0f 2a 38 cvtsi2ssl \(%rax\),%xmm7 -[ ]*[a-f0-9]+: f2 41 0f 2a 00 cvtsi2sdl \(%r8\),%xmm0 -[ ]*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0 -[ ]*[a-f0-9]+: f2 45 0f 2a 38 cvtsi2sdl \(%r8\),%xmm15 -[ ]*[a-f0-9]+: f2 44 0f 2a 38 cvtsi2sdl \(%rax\),%xmm15 -[ ]*[a-f0-9]+: f2 45 0f 2a 00 cvtsi2sdl \(%r8\),%xmm8 -[ ]*[a-f0-9]+: f2 44 0f 2a 00 cvtsi2sdl \(%rax\),%xmm8 -[ ]*[a-f0-9]+: f2 41 0f 2a 38 cvtsi2sdl \(%r8\),%xmm7 -[ ]*[a-f0-9]+: f2 0f 2a 38 cvtsi2sdl \(%rax\),%xmm7 -[ ]*[a-f0-9]+: f2 0f 2a c0 cvtsi2sd %eax,%xmm0 -[ ]*[a-f0-9]+: f2 44 0f 2a f8 cvtsi2sd %eax,%xmm15 -[ ]*[a-f0-9]+: f2 44 0f 2a c0 cvtsi2sd %eax,%xmm8 -[ ]*[a-f0-9]+: f2 0f 2a f8 cvtsi2sd %eax,%xmm7 -[ ]*[a-f0-9]+: f2 41 0f 2a 00 cvtsi2sdl \(%r8\),%xmm0 -[ ]*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0 -[ ]*[a-f0-9]+: f2 45 0f 2a 38 cvtsi2sdl \(%r8\),%xmm15 -[ ]*[a-f0-9]+: f2 44 0f 2a 38 cvtsi2sdl \(%rax\),%xmm15 -[ ]*[a-f0-9]+: f2 45 0f 2a 00 cvtsi2sdl \(%r8\),%xmm8 -[ ]*[a-f0-9]+: f2 44 0f 2a 00 cvtsi2sdl \(%rax\),%xmm8 -[ ]*[a-f0-9]+: f2 41 0f 2a 38 cvtsi2sdl \(%r8\),%xmm7 -[ ]*[a-f0-9]+: f2 0f 2a 38 cvtsi2sdl \(%rax\),%xmm7 -[ ]*[a-f0-9]+: 66 41 0f 6e 00 movd \(%r8\),%xmm0 -[ ]*[a-f0-9]+: 66 0f 6e 00 movd \(%rax\),%xmm0 -[ ]*[a-f0-9]+: 66 45 0f 6e 38 movd \(%r8\),%xmm15 -[ ]*[a-f0-9]+: 66 44 0f 6e 38 movd \(%rax\),%xmm15 -[ ]*[a-f0-9]+: 66 45 0f 6e 00 movd \(%r8\),%xmm8 -[ ]*[a-f0-9]+: 66 44 0f 6e 00 movd \(%rax\),%xmm8 -[ ]*[a-f0-9]+: 66 41 0f 6e 38 movd \(%r8\),%xmm7 -[ ]*[a-f0-9]+: 66 0f 6e 38 movd \(%rax\),%xmm7 -[ ]*[a-f0-9]+: 66 0f 6e c0 movd %eax,%xmm0 -[ ]*[a-f0-9]+: 66 44 0f 6e f8 movd %eax,%xmm15 -[ ]*[a-f0-9]+: 66 44 0f 6e c0 movd %eax,%xmm8 -[ ]*[a-f0-9]+: 66 0f 6e f8 movd %eax,%xmm7 -[ ]*[a-f0-9]+: 66 41 0f 7e 00 movd %xmm0,\(%r8\) -[ ]*[a-f0-9]+: 66 0f 7e 00 movd %xmm0,\(%rax\) -[ ]*[a-f0-9]+: 66 45 0f 7e 38 movd %xmm15,\(%r8\) -[ ]*[a-f0-9]+: 66 44 0f 7e 38 movd %xmm15,\(%rax\) -[ ]*[a-f0-9]+: 66 45 0f 7e 00 movd %xmm8,\(%r8\) -[ ]*[a-f0-9]+: 66 44 0f 7e 00 movd %xmm8,\(%rax\) -[ ]*[a-f0-9]+: 66 41 0f 7e 38 movd %xmm7,\(%r8\) -[ ]*[a-f0-9]+: 66 0f 7e 38 movd %xmm7,\(%rax\) -[ ]*[a-f0-9]+: 66 0f 7e c0 movd %xmm0,%eax -[ ]*[a-f0-9]+: 66 44 0f 7e f8 movd %xmm15,%eax -[ ]*[a-f0-9]+: 66 44 0f 7e c0 movd %xmm8,%eax -[ ]*[a-f0-9]+: 66 0f 7e f8 movd %xmm7,%eax -[ ]*[a-f0-9]+: 66 48 0f 6e c0 movq %rax,%xmm0 -[ ]*[a-f0-9]+: 66 49 0f 6e c0 movq %r8,%xmm0 -[ ]*[a-f0-9]+: 66 4d 0f 6e f8 movq %r8,%xmm15 -[ ]*[a-f0-9]+: 66 48 0f 7e c0 movq %xmm0,%rax -[ ]*[a-f0-9]+: 66 49 0f 7e c0 movq %xmm0,%r8 -[ ]*[a-f0-9]+: 66 49 0f 7e f8 movq %xmm7,%r8 -[ ]*[a-f0-9]+: f3 41 0f 7e 00 movq \(%r8\),%xmm0 -[ ]*[a-f0-9]+: f3 0f 7e 00 movq \(%rax\),%xmm0 -[ ]*[a-f0-9]+: f3 45 0f 7e 38 movq \(%r8\),%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 7e 38 movq \(%rax\),%xmm15 -[ ]*[a-f0-9]+: f3 45 0f 7e 00 movq \(%r8\),%xmm8 -[ ]*[a-f0-9]+: f3 44 0f 7e 00 movq \(%rax\),%xmm8 -[ ]*[a-f0-9]+: f3 41 0f 7e 38 movq \(%r8\),%xmm7 -[ ]*[a-f0-9]+: f3 0f 7e 38 movq \(%rax\),%xmm7 -[ ]*[a-f0-9]+: f3 0f 7e c0 movq %xmm0,%xmm0 -[ ]*[a-f0-9]+: f3 45 0f 7e ff movq %xmm15,%xmm15 -[ ]*[a-f0-9]+: f3 45 0f 7e c7 movq %xmm15,%xmm8 -[ ]*[a-f0-9]+: f3 41 0f 7e ff movq %xmm15,%xmm7 -[ ]*[a-f0-9]+: f3 41 0f 7e c7 movq %xmm15,%xmm0 -[ ]*[a-f0-9]+: f3 45 0f 7e f8 movq %xmm8,%xmm15 -[ ]*[a-f0-9]+: f3 45 0f 7e c0 movq %xmm8,%xmm8 -[ ]*[a-f0-9]+: f3 41 0f 7e f8 movq %xmm8,%xmm7 -[ ]*[a-f0-9]+: f3 41 0f 7e c0 movq %xmm8,%xmm0 -[ ]*[a-f0-9]+: f3 44 0f 7e ff movq %xmm7,%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 7e c7 movq %xmm7,%xmm8 -[ ]*[a-f0-9]+: f3 0f 7e ff movq %xmm7,%xmm7 -[ ]*[a-f0-9]+: f3 0f 7e c7 movq %xmm7,%xmm0 -[ ]*[a-f0-9]+: f3 44 0f 7e f8 movq %xmm0,%xmm15 -[ ]*[a-f0-9]+: f3 44 0f 7e c0 movq %xmm0,%xmm8 -[ ]*[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7 -[ ]*[a-f0-9]+: 66 41 0f d6 00 movq %xmm0,\(%r8\) -[ ]*[a-f0-9]+: 66 0f d6 00 movq %xmm0,\(%rax\) -[ ]*[a-f0-9]+: 66 45 0f d6 38 movq %xmm15,\(%r8\) -[ ]*[a-f0-9]+: 66 44 0f d6 38 movq %xmm15,\(%rax\) -[ ]*[a-f0-9]+: 66 45 0f d6 00 movq %xmm8,\(%r8\) -[ ]*[a-f0-9]+: 66 44 0f d6 00 movq %xmm8,\(%rax\) -[ ]*[a-f0-9]+: 66 41 0f d6 38 movq %xmm7,\(%r8\) -[ ]*[a-f0-9]+: 41 0f 6e 00 movd \(%r8\),%mm0 -[ ]*[a-f0-9]+: 0f 6e 00 movd \(%rax\),%mm0 -[ ]*[a-f0-9]+: 41 0f 6e 38 movd \(%r8\),%mm7 -[ ]*[a-f0-9]+: 0f 6e 38 movd \(%rax\),%mm7 -[ ]*[a-f0-9]+: 0f 6e c0 movd %eax,%mm0 -[ ]*[a-f0-9]+: 0f 6e f8 movd %eax,%mm7 -[ ]*[a-f0-9]+: 41 0f 7e 00 movd %mm0,\(%r8\) -[ ]*[a-f0-9]+: 0f 7e 00 movd %mm0,\(%rax\) -[ ]*[a-f0-9]+: 41 0f 7e 38 movd %mm7,\(%r8\) -[ ]*[a-f0-9]+: 0f 7e 38 movd %mm7,\(%rax\) -[ ]*[a-f0-9]+: 0f 7e c0 movd %mm0,%eax -[ ]*[a-f0-9]+: 0f 7e f8 movd %mm7,%eax -[ ]*[a-f0-9]+: 41 0f 6f 00 movq \(%r8\),%mm0 -[ ]*[a-f0-9]+: 0f 6f 00 movq \(%rax\),%mm0 -[ ]*[a-f0-9]+: 41 0f 6f 38 movq \(%r8\),%mm7 -[ ]*[a-f0-9]+: 0f 6f 38 movq \(%rax\),%mm7 -[ ]*[a-f0-9]+: 41 0f 7f 00 movq %mm0,\(%r8\) -[ ]*[a-f0-9]+: 0f 7f 00 movq %mm0,\(%rax\) -[ ]*[a-f0-9]+: 41 0f 7f 38 movq %mm7,\(%r8\) -[ ]*[a-f0-9]+: 0f 7f 38 movq %mm7,\(%rax\) -[ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\) -[ ]*[a-f0-9]+: 8f 00 popq \(%rax\) -[ ]*[a-f0-9]+: 9d popfq -[ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\) -[ ]*[a-f0-9]+: ff 30 pushq \(%rax\) -[ ]*[a-f0-9]+: 9c pushfq -[ ]*[a-f0-9]+: 0f 77 emms -[ ]*[a-f0-9]+: 0f 0e femms -[ ]*[a-f0-9]+: 0f 08 invd -[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\) -[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\) -[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\) -[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\) -[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\) -[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\) -[ ]*[a-f0-9]+: 0f 00 c0 sldt %eax -[ ]*[a-f0-9]+: 0f 00 c0 sldt %eax -[ ]*[a-f0-9]+: 66 0f 00 c0 sldt %ax -[ ]*[a-f0-9]+: 0f 00 00 sldt \(%rax\) -[ ]*[a-f0-9]+: e6 00 out %al,\$0x0 -[ ]*[a-f0-9]+: 66 e7 00 out %ax,\$0x0 -[ ]*[a-f0-9]+: e7 00 out %eax,\$0x0 -[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -[ ]*[a-f0-9]+: 87 c0 xchg %eax,%eax -[ ]*[a-f0-9]+: 90 nop -[ ]*[a-f0-9]+: 48 90 rex.W nop -[ ]*[a-f0-9]+: 49 90 xchg %rax,%r8 -[ ]*[a-f0-9]+: 41 90 xchg %eax,%r8d -[ ]*[a-f0-9]+: 41 90 xchg %eax,%r8d -[ ]*[a-f0-9]+: 41 91 xchg %eax,%r9d -[ ]*[a-f0-9]+: 41 91 xchg %eax,%r9d -[ ]*[a-f0-9]+: 93 xchg %eax,%ebx -[ ]*[a-f0-9]+: 93 xchg %eax,%ebx -[ ]*[a-f0-9]+: 66 41 90 xchg %ax,%r8w -[ ]*[a-f0-9]+: 66 41 90 xchg %ax,%r8w -[ ]*[a-f0-9]+: 66 41 91 xchg %ax,%r9w -[ ]*[a-f0-9]+: 66 41 91 xchg %ax,%r9w -[ ]*[a-f0-9]+: 48 0f 01 e0 smsw %rax -[ ]*[a-f0-9]+: 0f 01 e0 smsw %eax -[ ]*[a-f0-9]+: 66 0f 01 e0 smsw %ax -[ ]*[a-f0-9]+: 0f 01 20 smsw \(%rax\) -[ ]*[a-f0-9]+: 0f 00 c8 str %eax -[ ]*[a-f0-9]+: 0f 00 c8 str %eax -[ ]*[a-f0-9]+: 66 0f 00 c8 str %ax -[ ]*[a-f0-9]+: 0f 00 08 str \(%rax\) -[ ]*[a-f0-9]+: 0f 05 syscall -[ ]*[a-f0-9]+: 0f 07 sysret -[ ]*[a-f0-9]+: 0f 01 f8 swapgs -[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222 -[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl -[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx -[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx -[ ]*[a-f0-9]+: 48 f7 c9 08 00 00 00 test \$(0x)?0*8,%rcx -#pass +#dump: ../x86-64-opcode.d diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d index a2e9a71..35829f4 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.d +++ b/gas/testsuite/gas/i386/x86-64-opcode.d @@ -254,9 +254,13 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 0f 7f 38 movq %mm7,\(%rax\) [ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\) [ ]*[a-f0-9]+: 8f 00 popq \(%rax\) +[ ]*[a-f0-9]+: 0f a1 popq %fs +[ ]*[a-f0-9]+: 0f a9 popq %gs [ ]*[a-f0-9]+: 9d popfq [ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\) [ ]*[a-f0-9]+: ff 30 pushq \(%rax\) +[ ]*[a-f0-9]+: 0f a0 pushq %fs +[ ]*[a-f0-9]+: 0f a8 pushq %gs [ ]*[a-f0-9]+: 9c pushfq [ ]*[a-f0-9]+: 0f 77 emms [ ]*[a-f0-9]+: 0f 0e femms diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s index 5df5d13..8d4a6ed 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.s +++ b/gas/testsuite/gas/i386/x86-64-opcode.s @@ -322,11 +322,15 @@ # POP POPq (%r8) # -- -- -- 41 8F 00 ; REX to access upper reg. POPq (%rax) # -- -- -- -- 8F 00 + POP %fs # -- -- -- -- 0F A1 + POP %gs # -- -- -- -- 0F A9 POPFQ # -- -- -- -- 9D # PUSH PUSHq (%r8) # -- -- -- 41 FF 30 ; REX to access upper reg. PUSHq (%rax) # -- -- -- -- FF 30 + PUSH %fs # -- -- -- -- 0F A0 + PUSH %gs # -- -- -- -- 0F A8 PUSHFQ # -- -- -- -- 9C |