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-rw-r--r--gas/testsuite/ChangeLog13
-rw-r--r--gas/testsuite/gas/mips/cp0-names-mips32r2.d42
-rw-r--r--gas/testsuite/gas/mips/hwr-names-mips32r2.d43
-rw-r--r--gas/testsuite/gas/mips/hwr-names-numeric.d43
-rw-r--r--gas/testsuite/gas/mips/hwr-names.s44
-rw-r--r--gas/testsuite/gas/mips/mips.exp11
-rw-r--r--gas/testsuite/gas/mips/mips32r2-ill.l15
-rw-r--r--gas/testsuite/gas/mips/mips32r2-ill.s60
-rw-r--r--gas/testsuite/gas/mips/mips32r2.d46
-rw-r--r--gas/testsuite/gas/mips/mips32r2.s81
10 files changed, 398 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b4c687c..93bb537 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2002-12-29 Chris Demetriou <cgd@broadcom.com>
+
+ * gas/mips/cp0-names-mips32r2.d: New test.
+ * gas/mips/hwr-names-mips32r2.d: New test.
+ * gas/mips/hwr-names-numeric.d: New test.
+ * gas/mips/hwr-names.s: New test source file.
+ * gas/mips/mips32r2.d: New test.
+ * gas/mips/mips32r2.s: New test source file.
+ * gas/mips/mips32r2-ill.l: New test.
+ * gas/mips/mips32r2-ill.s: New test source file.
+ * gas/mips/mips.exp: Add mips32r2 architecture data array
+ entry. Run new tests mentioned above.
+
2002-12-24 Dmitry Diky <diwil@mail.ru>
* gas/msp430: New directory.
diff --git a/gas/testsuite/gas/mips/cp0-names-mips32r2.d b/gas/testsuite/gas/mips/cp0-names-mips32r2.d
new file mode 100644
index 0000000..edd67d9
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0-names-mips32r2.d
@@ -0,0 +1,42 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=mips32r2
+#name: MIPS CP0 register disassembly (mips32r2)
+#source: cp0-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800000 mtc0 \$0,c0_index
+0+0004 <[^>]*> 40800800 mtc0 \$0,c0_random
+0+0008 <[^>]*> 40801000 mtc0 \$0,c0_entrylo0
+0+000c <[^>]*> 40801800 mtc0 \$0,c0_entrylo1
+0+0010 <[^>]*> 40802000 mtc0 \$0,c0_context
+0+0014 <[^>]*> 40802800 mtc0 \$0,c0_pagemask
+0+0018 <[^>]*> 40803000 mtc0 \$0,c0_wired
+0+001c <[^>]*> 40803800 mtc0 \$0,c0_hwrena
+0+0020 <[^>]*> 40804000 mtc0 \$0,c0_badvaddr
+0+0024 <[^>]*> 40804800 mtc0 \$0,c0_count
+0+0028 <[^>]*> 40805000 mtc0 \$0,c0_entryhi
+0+002c <[^>]*> 40805800 mtc0 \$0,c0_compare
+0+0030 <[^>]*> 40806000 mtc0 \$0,c0_status
+0+0034 <[^>]*> 40806800 mtc0 \$0,c0_cause
+0+0038 <[^>]*> 40807000 mtc0 \$0,c0_epc
+0+003c <[^>]*> 40807800 mtc0 \$0,c0_prid
+0+0040 <[^>]*> 40808000 mtc0 \$0,c0_config
+0+0044 <[^>]*> 40808800 mtc0 \$0,c0_lladdr
+0+0048 <[^>]*> 40809000 mtc0 \$0,c0_watchlo
+0+004c <[^>]*> 40809800 mtc0 \$0,c0_watchhi
+0+0050 <[^>]*> 4080a000 mtc0 \$0,c0_xcontext
+0+0054 <[^>]*> 4080a800 mtc0 \$0,\$21
+0+0058 <[^>]*> 4080b000 mtc0 \$0,\$22
+0+005c <[^>]*> 4080b800 mtc0 \$0,c0_debug
+0+0060 <[^>]*> 4080c000 mtc0 \$0,c0_depc
+0+0064 <[^>]*> 4080c800 mtc0 \$0,c0_perfcnt
+0+0068 <[^>]*> 4080d000 mtc0 \$0,c0_errctl
+0+006c <[^>]*> 4080d800 mtc0 \$0,c0_cacheerr
+0+0070 <[^>]*> 4080e000 mtc0 \$0,c0_taglo
+0+0074 <[^>]*> 4080e800 mtc0 \$0,c0_taghi
+0+0078 <[^>]*> 4080f000 mtc0 \$0,c0_errorepc
+0+007c <[^>]*> 4080f800 mtc0 \$0,c0_desave
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/hwr-names-mips32r2.d b/gas/testsuite/gas/mips/hwr-names-mips32r2.d
new file mode 100644
index 0000000..93333e3
--- /dev/null
+++ b/gas/testsuite/gas/mips/hwr-names-mips32r2.d
@@ -0,0 +1,43 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r2 -M gpr-names=numeric,hwr-names=mips32r2
+#name: MIPS HWR disassembly (mips32r2)
+#as: -mips32r2
+#source: hwr-names.s
+
+# Check objdump's handling of -M hwr-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c00003b rdhwr \$0,hwr_cpunum
+0+0004 <[^>]*> 7c00083b rdhwr \$0,hwr_synci_step
+0+0008 <[^>]*> 7c00103b rdhwr \$0,hwr_cc
+0+000c <[^>]*> 7c00183b rdhwr \$0,hwr_ccres
+0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4
+0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5
+0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6
+0+001c <[^>]*> 7c00383b rdhwr \$0,\$7
+0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8
+0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9
+0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10
+0+002c <[^>]*> 7c00583b rdhwr \$0,\$11
+0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12
+0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13
+0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14
+0+003c <[^>]*> 7c00783b rdhwr \$0,\$15
+0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16
+0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17
+0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18
+0+004c <[^>]*> 7c00983b rdhwr \$0,\$19
+0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20
+0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21
+0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22
+0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23
+0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24
+0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25
+0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26
+0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27
+0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28
+0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29
+0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30
+0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/hwr-names-numeric.d b/gas/testsuite/gas/mips/hwr-names-numeric.d
new file mode 100644
index 0000000..71a9700
--- /dev/null
+++ b/gas/testsuite/gas/mips/hwr-names-numeric.d
@@ -0,0 +1,43 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r2 -M gpr-names=numeric,hwr-names=numeric
+#name: MIPS HWR disassembly (numeric)
+#as: -mips32r2
+#source: hwr-names.s
+
+# Check objdump's handling of -M hwr-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c00003b rdhwr \$0,\$0
+0+0004 <[^>]*> 7c00083b rdhwr \$0,\$1
+0+0008 <[^>]*> 7c00103b rdhwr \$0,\$2
+0+000c <[^>]*> 7c00183b rdhwr \$0,\$3
+0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4
+0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5
+0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6
+0+001c <[^>]*> 7c00383b rdhwr \$0,\$7
+0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8
+0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9
+0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10
+0+002c <[^>]*> 7c00583b rdhwr \$0,\$11
+0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12
+0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13
+0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14
+0+003c <[^>]*> 7c00783b rdhwr \$0,\$15
+0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16
+0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17
+0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18
+0+004c <[^>]*> 7c00983b rdhwr \$0,\$19
+0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20
+0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21
+0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22
+0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23
+0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24
+0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25
+0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26
+0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27
+0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28
+0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29
+0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30
+0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/hwr-names.s b/gas/testsuite/gas/mips/hwr-names.s
new file mode 100644
index 0000000..f0e056b
--- /dev/null
+++ b/gas/testsuite/gas/mips/hwr-names.s
@@ -0,0 +1,44 @@
+# source file to test objdump's disassembly using various styles of
+# HWR (hardware register) names.
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ rdhwr $0, $0
+ rdhwr $0, $1
+ rdhwr $0, $2
+ rdhwr $0, $3
+ rdhwr $0, $4
+ rdhwr $0, $5
+ rdhwr $0, $6
+ rdhwr $0, $7
+ rdhwr $0, $8
+ rdhwr $0, $9
+ rdhwr $0, $10
+ rdhwr $0, $11
+ rdhwr $0, $12
+ rdhwr $0, $13
+ rdhwr $0, $14
+ rdhwr $0, $15
+ rdhwr $0, $16
+ rdhwr $0, $17
+ rdhwr $0, $18
+ rdhwr $0, $19
+ rdhwr $0, $20
+ rdhwr $0, $21
+ rdhwr $0, $22
+ rdhwr $0, $23
+ rdhwr $0, $24
+ rdhwr $0, $25
+ rdhwr $0, $26
+ rdhwr $0, $27
+ rdhwr $0, $28
+ rdhwr $0, $29
+ rdhwr $0, $30
+ rdhwr $0, $31
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 29951eb..d6ebe4e 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -343,6 +343,10 @@ mips_arch_create mips5 64 mips4 {} \
mips_arch_create mips32 32 mips2 {} \
{ -march=mips32 -mtune=mips32 } { -mmips:isa32 } \
{ mipsisa32-*-* mipsisa32el-*-* }
+mips_arch_create mips32r2 32 mips32 { ror } \
+ { -march=mips32r2 -mtune=mips32r2 } \
+ { -mmips:isa32r2 } \
+ { mipsisa32r2-*-* mipsisa32r2el-*-* }
mips_arch_create mips64 64 mips5 { mips32 } \
{ -march=mips64 -mtune=mips64 } { -mmips:isa64 } \
{ mipsisa64-*-* mipsisa64el-*-* }
@@ -522,6 +526,9 @@ if { [istarget mips*-*-*] } then {
run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
+ run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
+ run_list_test_arches "mips32r2-ill" "" [mips_arch_list_matching mips32r2]
+
run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
run_dump_test "mips64-mips3d"
@@ -610,6 +617,10 @@ if { [istarget mips*-*-*] } then {
run_dump_test "cp0-names-numeric"
run_dump_test "cp0-names-mips32"
+ run_dump_test "cp0-names-mips32r2"
run_dump_test "cp0-names-mips64"
run_dump_test "cp0-names-sb1"
+
+ run_dump_test "hwr-names-numeric"
+ run_dump_test "hwr-names-mips32r2"
}
diff --git a/gas/testsuite/gas/mips/mips32r2-ill.l b/gas/testsuite/gas/mips/mips32r2-ill.l
new file mode 100644
index 0000000..66223a2
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r2-ill.l
@@ -0,0 +1,15 @@
+.*: Assembler messages:
+.*:12: Error: Improper position \([0-9]*\)
+.*:15: Error: Improper position \(32\)
+.*:18: Error: Improper extract size \(0, position 0\)
+.*:21: Error: Improper extract size \(33, position 0\)
+.*:24: Error: Improper extract size \(0, position 0\)
+.*:27: Error: Improper extract size \(2, position 31\)
+.*:30: Error: Improper position \([0-9]*\)
+.*:33: Error: Improper position \(32\)
+.*:36: Error: Improper insert size \(0, position 0\)
+.*:39: Error: Improper insert size \(33, position 0\)
+.*:42: Error: Improper insert size \(0, position 0\)
+.*:45: Error: Improper insert size \(2, position 31\)
+.*:54: Warning: Float register should be even, was 1
+.*:57: Warning: Float register should be even, was 1
diff --git a/gas/testsuite/gas/mips/mips32r2-ill.s b/gas/testsuite/gas/mips/mips32r2-ill.s
new file mode 100644
index 0000000..d350cc9
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r2-ill.s
@@ -0,0 +1,60 @@
+# source file to test illegal mips32r2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # insert and extract position/size checks:
+
+ # ext constraint: 0 <= pos < 32
+ ext $4, $5, -1, 1 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 32, 1 # error
+
+ # ext constraint: 0 < size <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 0, 32
+ ext $4, $5, 0, 33 # error
+
+ # ext constraint: 0 < (pos+size) <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 31, 2 # error
+
+ # ins constraint: 0 <= pos < 32
+ ins $4, $5, -1, 1 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 32, 1 # error
+
+ # ins constraint: 0 < size <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 0, 32
+ ins $4, $5, 0, 33 # error
+
+ # ins constraint: 0 < (pos+size) <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 31, 2 # error
+
+ # FP register checks.
+ #
+ # Even registers are supported w/ 32-bit FPU, odd
+ # registers supported only for 64-bit FPU.
+ # This file tests 32-bit FPU.
+
+ mfhc1 $17, $f0
+ mfhc1 $17, $f1 # warn
+
+ mthc1 $17, $f0
+ mthc1 $17, $f1 # warn
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff --git a/gas/testsuite/gas/mips/mips32r2.d b/gas/testsuite/gas/mips/mips32r2.d
new file mode 100644
index 0000000..196cb41
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r2.d
@@ -0,0 +1,46 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 instructions
+
+# Check MIPS32 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 000000c0 ehb
+0+0004 <[^>]*> 7ca43980 ext \$4,\$5,0x6,0x8
+0+0008 <[^>]*> 7ca46984 ins \$4,\$5,0x6,0x8
+0+000c <[^>]*> 0100fc09 jalr.hb \$8
+0+0010 <[^>]*> 0120a409 jalr.hb \$20,\$9
+0+0014 <[^>]*> 01000408 jr.hb \$8
+0+0018 <[^>]*> 7c0a003b rdhwr \$10,\$0
+0+001c <[^>]*> 7c0b083b rdhwr \$11,\$1
+0+0020 <[^>]*> 7c0c103b rdhwr \$12,\$2
+0+0024 <[^>]*> 7c0d183b rdhwr \$13,\$3
+0+0028 <[^>]*> 7c0e203b rdhwr \$14,\$4
+0+002c <[^>]*> 7c0f283b rdhwr \$15,\$5
+0+0030 <[^>]*> 002acf02 ror \$25,\$10,0x1c
+0+0034 <[^>]*> 002ac902 ror \$25,\$10,0x4
+0+0038 <[^>]*> 0004c823 negu \$25,\$4
+0+003c <[^>]*> 032ac846 rorv \$25,\$10,\$25
+0+0040 <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0044 <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0048 <[^>]*> 7c073c20 seb \$7,\$7
+0+004c <[^>]*> 7c0a4420 seb \$8,\$10
+0+0050 <[^>]*> 7c073e20 seh \$7,\$7
+0+0054 <[^>]*> 7c0a4620 seh \$8,\$10
+0+0058 <[^>]*> 055f5555 synci 21845\(\$10\)
+0+005c <[^>]*> 7c0738a0 wsbh \$7,\$7
+0+0060 <[^>]*> 7c0a40a0 wsbh \$8,\$10
+0+0064 <[^>]*> 41606000 di
+0+0068 <[^>]*> 41606000 di
+0+006c <[^>]*> 416a6000 di \$10
+0+0070 <[^>]*> 41606020 ei
+0+0074 <[^>]*> 41606020 ei
+0+0078 <[^>]*> 416a6020 ei \$10
+0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
+0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
+0+0084 <[^>]*> 44710000 mfhc1 \$17,\$f0
+0+0088 <[^>]*> 44f10000 mthc1 \$17,\$f0
+0+008c <[^>]*> 48715555 mfhc2 \$17,0x5555
+0+0090 <[^>]*> 48f15555 mthc2 \$17,0x5555
+ ...
diff --git a/gas/testsuite/gas/mips/mips32r2.s b/gas/testsuite/gas/mips/mips32r2.s
new file mode 100644
index 0000000..4731fc4
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r2.s
@@ -0,0 +1,81 @@
+# source file to test assembly of mips32r2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # unprivileged CPU instructions
+
+ ehb
+
+ ext $4, $5, 6, 8
+
+ ins $4, $5, 6, 8
+
+ jalr.hb $8
+ jalr.hb $20, $9
+
+ jr.hb $8
+
+ # Note, further testing of rdhwr is done in hwr-names-mips32r2.d
+ rdhwr $10, $0
+ rdhwr $11, $1
+ rdhwr $12, $2
+ rdhwr $13, $3
+ rdhwr $14, $4
+ rdhwr $15, $5
+
+ # This file checks that in fact HW rotate will
+ # be used for this arch, and checks assembly
+ # of the official MIPS mnemonics. (Note that disassembly
+ # uses the traditional "ror" and "rorv" mnemonics.)
+ # Additional rotate tests are done by rol-hw.d.
+ rotl $25, $10, 4
+ rotr $25, $10, 4
+ rotl $25, $10, $4
+ rotr $25, $10, $4
+ rotrv $25, $10, $4
+
+ seb $7
+ seb $8, $10
+
+ seh $7
+ seh $8, $10
+
+ synci 0x5555($10)
+
+ wsbh $7
+ wsbh $8, $10
+
+ # cp0 instructions
+
+ di
+ di $0
+ di $10
+
+ ei
+ ei $0
+ ei $10
+
+ rdpgpr $10, $25
+
+ wrpgpr $10, $25
+
+ # FPU (cp1) instructions
+ #
+ # Even registers are supported w/ 32-bit FPU, odd
+ # registers supported only for 64-bit FPU.
+ # Only the 32-bit FPU instructions are tested here.
+
+ mfhc1 $17, $f0
+ mthc1 $17, $f0
+
+ # cp2 instructions
+
+ mfhc2 $17, 0x5555
+ mthc2 $17, 0x5555
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
generated by cgit v1.1 at 2025-01-22 03:40:32 +0000