diff options
Diffstat (limited to 'gas/doc/c-mips.texi')
| -rw-r--r-- | gas/doc/c-mips.texi | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index e56156e..b9902ff 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -13,7 +13,8 @@ @cindex MIPS processor @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several -different @sc{mips} processors, and MIPS ISA levels I through IV. For +different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, +and MIPS64. For information about the @sc{mips} instruction set, see @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language @@ -60,13 +61,18 @@ to select big-endian output, and @samp{-EL} for little-endian. @itemx -mips2 @itemx -mips3 @itemx -mips4 +@itemx -mips5 @itemx -mips32 +@itemx -mips64 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the -@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and -@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32) -processor. You can also switch instruction sets during the +@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and +@sc{r10000} processors. +@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond +to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA +processors, respectively. +You can also switch instruction sets during the assembly; see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 @@ -239,8 +245,9 @@ assembly language programmers! @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the @sc{mips} Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1 -to 4 and 32 make the assembler accept instructions for the corresponding +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64. +The values 1 to 5, 32, and 64 make the assembler accept instructions +for the corresponding @sc{isa} level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions are permitted, but also how certain macros are expanded. @code{.set mips0} restores the |