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Diffstat (limited to 'gas/doc/c-avr.texi')
| -rw-r--r-- | gas/doc/c-avr.texi | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/gas/doc/c-avr.texi b/gas/doc/c-avr.texi index f829e79..e419964 100644 --- a/gas/doc/c-avr.texi +++ b/gas/doc/c-avr.texi @@ -18,6 +18,7 @@ * AVR Options:: Options * AVR Syntax:: Syntax * AVR Opcodes:: Opcodes +* AVR Pseudo Instructions:: Pseudo Instructions @end menu @node AVR Options @@ -151,6 +152,10 @@ Disable support for link-time relaxation. The assembler will resolve relocations when it can, and may be able to better compress some debug information. +@cindex @code{-mgcc-isr} command line option, AVR +@item -mgcc-isr +Enable the @code{__gcc_isr} pseudo instruction. + @end table @@ -441,3 +446,60 @@ The following table summarizes the AVR opcodes, and their arguments. 1001010100011001 eicall 1001010000011001 eijmp @end smallexample + +@node AVR Pseudo Instructions +@section Pseudo Instructions + +The only available pseudo-instruction @code{__gcc_isr} can be activated by +option @option{-mgcc-isr}. + +@table @code + +@item __gcc_isr 1 +Emit code chunk to be used in avr-gcc ISR prologue. +It will expand to at most six 1-word instructions, all optional: +push of @code{tmp_reg}, push of @code{SREG}, +push and clear of @code{zero_reg}, push of @var{Reg}. + +@item __gcc_isr 2 +Emit code chunk to be used in an avr-gcc ISR epilogue. +It will expand to at most five 1-word instructions, all optional: +pop of @var{Reg}, pop of @code{zero_reg}, +pop of @code{SREG}, pop of @code{tmp_reg}. + +@item __gcc_isr 0, @var{Reg} +Finish avr-gcc ISR function. Scan code since the last prologue +for usage of: @code{SREG}, @code{tmp_reg}, @code{zero_reg}. +Prologue chunk and epilogue chunks will be replaced by appropriate code +to save / restore @code{SREG}, @code{tmp_reg}, @code{zero_reg} and @var{Reg}. + +@end table + +Example input: + +@example +__vector1: + __gcc_isr 1 + lds r24, var + inc r24 + sts var, r24 + __gcc_isr 2 + reti + __gcc_isr 0, r24 +@end example + +Example output: + +@example +00000000 <__vector1>: + 0: 8f 93 push r24 + 2: 8f b7 in r24, 0x3f + 4: 8f 93 push r24 + 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> + a: 83 95 inc r24 + c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> + 10: 8f 91 pop r24 + 12: 8f bf out 0x3f, r24 + 14: 8f 91 pop r24 + 16: 18 95 reti +@end example |