7 files changed, 112 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 45ec453..057e309 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,12 @@
+2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* testsuite/binutils-all/mips/mips-ase-1.d: New test.
+	* testsuite/binutils-all/mips/mips-ase-2.d: New test.
+	* testsuite/binutils-all/mips/mips-ase-3.d: New test.
+	* testsuite/binutils-all/mips/mips-ase-1.s: New test source.
+	* testsuite/binutils-all/mips/mips-ase-2.s: New test source.
+	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
+
 2016-12-13  Jiong Wang  <jiong.wang@arm.com>
 
 	* readelf.c (is_32bit_abs_reloc): Recognize R_AARCH64_P32_ABS32.
diff --git a/binutils/testsuite/binutils-all/mips/mips-ase-1.d b/binutils/testsuite/binutils-all/mips/mips-ase-1.d
new file mode 100644
index 0000000..d9d5839
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips-ase-1.d
@@ -0,0 +1,29 @@
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 1
+#as: -32
+
+# Verify that in the absence of its ASE flag MDMX code is not disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+!private flags = .*mdmx.*
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r2
+GPR size: 32
+CPR1 size: 64
+CPR2 size: 0
+FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
+ISA Extension: None
+ASEs:
+	None
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b 	0x7aa2080b
+[0-9a-f]+ <[^>]*> 46c520c0 	add\.ps	\$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 	addr\.ps	\$f6,\$f7,\$f8
+	\.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips-ase-1.s b/binutils/testsuite/binutils-all/mips/mips-ase-1.s
new file mode 100644
index 0000000..c1d7671
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips-ase-1.s
@@ -0,0 +1,12 @@
+	.module	mips64r2
+	.module	fp=64
+	.set	mdmx
+	.set	mips3d
+foo:
+	add.qh	$v0, $v1, $v2
+	add.ps	$f3, $f4, $f5
+	addr.ps	$f6, $f7, $f8
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16
diff --git a/binutils/testsuite/binutils-all/mips/mips-ase-2.d b/binutils/testsuite/binutils-all/mips/mips-ase-2.d
new file mode 100644
index 0000000..baf80dd
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips-ase-2.d
@@ -0,0 +1,29 @@
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 2
+#as: -32
+
+# Verify that in the presence of its ASE flag MDMX code is disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+private flags = .[8-f]......: .*mdmx.*
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r2
+GPR size: 32
+CPR1 size: 64
+CPR2 size: 0
+FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
+ISA Extension: None
+ASEs:
+	MDMX ASE
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b 	add\.qh	\$v0,\$v1,\$v2
+[0-9a-f]+ <[^>]*> 46c520c0 	add\.ps	\$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 	addr\.ps	\$f6,\$f7,\$f8
+	\.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips-ase-2.s b/binutils/testsuite/binutils-all/mips/mips-ase-2.s
new file mode 100644
index 0000000..54adac2
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips-ase-2.s
@@ -0,0 +1,12 @@
+	.module	mips64r2
+	.module	fp=64
+	.module	mdmx
+	.set	mips3d
+foo:
+	add.qh	$v0, $v1, $v2
+	add.ps	$f3, $f4, $f5
+	addr.ps	$f6, $f7, $f8
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16
diff --git a/binutils/testsuite/binutils-all/mips/mips-ase-3.d b/binutils/testsuite/binutils-all/mips/mips-ase-3.d
new file mode 100644
index 0000000..a52a647
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips-ase-3.d
@@ -0,0 +1,18 @@
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 3
+#as: -32
+#objcopy: -R .MIPS.abiflags
+#source: mips-ase-2.s
+
+# Verify that in the presence of its ASE flag MDMX code is disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+private flags = .[8-f]......: .*mdmx.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b 	add\.qh	\$v0,\$v1,\$v2
+[0-9a-f]+ <[^>]*> 46c520c0 	add\.ps	\$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 	addr\.ps	\$f6,\$f7,\$f8
+	\.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp
index f3d956f..143fbc4 100644
--- a/binutils/testsuite/binutils-all/mips/mips.exp
+++ b/binutils/testsuite/binutils-all/mips/mips.exp
@@ -20,6 +20,9 @@ if ![istarget mips*-*-*] {
 }
 
 if [is_elf_format] {
+    run_dump_test "mips-ase-1"
+    run_dump_test "mips-ase-2"
+    run_dump_test "mips-ase-3"
     run_dump_test "mixed-mips16"
     run_dump_test "mixed-micromips"
     run_dump_test "mixed-mips16-micromips"