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-rw-r--r--binutils/ChangeLog6
-rw-r--r--binutils/testsuite/binutils-all/aarch64/in-order-all.d6
-rw-r--r--binutils/testsuite/binutils-all/aarch64/out-of-order-all.d6
3 files changed, 12 insertions, 6 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 3cd5095..d4fa9fb 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-30 Alex Coplan <alex.coplan@arm.com>
+
+ * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
+ disassembly.
+ * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.
+
2020-04-30 Nick Clifton <nickc@redhat.com>
* testsuite/lib/binutils-common.exp (check_pie_support): New
diff --git a/binutils/testsuite/binutils-all/aarch64/in-order-all.d b/binutils/testsuite/binutils-all/aarch64/in-order-all.d
index a484ca7..a6daea8 100644
--- a/binutils/testsuite/binutils-all/aarch64/in-order-all.d
+++ b/binutils/testsuite/binutils-all/aarch64/in-order-all.d
@@ -10,7 +10,7 @@ Disassembly of section \.func1:
.+ <v1>:
[^:]+: 8b010000 add x0, x0, x1
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0
Disassembly of section \.func2:
@@ -25,12 +25,12 @@ Disassembly of section \.func3:
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0
Disassembly of section \.rodata:
.+ <\.rodata>:
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0
Disassembly of section .global:
diff --git a/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d b/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d
index d3aa79e..955d190 100644
--- a/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d
+++ b/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d
@@ -20,7 +20,7 @@ Disassembly of section \.func1:
.+ <v1>:
[^:]+: 8b010000 add x0, x0, x1
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0
Disassembly of section \.func3:
@@ -30,9 +30,9 @@ Disassembly of section \.func3:
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0
Disassembly of section \.rodata:
.+ <\.rodata>:
-[^:]+: 00000000 \.inst 0x00000000 ; undefined
+[^:]+: 00000000 udf #0