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Diffstat (limited to 'bfd/elfxx-riscv.c')
-rw-r--r--bfd/elfxx-riscv.c79
1 files changed, 67 insertions, 12 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 44dd624..26ec664 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1213,7 +1213,14 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zcd", "+d,+zca", check_implicit_always},
{"zcf", "+f,+zca", check_implicit_always},
{"zcmp", "+zca", check_implicit_always},
-
+ {"zcmop", "+zca", check_implicit_always},
+
+ {"shcounterenw", "+h", check_implicit_always},
+ {"shgatpa", "+h", check_implicit_always},
+ {"shtvala", "+h", check_implicit_always},
+ {"shvsatpa", "+h", check_implicit_always},
+ {"shvstvala", "+h", check_implicit_always},
+ {"shvstvecd", "+h", check_implicit_always},
{"h", "+zicsr", check_implicit_always},
{"zhinx", "+zhinxmin", check_implicit_always},
{"zhinxmin", "+zfinx", check_implicit_always},
@@ -1253,9 +1260,16 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"ssaia", "+zicsr", check_implicit_always},
{"sscsrind", "+zicsr", check_implicit_always},
{"sscofpmf", "+zicsr", check_implicit_always},
+ {"sscounterenw", "+zicsr", check_implicit_always},
{"ssstateen", "+zicsr", check_implicit_always},
{"sstc", "+zicsr", check_implicit_always},
+ {"sstvala", "+zicsr", check_implicit_always},
+ {"sstvecd", "+zicsr", check_implicit_always},
+ {"ssu64xl", "+zicsr", check_implicit_always},
+
+ {"svade", "+zicsr", check_implicit_always},
{"svadu", "+zicsr", check_implicit_always},
+ {"svbare", "+zicsr", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1314,6 +1328,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1326,7 +1345,10 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
+ {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1400,23 +1422,38 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{
+ {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1430,11 +1467,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
- {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
- {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"xcvsimd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2353,7 +2392,7 @@ riscv_update_subset1 (riscv_parse_subset_t *rps,
const char *implicit_exts)
{
const char *p = implicit_exts;
- const char *errmsg_internal = explicit_subset == NULL ? "" : "internal: ";
+ const char *errmsg_internal = explicit_subset == NULL ? "" : _("internal: ");
const char *errmsg_caller = explicit_subset == NULL
? ".option arch" : "riscv_implicit_subsets";
@@ -2523,6 +2562,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zca")));
case INSN_CLASS_ZIHINTPAUSE:
return riscv_subset_supports (rps, "zihintpause");
+ case INSN_CLASS_ZIMOP:
+ return riscv_subset_supports (rps, "zimop");
case INSN_CLASS_M:
return riscv_subset_supports (rps, "m");
case INSN_CLASS_ZMMUL:
@@ -2675,22 +2716,28 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZCB_AND_ZMMUL:
return (riscv_subset_supports (rps, "zcb")
&& riscv_subset_supports (rps, "zmmul"));
+ case INSN_CLASS_ZCMOP:
+ return riscv_subset_supports (rps, "zcmop");
case INSN_CLASS_ZCMP:
return riscv_subset_supports (rps, "zcmp");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
- case INSN_CLASS_XCVMAC:
- return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
- case INSN_CLASS_XCVELW:
- return riscv_subset_supports (rps, "xcvelw");
case INSN_CLASS_XCVBI:
return riscv_subset_supports (rps, "xcvbi");
+ case INSN_CLASS_XCVBITMANIP:
+ return riscv_subset_supports (rps, "xcvbitmanip");
+ case INSN_CLASS_XCVELW:
+ return riscv_subset_supports (rps, "xcvelw");
+ case INSN_CLASS_XCVMAC:
+ return riscv_subset_supports (rps, "xcvmac");
case INSN_CLASS_XCVMEM:
return riscv_subset_supports (rps, "xcvmem");
+ case INSN_CLASS_XCVSIMD:
+ return riscv_subset_supports (rps, "xcvsimd");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@@ -2770,6 +2817,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("c' or `zca");
case INSN_CLASS_ZIHINTPAUSE:
return "zihintpause";
+ case INSN_CLASS_ZIMOP:
+ return "zimop";
case INSN_CLASS_M:
return "m";
case INSN_CLASS_ZMMUL:
@@ -2949,22 +2998,28 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zcb' and `zbb");
case INSN_CLASS_ZCB_AND_ZMMUL:
return _("zcb' and `zmmul', or `zcb' and `m");
+ case INSN_CLASS_ZCMOP:
+ return "zcmop";
case INSN_CLASS_ZCMP:
return "zcmp";
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
return _("h");
- case INSN_CLASS_XCVMAC:
- return "xcvmac";
case INSN_CLASS_XCVALU:
return "xcvalu";
- case INSN_CLASS_XCVELW:
- return "xcvelw";
case INSN_CLASS_XCVBI:
return "xcvbi";
+ case INSN_CLASS_XCVBITMANIP:
+ return "xcvbitmanip";
+ case INSN_CLASS_XCVELW:
+ return "xcvelw";
+ case INSN_CLASS_XCVMAC:
+ return "xcvmac";
case INSN_CLASS_XCVMEM:
return "xcvmem";
+ case INSN_CLASS_XCVSIMD:
+ return "xcvsimd";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
generated by cgit v1.1 at 2024-10-02 07:27:38 +0000