diff options
| -rw-r--r-- | gas/ChangeLog | 16 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 193 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/set-arch.d | 365 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/set-arch.s | 487 |
6 files changed, 1000 insertions, 69 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 96538fb..6cfe9b3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,19 @@ +2003-06-29 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * config/tc-mips.c (mips_set_options,mips_opts): Support for + .set arch=FOO. + (file_mips_arch): Rename mips_arch. + (mips_arch_info,mips_tune_info): Remove. + (hilo_interlocks,gpr_interlocks,cop_interlocks): Use mips_opts.arch. + (mips_cpu_info_from_arch): New function. + (md_begin): Use file_mips_arch. + (macro_build,macro,mips_ip): Use mips_opts.arch. + (mips_set_architecture): Init file_mips_arch and mips_opts.arch. + (mips_after_parse_args): Remove mips_arch_info and mips_tune_info. + Use file_mips_arch. + (s_mipsset): Support for .set arch=FOO. + (mips_cpu_info_table): Fix typo. + 2003-06-26 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Declare "exp" before "if". diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 101afe7..6bba581 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -180,6 +180,9 @@ struct mips_set_options is passed but can changed if the assembler code uses .set mipsN. */ int gp32; int fp32; + /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march + command line option, and the default CPU. */ + int arch; }; /* True if -mgp32 was passed. */ @@ -194,7 +197,7 @@ static int file_mips_fp32 = -1; static struct mips_set_options mips_opts = { - ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 + ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN }; /* These variables are filled in with the masks of registers used. @@ -219,15 +222,13 @@ static int file_ase_mips3d; static int file_ase_mdmx; /* The argument of the -march= flag. The architecture we are assembling. */ -static int mips_arch = CPU_UNKNOWN; +static int file_mips_arch = CPU_UNKNOWN; static const char *mips_arch_string; -static const struct mips_cpu_info *mips_arch_info; /* The argument of the -mtune= flag. The architecture for which we are optimizing. */ static int mips_tune = CPU_UNKNOWN; static const char *mips_tune_string; -static const struct mips_cpu_info *mips_tune_info; /* True when generating 32-bit code for a 64-bit processor. */ static int mips_32bitmode = 0; @@ -338,26 +339,26 @@ static int mips_32bitmode = 0; reads from the HI and LO registers, and thus does not require nops to be inserted. */ -#define hilo_interlocks (mips_arch == CPU_R4010 \ - || mips_arch == CPU_VR5500 \ - || mips_arch == CPU_SB1 \ +#define hilo_interlocks (mips_opts.arch == CPU_R4010 \ + || mips_opts.arch == CPU_VR5500 \ + || mips_opts.arch == CPU_SB1 \ ) /* Whether the processor uses hardware interlocks to protect reads from the GPRs, and thus does not require nops to be inserted. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ - || mips_arch == CPU_VR5400 \ - || mips_arch == CPU_VR5500 \ - || mips_arch == CPU_R3900) + || mips_opts.arch == CPU_VR5400 \ + || mips_opts.arch == CPU_VR5500 \ + || mips_opts.arch == CPU_R3900) /* As with other "interlocks" this is used by hardware that has FP (co-processor) interlocks. */ /* Itbl support may require additional care here. */ -#define cop_interlocks (mips_arch == CPU_R4300 \ - || mips_arch == CPU_VR5400 \ - || mips_arch == CPU_VR5500 \ - || mips_arch == CPU_SB1 \ +#define cop_interlocks (mips_opts.arch == CPU_R4300 \ + || mips_opts.arch == CPU_VR5400 \ + || mips_opts.arch == CPU_VR5500 \ + || mips_opts.arch == CPU_SB1 \ ) /* Is this a mfhi or mflo instruction? */ @@ -998,6 +999,8 @@ static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *, const char *)); static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); +static const struct mips_cpu_info *mips_cpu_info_from_arch + PARAMS ((int)); /* Pseudo-op table. @@ -1202,7 +1205,7 @@ md_begin () int i = 0; int broken = 0; - if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) + if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) as_warn (_("Could not set architecture and machine")); op_hash = hash_new (); @@ -2984,8 +2987,8 @@ macro_build (place, counter, ep, name, fmt, va_alist) && OPCODE_IS_MEMBER (insn.insn_mo, (mips_opts.isa | (file_ase_mips16 ? INSN_MIPS16 : 0)), - mips_arch) - && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) + mips_opts.arch) + && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) break; ++insn.insn_mo; @@ -5899,7 +5902,7 @@ macro (ip) lr = 1; goto ld; case M_LDC1_AB: - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -5988,7 +5991,7 @@ macro (ip) s = "scd"; goto st; case M_SDC1_AB: - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -6675,7 +6678,7 @@ macro (ip) } case M_L_DOB: - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -6716,7 +6719,7 @@ macro (ip) * But, the resulting address is the same after relocation so why * generate the extra instruction? */ - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -6734,7 +6737,7 @@ macro (ip) goto ldd_std; case M_S_DAB: - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -7318,7 +7321,7 @@ macro2 (ip) break; case M_DROL: - if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) + if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) { if (dreg == sreg) { @@ -7349,7 +7352,7 @@ macro2 (ip) break; case M_ROL: - if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) + if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) { if (dreg == sreg) { @@ -7387,7 +7390,7 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("Improper rotate count")); rot = imm_expr.X_add_number & 0x3f; - if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) + if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) { rot = (64 - rot) & 0x3f; if (rot >= 32) @@ -7423,7 +7426,7 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("Improper rotate count")); rot = imm_expr.X_add_number & 0x1f; - if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) + if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) { macro_build ((char *) NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); @@ -7445,7 +7448,7 @@ macro2 (ip) break; case M_DROR: - if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) + if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) { macro_build ((char *) NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg); @@ -7462,7 +7465,7 @@ macro2 (ip) break; case M_ROR: - if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) + if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) { macro_build ((char *) NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg); @@ -7486,7 +7489,7 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("Improper rotate count")); rot = imm_expr.X_add_number & 0x3f; - if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) + if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) { if (rot >= 32) macro_build ((char *) NULL, &icnt, NULL, "dror32", @@ -7521,7 +7524,7 @@ macro2 (ip) if (imm_expr.X_op != O_constant) as_bad (_("Improper rotate count")); rot = imm_expr.X_add_number & 0x1f; - if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) + if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) { macro_build ((char *) NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot); @@ -7543,7 +7546,7 @@ macro2 (ip) break; case M_S_DOB: - if (mips_arch == CPU_R4650) + if (mips_opts.arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -8555,14 +8558,14 @@ mips_ip (str, ip) | (file_ase_mips16 ? INSN_MIPS16 : 0) | (mips_opts.ase_mdmx ? INSN_MDMX : 0) | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), - mips_arch)) + mips_opts.arch)) ok = TRUE; else ok = FALSE; if (insn->pinfo != INSN_MACRO) { - if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) + if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) ok = FALSE; } @@ -8579,15 +8582,10 @@ mips_ip (str, ip) if (!insn_error) { static char buf[100]; - if (mips_arch_info->is_isa) - sprintf (buf, - _("opcode not supported at this ISA level (%s)"), - mips_cpu_info_from_isa (mips_opts.isa)->name); - else - sprintf (buf, - _("opcode not supported on this processor: %s (%s)"), - mips_arch_info->name, - mips_cpu_info_from_isa (mips_opts.isa)->name); + sprintf (buf, + _("opcode not supported on this processor: %s (%s)"), + mips_cpu_info_from_arch (mips_opts.arch)->name, + mips_cpu_info_from_isa (mips_opts.isa)->name); insn_error = buf; } if (save_c) @@ -11089,8 +11087,8 @@ mips_set_architecture (info) { if (info != 0) { - mips_arch_info = info; - mips_arch = info->cpu; + file_mips_arch = info->cpu; + mips_opts.arch = info->cpu; mips_opts.isa = info->isa; } } @@ -11103,16 +11101,16 @@ mips_set_tune (info) const struct mips_cpu_info *info; { if (info != 0) - { - mips_tune_info = info; - mips_tune = info->cpu; - } + mips_tune = info->cpu; } void mips_after_parse_args () { + const struct mips_cpu_info *arch_info = 0; + const struct mips_cpu_info *tune_info = 0; + /* GP relative stuff not working for PE */ if (strncmp (TARGET_OS, "pe", 2) == 0 && g_switch_value != 0) @@ -11131,41 +11129,44 @@ mips_after_parse_args () as much as possible. */ if (mips_arch_string != 0) - mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); - - if (mips_tune_string != 0) - mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); + arch_info = mips_parse_cpu ("-march", mips_arch_string); if (file_mips_isa != ISA_UNKNOWN) { /* Handle -mipsN. At this point, file_mips_isa contains the - ISA level specified by -mipsN, while mips_opts.isa contains + ISA level specified by -mipsN, while arch_info->isa contains the -march selection (if any). */ - if (mips_arch_info != 0) + if (arch_info != 0) { /* -march takes precedence over -mipsN, since it is more descriptive. There's no harm in specifying both as long as the ISA levels are the same. */ - if (file_mips_isa != mips_opts.isa) + if (file_mips_isa != arch_info->isa) as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), mips_cpu_info_from_isa (file_mips_isa)->name, - mips_cpu_info_from_isa (mips_opts.isa)->name); + mips_cpu_info_from_isa (arch_info->isa)->name); } else - mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); + arch_info = mips_cpu_info_from_isa (file_mips_isa); } - if (mips_arch_info == 0) - mips_set_architecture (mips_parse_cpu ("default CPU", - MIPS_CPU_STRING_DEFAULT)); + if (arch_info == 0) + arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); - if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) + if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) as_bad ("-march=%s is not compatible with the selected ABI", - mips_arch_info->name); + arch_info->name); + + mips_set_architecture (arch_info); + + /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ + if (mips_tune_string != 0) + tune_info = mips_parse_cpu ("-mtune", mips_tune_string); - /* Optimize for mips_arch, unless -mtune selects a different processor. */ - if (mips_tune_info == 0) - mips_set_tune (mips_arch_info); + if (tune_info == 0) + mips_set_tune (arch_info); + else + mips_set_tune (tune_info); if (file_mips_gp32 >= 0) { @@ -11210,11 +11211,11 @@ mips_after_parse_args () /* If the selected architecture includes support for ASEs, enable generation of code for them. */ if (mips_opts.mips16 == -1) - mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; + mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; if (mips_opts.ase_mips3d == -1) - mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; + mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; if (mips_opts.ase_mdmx == -1) - mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; + mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; file_mips_isa = mips_opts.isa; file_ase_mips16 = mips_opts.mips16; @@ -12464,6 +12465,47 @@ s_mipsset (x) free (s); } } + else if (strncmp (name, "arch=", 5) == 0) + { + /* Permit the user to change the architecture on the fly. Needless + to say, misuse can cause serious problems. */ + if (strcmp (name + 5, "default") == 0) + { + mips_opts.arch = file_mips_arch; + mips_opts.isa = file_mips_isa; + mips_opts.gp32 = file_mips_gp32; + mips_opts.fp32 = file_mips_fp32; + } + else + { + const struct mips_cpu_info *p; + + p = mips_parse_cpu("internal use", name + 5); + if (!p) + as_bad (_("unknown architecture %s"), name + 5); + else + { + mips_opts.arch = p->cpu; + mips_opts.isa = p->isa; + } + + switch (mips_opts.arch) + { + case CPU_R3000: + case CPU_R3900: + case CPU_R6000: + case CPU_MIPS32: + case CPU_MIPS32R2: + mips_opts.gp32 = 1; + mips_opts.fp32 = 1; + break; + default: + mips_opts.gp32 = 0; + mips_opts.fp32 = 0; + break; + } + } + } else { as_warn (_("Tried to set unrecognized symbol: %s\n"), name); @@ -14738,7 +14780,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "r7000", 0, ISA_MIPS4, CPU_R5000 }, /* MIPS 32 */ - { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, + { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, @@ -14872,6 +14914,19 @@ mips_cpu_info_from_isa (isa) return NULL; } + +static const struct mips_cpu_info * +mips_cpu_info_from_arch (arch) + int arch; +{ + int i; + + for (i = 0; mips_cpu_info_table[i].name != NULL; i++) + if (arch == mips_cpu_info_table[i].cpu) + return (&mips_cpu_info_table[i]); + + return NULL; +} static void show (stream, string, col_p, first_p) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 57a7903..726b5fb 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2003-06-29 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * gas/mips/set-arch.s: New file, testcase for .set arch=FOO. + * gas/mips/set-arch.d: Likewise. + * gas/mips/mips.exp: Use it. + 2003-06-25 Richard Sandiford <rsandifo@redhat.com> * gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 2330443..541c86f 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -562,6 +562,8 @@ if { [istarget mips*-*-*] } then { run_dump_test_arches "mips64" [mips_arch_list_matching mips64] + run_dump_test "set-arch" + if { !$addr32 } { run_dump_test "mips64-mips3d" run_dump_test_arches "mips64-mips3d-incl" [mips_arch_list_matching mips3d] diff --git a/gas/testsuite/gas/mips/set-arch.d b/gas/testsuite/gas/mips/set-arch.d new file mode 100644 index 0000000..eca1ac3 --- /dev/null +++ b/gas/testsuite/gas/mips/set-arch.d @@ -0,0 +1,365 @@ +#objdump: -dr --prefix-addresses -mmips:sb1 +#name: \.set arch=FOO + +dump\.o: file format .*mips + +Disassembly of section \.text: +00000000 <[^>]*> cache 0x1,0\(zero\) +00000004 <[^>]*> cache 0x2,0\(zero\) +00000008 <[^>]*> cache 0x3,0\(zero\) +0000000c <[^>]*> dmult a0,a1 +00000010 <[^>]*> dmultu a1,a2 +00000014 <[^>]*> movn a2,a3,zero +00000018 <[^>]*> movz a3,t0,zero +0000001c <[^>]*> ddiv zero,t0,t1 +00000020 <[^>]*> ddivu zero,t1,t2 +00000024 <[^>]*> 0x16c5005 +00000028 <[^>]*> movt t3,t4,\$fcc3 +0000002c <[^>]*> wait +00000030 <[^>]*> cache 0x4,16\(t6\) +00000034 <[^>]*> 0x71ee0010 +00000038 <[^>]*> c0 0x23 +0000003c <[^>]*> c0 0x21 +00000040 <[^>]*> c0 0x22 +00000044 <[^>]*> madd a0,a1 +00000048 <[^>]*> maddu a1,a2 +0000004c <[^>]*> mul a2,a3,t0 +00000050 <[^>]*> bc1f 00000050 <[^>]*> +00000054 <[^>]*> bc1f \$fcc1,00000050 <[^>]*> +00000058 <[^>]*> bc1fl \$fcc1,00000050 <[^>]*> +0000005c <[^>]*> bc1t \$fcc1,00000050 <[^>]*> +00000060 <[^>]*> bc1tl \$fcc2,00000050 <[^>]*> +00000064 <[^>]*> c\.f\.d \$f4,\$f6 +00000068 <[^>]*> c\.f\.d \$fcc1,\$f4,\$f6 +0000006c <[^>]*> ldxc1 \$f2,a0\(a1\) +00000070 <[^>]*> lwxc1 \$f2,a0\(a1\) +00000074 <[^>]*> madd\.d \$f0,\$f2,\$f4,\$f6 +00000078 <[^>]*> madd\.s \$f0,\$f2,\$f4,\$f6 +0000007c <[^>]*> movf a0,a1,\$fcc4 +00000080 <[^>]*> movf\.d \$f4,\$f6,\$fcc0 +00000084 <[^>]*> movf\.s \$f4,\$f6,\$fcc0 +00000088 <[^>]*> movn a0,a2,a2 +0000008c <[^>]*> movn\.d \$f4,\$f6,a2 +00000090 <[^>]*> movn\.s \$f4,\$f6,a2 +00000094 <[^>]*> movt a0,a1,\$fcc4 +00000098 <[^>]*> movt\.d \$f4,\$f6,\$fcc0 +0000009c <[^>]*> movt\.s \$f4,\$f6,\$fcc0 +000000a0 <[^>]*> movz a0,a2,a2 +000000a4 <[^>]*> movz\.d \$f4,\$f6,a2 +000000a8 <[^>]*> movz\.s \$f4,\$f6,a2 +000000ac <[^>]*> msub\.d \$f0,\$f2,\$f4,\$f6 +000000b0 <[^>]*> msub\.s \$f0,\$f2,\$f4,\$f6 +000000b4 <[^>]*> nmadd\.d \$f0,\$f2,\$f4,\$f6 +000000b8 <[^>]*> nmadd\.s \$f0,\$f2,\$f4,\$f6 +000000bc <[^>]*> nmsub\.d \$f0,\$f2,\$f4,\$f6 +000000c0 <[^>]*> nmsub\.s \$f0,\$f2,\$f4,\$f6 +000000c4 <[^>]*> prefx 0x4,a0\(a1\) +000000c8 <[^>]*> recip\.d \$f4,\$f6 +000000cc <[^>]*> recip\.s \$f4,\$f6 +000000d0 <[^>]*> rsqrt\.d \$f4,\$f6 +000000d4 <[^>]*> rsqrt\.s \$f4,\$f6 +000000d8 <[^>]*> sdxc1 \$f4,a0\(a1\) +000000dc <[^>]*> swxc1 \$f4,a0\(a1\) +000000e0 <[^>]*> abs\.ps \$f0,\$f2 +000000e4 <[^>]*> add\.ps \$f2,\$f4,\$f6 +000000e8 <[^>]*> alnv\.ps \$f6,\$f8,\$f10,v1 +000000ec <[^>]*> c\.eq\.ps \$f8,\$f10 +000000f0 <[^>]*> c\.eq\.ps \$fcc2,\$f10,\$f12 +000000f4 <[^>]*> c\.f\.ps \$f8,\$f10 +000000f8 <[^>]*> c\.f\.ps \$fcc2,\$f10,\$f12 +000000fc <[^>]*> c\.le\.ps \$f8,\$f10 +00000100 <[^>]*> c\.le\.ps \$fcc2,\$f10,\$f12 +00000104 <[^>]*> c\.lt\.ps \$f8,\$f10 +00000108 <[^>]*> c\.lt\.ps \$fcc2,\$f10,\$f12 +0000010c <[^>]*> c\.nge\.ps \$f8,\$f10 +00000110 <[^>]*> c\.nge\.ps \$fcc2,\$f10,\$f12 +00000114 <[^>]*> c\.ngl\.ps \$f8,\$f10 +00000118 <[^>]*> c\.ngl\.ps \$fcc2,\$f10,\$f12 +0000011c <[^>]*> c\.ngle\.ps \$f8,\$f10 +00000120 <[^>]*> c\.ngle\.ps \$fcc2,\$f10,\$f12 +00000124 <[^>]*> c\.ngt\.ps \$f8,\$f10 +00000128 <[^>]*> c\.ngt\.ps \$fcc2,\$f10,\$f12 +0000012c <[^>]*> c\.ole\.ps \$f8,\$f10 +00000130 <[^>]*> c\.ole\.ps \$fcc2,\$f10,\$f12 +00000134 <[^>]*> c\.olt\.ps \$f8,\$f10 +00000138 <[^>]*> c\.olt\.ps \$fcc2,\$f10,\$f12 +0000013c <[^>]*> c\.seq\.ps \$f8,\$f10 +00000140 <[^>]*> c\.seq\.ps \$fcc2,\$f10,\$f12 +00000144 <[^>]*> c\.sf\.ps \$f8,\$f10 +00000148 <[^>]*> c\.sf\.ps \$fcc2,\$f10,\$f12 +0000014c <[^>]*> c\.ueq\.ps \$f8,\$f10 +00000150 <[^>]*> c\.ueq\.ps \$fcc2,\$f10,\$f12 +00000154 <[^>]*> c\.ule\.ps \$f8,\$f10 +00000158 <[^>]*> c\.ule\.ps \$fcc2,\$f10,\$f12 +0000015c <[^>]*> c\.ult\.ps \$f8,\$f10 +00000160 <[^>]*> c\.ult\.ps \$fcc2,\$f10,\$f12 +00000164 <[^>]*> c\.un\.ps \$f8,\$f10 +00000168 <[^>]*> c\.un\.ps \$fcc2,\$f10,\$f12 +0000016c <[^>]*> cvt\.ps\.s \$f12,\$f14,\$f16 +00000170 <[^>]*> cvt\.s\.pl \$f16,\$f18 +00000174 <[^>]*> cvt\.s\.pu \$f18,\$f20 +00000178 <[^>]*> luxc1 \$f20,a0\(a1\) +0000017c <[^>]*> madd\.ps \$f20,\$f22,\$f24,\$f26 +00000180 <[^>]*> mov\.ps \$f24,\$f26 +00000184 <[^>]*> movf\.ps \$f26,\$f28,\$fcc2 +00000188 <[^>]*> movn\.ps \$f26,\$f28,v1 +0000018c <[^>]*> movt\.ps \$f28,\$f30,\$fcc4 +00000190 <[^>]*> movz\.ps \$f28,\$f30,a1 +00000194 <[^>]*> msub\.ps \$f30,\$f0,\$f2,\$f4 +00000198 <[^>]*> mul\.ps \$f2,\$f4,\$f6 +0000019c <[^>]*> neg\.ps \$f6,\$f8 +000001a0 <[^>]*> nmadd\.ps \$f6,\$f8,\$f10,\$f12 +000001a4 <[^>]*> nmsub\.ps \$f6,\$f8,\$f10,\$f12 +000001a8 <[^>]*> pll\.ps \$f10,\$f12,\$f14 +000001ac <[^>]*> plu\.ps \$f14,\$f16,\$f18 +000001b0 <[^>]*> pul\.ps \$f16,\$f18,\$f20 +000001b4 <[^>]*> puu\.ps \$f20,\$f22,\$f24 +000001b8 <[^>]*> sub\.ps \$f22,\$f24,\$f26 +000001bc <[^>]*> suxc1 \$f26,a2\(a3\) +000001c0 <[^>]*> c\.eq\.ps \$fcc3,\$f10,\$f12 +000001c4 <[^>]*> movf\.ps \$f26,\$f28,\$fcc3 +000001c8 <[^>]*> clo at,v0 +000001cc <[^>]*> clz v1,a0 +000001d0 <[^>]*> madd a1,a2 +000001d4 <[^>]*> maddu a3,a4 +000001d8 <[^>]*> msub a5,a6 +000001dc <[^>]*> msubu a7,t0 +000001e0 <[^>]*> mul t1,t2,t3 +000001e4 <[^>]*> pref 0x4,0\(s0\) +000001e8 <[^>]*> pref 0x4,32767\(s1\) +000001ec <[^>]*> pref 0x4,-32768\(s2\) +000001f0 <[^>]*> ssnop +000001f4 <[^>]*> bc2f 00000050 <[^>]*> +000001f8 <[^>]*> nop +000001fc <[^>]*> bc2fl 00000050 <[^>]*> +00000200 <[^>]*> nop +00000204 <[^>]*> bc2t 00000050 <[^>]*> +00000208 <[^>]*> nop +0000020c <[^>]*> bc2tl 00000050 <[^>]*> +00000210 <[^>]*> nop +00000214 <[^>]*> cfc2 at,\$2 +00000218 <[^>]*> c2 0x1234567 +0000021c <[^>]*> ctc2 v0,\$3 +00000220 <[^>]*> mfc2 v1,\$4 +00000224 <[^>]*> mfc2 a0,\$5 +00000228 <[^>]*> mfc2 a1,\$6,7 +0000022c <[^>]*> mtc2 a2,\$7 +00000230 <[^>]*> mtc2 a3,\$8 +00000234 <[^>]*> mtc2 a4,\$9,7 +00000238 <[^>]*> cache 0x5,0\(at\) +0000023c <[^>]*> cache 0x5,32767\(v0\) +00000240 <[^>]*> cache 0x5,-32768\(v1\) +00000244 <[^>]*> eret +00000248 <[^>]*> tlbp +0000024c <[^>]*> tlbr +00000250 <[^>]*> tlbwi +00000254 <[^>]*> tlbwr +00000258 <[^>]*> wait +0000025c <[^>]*> wait +00000260 <[^>]*> wait 0x56789 +00000264 <[^>]*> break +00000268 <[^>]*> break +0000026c <[^>]*> break 0x12345 +00000270 <[^>]*> sdbbp +00000274 <[^>]*> sdbbp +00000278 <[^>]*> sdbbp 0x56789 +0000027c <[^>]*> sll zero,zero,0x3 +00000280 <[^>]*> 0x7ca43980 +00000284 <[^>]*> 0x7ca46984 +00000288 <[^>]*> 0x100fc09 +0000028c <[^>]*> 0x120a409 +00000290 <[^>]*> 0x1000408 +00000294 <[^>]*> 0x7c0a003b +00000298 <[^>]*> 0x7c0b083b +0000029c <[^>]*> 0x7c0c103b +000002a0 <[^>]*> 0x7c0d183b +000002a4 <[^>]*> 0x7c0e203b +000002a8 <[^>]*> 0x7c0f283b +000002ac <[^>]*> 0x2acf02 +000002b0 <[^>]*> 0x2ac902 +000002b4 <[^>]*> negu t9,a0 +000002b8 <[^>]*> 0x32ac846 +000002bc <[^>]*> 0x8ac846 +000002c0 <[^>]*> 0x8ac846 +000002c4 <[^>]*> 0x7c073c20 +000002c8 <[^>]*> 0x7c0a4420 +000002cc <[^>]*> 0x7c073e20 +000002d0 <[^>]*> 0x7c0a4620 +000002d4 <[^>]*> 0x55f5555 +000002d8 <[^>]*> 0x7c0738a0 +000002dc <[^>]*> 0x7c0a40a0 +000002e0 <[^>]*> 0x41606000 +000002e4 <[^>]*> 0x41606000 +000002e8 <[^>]*> 0x416a6000 +000002ec <[^>]*> 0x41606020 +000002f0 <[^>]*> 0x41606020 +000002f4 <[^>]*> 0x416a6020 +000002f8 <[^>]*> 0x41595000 +000002fc <[^>]*> 0x41d95000 +00000300 <[^>]*> 0x44710000 +00000304 <[^>]*> 0x44f10000 +00000308 <[^>]*> 0x48715555 +0000030c <[^>]*> 0x48f15555 +00000310 <[^>]*> dclo at,v0 +00000314 <[^>]*> dclz v1,a0 +00000318 <[^>]*> dmfc2 v1,\$4 +0000031c <[^>]*> dmfc2 a0,\$5 +00000320 <[^>]*> dmfc2 a1,\$6,7 +00000324 <[^>]*> dmtc2 a2,\$7 +00000328 <[^>]*> dmtc2 a3,\$8 +0000032c <[^>]*> dmtc2 a4,\$9,7 +00000330 <[^>]*> 0x850029 +00000334 <[^>]*> 0xa60028 +00000338 <[^>]*> mflo a0 +0000033c <[^>]*> 0xa62029 +00000340 <[^>]*> 0xa62229 +00000344 <[^>]*> 0xa62629 +00000348 <[^>]*> 0xa62269 +0000034c <[^>]*> 0xa62669 +00000350 <[^>]*> 0xa62429 +00000354 <[^>]*> 0xa62069 +00000358 <[^>]*> 0xa62469 +0000035c <[^>]*> mflo a0 +00000360 <[^>]*> 0xa62028 +00000364 <[^>]*> 0xa62228 +00000368 <[^>]*> 0xa62628 +0000036c <[^>]*> 0xa62268 +00000370 <[^>]*> 0xa62668 +00000374 <[^>]*> 0xa62428 +00000378 <[^>]*> 0xa62068 +0000037c <[^>]*> 0xa62468 +00000380 <[^>]*> 0xa62059 +00000384 <[^>]*> 0xa62258 +00000388 <[^>]*> 0xa62259 +0000038c <[^>]*> 0xa620d8 +00000390 <[^>]*> 0xa620d9 +00000394 <[^>]*> 0xa622d8 +00000398 <[^>]*> 0xa622d9 +0000039c <[^>]*> 0xa62158 +000003a0 <[^>]*> 0xa62159 +000003a4 <[^>]*> 0xa62358 +000003a8 <[^>]*> 0xa62359 +000003ac <[^>]*> 0xa621d8 +000003b0 <[^>]*> 0xa621d9 +000003b4 <[^>]*> 0xa623d8 +000003b8 <[^>]*> 0xa623d9 +000003bc <[^>]*> 0x252642 +000003c0 <[^>]*> 0xc52046 +000003c4 <[^>]*> 0x25267a +000003c8 <[^>]*> 0x25267e +000003cc <[^>]*> 0x25267e +000003d0 <[^>]*> 0xc52056 +000003d4 <[^>]*> sdbbp +000003d8 <[^>]*> 0x7000003e +000003dc <[^>]*> 0x7003183d +000003e0 <[^>]*> 0x7083183d +000003e4 <[^>]*> mfc0 a0,c0_perfcnt,3 +000003e8 <[^>]*> mfc0 a0,c0_perfcnt,2 +000003ec <[^>]*> mtc0 a0,c0_perfcnt,3 +000003f0 <[^>]*> mtc0 a0,c0_perfcnt,2 +000003f4 <[^>]*> c2 0xc4100b +000003f8 <[^>]*> 0x4886208b +000003fc <[^>]*> c2 0x1cf218b +00000400 <[^>]*> c2 0x1df310b +00000404 <[^>]*> c2 0xc4100c +00000408 <[^>]*> 0x4886208c +0000040c <[^>]*> c2 0x1cf218c +00000410 <[^>]*> c2 0x1df310c +00000414 <[^>]*> c2 0xc20001 +00000418 <[^>]*> mtc2 a2,\$4,1 +0000041c <[^>]*> c2 0x1cf3001 +00000420 <[^>]*> c2 0x1df2001 +00000424 <[^>]*> c2 0xc20005 +00000428 <[^>]*> mtc2 a2,\$4,5 +0000042c <[^>]*> c2 0x1cf3005 +00000430 <[^>]*> c2 0x1df2005 +00000434 <[^>]*> c2 0xc20004 +00000438 <[^>]*> mtc2 a2,\$4,4 +0000043c <[^>]*> c2 0x1cf3004 +00000440 <[^>]*> c2 0x1df2004 +00000444 <[^>]*> c2 0xc41007 +00000448 <[^>]*> 0x48862087 +0000044c <[^>]*> c2 0x1cf2187 +00000450 <[^>]*> c2 0x1df3107 +00000454 <[^>]*> c2 0xc41006 +00000458 <[^>]*> 0x48862086 +0000045c <[^>]*> c2 0x1cf2186 +00000460 <[^>]*> c2 0x1df3106 +00000464 <[^>]*> c2 0xc41030 +00000468 <[^>]*> 0x488620b0 +0000046c <[^>]*> c2 0x1cf21b0 +00000470 <[^>]*> c2 0x1df3130 +00000474 <[^>]*> c2 0xc20033 +00000478 <[^>]*> 0x48862033 +0000047c <[^>]*> c2 0x1cf3033 +00000480 <[^>]*> c2 0x1df2033 +00000484 <[^>]*> c2 0xc20433 +00000488 <[^>]*> 0x48862433 +0000048c <[^>]*> c2 0x1cf3433 +00000490 <[^>]*> c2 0x1df2433 +00000494 <[^>]*> c2 0xc20032 +00000498 <[^>]*> 0x48862032 +0000049c <[^>]*> c2 0x1cf3032 +000004a0 <[^>]*> c2 0x1df2032 +000004a4 <[^>]*> c2 0xc20432 +000004a8 <[^>]*> 0x48862432 +000004ac <[^>]*> c2 0x1cf3432 +000004b0 <[^>]*> c2 0x1df2432 +000004b4 <[^>]*> c2 0xc4100f +000004b8 <[^>]*> 0x4886208f +000004bc <[^>]*> c2 0x1cf218f +000004c0 <[^>]*> c2 0x1df310f +000004c4 <[^>]*> c2 0xc4100e +000004c8 <[^>]*> 0x4886208e +000004cc <[^>]*> c2 0x1cf218e +000004d0 <[^>]*> c2 0x1df310e +000004d4 <[^>]*> c2 0xc41002 +000004d8 <[^>]*> 0x48862082 +000004dc <[^>]*> c2 0x1cf2182 +000004e0 <[^>]*> c2 0x1df3102 +000004e4 <[^>]*> c2 0xc41003 +000004e8 <[^>]*> 0x48862083 +000004ec <[^>]*> c2 0x1cf2183 +000004f0 <[^>]*> c2 0x1df3103 +000004f4 <[^>]*> c2 0xc4100a +000004f8 <[^>]*> 0x4886208a +000004fc <[^>]*> c2 0x1cf218a +00000500 <[^>]*> c2 0x1df310a +00000504 <[^>]*> c2 0xc4100d +00000508 <[^>]*> 0x4886208d +0000050c <[^>]*> c2 0x1cf218d +00000510 <[^>]*> c2 0x1df310d +00000514 <[^>]*> 0x48a41018 +00000518 <[^>]*> 0x4984101f +0000051c <[^>]*> 0x49c4101f +00000520 <[^>]*> 0x4904101f +00000524 <[^>]*> 0x4944101f +00000528 <[^>]*> 0x48c62090 +0000052c <[^>]*> c2 0x1ce3110 +00000530 <[^>]*> 0x48c62092 +00000534 <[^>]*> c2 0x1ce3112 +00000538 <[^>]*> c2 0x1cd00a0 +0000053c <[^>]*> c2 0xbf +00000540 <[^>]*> 0x480000bf +00000544 <[^>]*> bc2f 00000844 <[^>]*> +00000548 <[^>]*> c2 0x103e +0000054c <[^>]*> 0x4804103e +00000550 <[^>]*> 0xc52046 +00000554 <[^>]*> 0x252442 +00000558 <[^>]*> 0xc52056 +0000055c <[^>]*> 0x25207e +00000560 <[^>]*> 0x2520ba +00000564 <[^>]*> prefx 0x4,a0\(a1\) +00000568 <[^>]*> wait +0000056c <[^>]*> wait +00000570 <[^>]*> wait 0x56789 +00000574 <[^>]*> ssnop +00000578 <[^>]*> clo v1,a0 +0000057c <[^>]*> dclo v1,a0 +00000580 <[^>]*> clz v1,a0 +00000584 <[^>]*> dclz v1,a0 +00000588 <[^>]*> luxc1 \$f0,a0\(v0\) +0000058c <[^>]*> suxc1 \$f2,a0\(v0\) +00000590 <[^>]*> tlbp +00000594 <[^>]*> tlbr + \.\.\. diff --git a/gas/testsuite/gas/mips/set-arch.s b/gas/testsuite/gas/mips/set-arch.s new file mode 100644 index 0000000..01a6c83 --- /dev/null +++ b/gas/testsuite/gas/mips/set-arch.s @@ -0,0 +1,487 @@ + .text + + .set noreorder + .set noat + + .set arch=4010 + + flushi + flushd + flushid + madd $4,$5 + maddu $5,$6 + ffc $6,$7 + ffs $7,$8 + msub $8,$9 + msubu $9,$10 + selsl $10,$11,$12 + selsr $11,$12,$13 + waiti + wb 16($14) + addciu $14,$15,16 + + .set arch=4100 + + hibernate + standby + suspend + + .set arch=4650 + + mad $4,$5 + madu $5,$6 + mul $6,$7,$8 + + # test mips4 instructions. + + .set arch=mips4 + +text_label: + bc1f text_label + bc1f $fcc1,text_label + bc1fl $fcc1,text_label + bc1t $fcc1,text_label + bc1tl $fcc2,text_label + c.f.d $f4,$f6 + c.f.d $fcc1,$f4,$f6 + ldxc1 $f2,$4($5) + lwxc1 $f2,$4($5) + madd.d $f0,$f2,$f4,$f6 + madd.s $f0,$f2,$f4,$f6 + movf $4,$5,$fcc4 + movf.d $f4,$f6,$fcc0 + movf.s $f4,$f6,$fcc0 + movn $4,$6,$6 + movn.d $f4,$f6,$6 + movn.s $f4,$f6,$6 + movt $4,$5,$fcc4 + movt.d $f4,$f6,$fcc0 + movt.s $f4,$f6,$fcc0 + movz $4,$6,$6 + movz.d $f4,$f6,$6 + movz.s $f4,$f6,$6 + msub.d $f0,$f2,$f4,$f6 + msub.s $f0,$f2,$f4,$f6 + nmadd.d $f0,$f2,$f4,$f6 + nmadd.s $f0,$f2,$f4,$f6 + nmsub.d $f0,$f2,$f4,$f6 + nmsub.s $f0,$f2,$f4,$f6 + + # We don't test pref because currently the disassembler will + # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, + # while pref is correct for mips4. Unfortunately, the + # disassembler does not know which architecture it is + # disassembling for. + # pref 4,0($4) + + prefx 4,$4($5) + recip.d $f4,$f6 + recip.s $f4,$f6 + rsqrt.d $f4,$f6 + rsqrt.s $f4,$f6 + sdxc1 $f4,$4($5) + swxc1 $f4,$4($5) + + # test mips5 instructions. + + .set arch=mips5 + + abs.ps $f0, $f2 + add.ps $f2, $f4, $f6 + alnv.ps $f6, $f8, $f10, $3 + c.eq.ps $f8, $f10 + c.eq.ps $fcc2, $f10, $f12 + c.f.ps $f8, $f10 + c.f.ps $fcc2, $f10, $f12 + c.le.ps $f8, $f10 + c.le.ps $fcc2, $f10, $f12 + c.lt.ps $f8, $f10 + c.lt.ps $fcc2, $f10, $f12 + c.nge.ps $f8, $f10 + c.nge.ps $fcc2, $f10, $f12 + c.ngl.ps $f8, $f10 + c.ngl.ps $fcc2, $f10, $f12 + c.ngle.ps $f8, $f10 + c.ngle.ps $fcc2, $f10, $f12 + c.ngt.ps $f8, $f10 + c.ngt.ps $fcc2, $f10, $f12 + c.ole.ps $f8, $f10 + c.ole.ps $fcc2, $f10, $f12 + c.olt.ps $f8, $f10 + c.olt.ps $fcc2, $f10, $f12 + c.seq.ps $f8, $f10 + c.seq.ps $fcc2, $f10, $f12 + c.sf.ps $f8, $f10 + c.sf.ps $fcc2, $f10, $f12 + c.ueq.ps $f8, $f10 + c.ueq.ps $fcc2, $f10, $f12 + c.ule.ps $f8, $f10 + c.ule.ps $fcc2, $f10, $f12 + c.ult.ps $f8, $f10 + c.ult.ps $fcc2, $f10, $f12 + c.un.ps $f8, $f10 + c.un.ps $fcc2, $f10, $f12 + cvt.ps.s $f12, $f14, $f16 + cvt.s.pl $f16, $f18 + cvt.s.pu $f18, $f20 + luxc1 $f20, $4($5) + madd.ps $f20, $f22, $f24, $f26 + mov.ps $f24, $f26 + movf.ps $f26, $f28, $fcc2 + movn.ps $f26, $f28, $3 + movt.ps $f28, $f30, $fcc4 + movz.ps $f28, $f30, $5 + msub.ps $f30, $f0, $f2, $f4 + mul.ps $f2, $f4, $f6 + neg.ps $f6, $f8 + nmadd.ps $f6, $f8, $f10, $f12 + nmsub.ps $f6, $f8, $f10, $f12 + pll.ps $f10, $f12, $f14 + plu.ps $f14, $f16, $f18 + pul.ps $f16, $f18, $f20 + puu.ps $f20, $f22, $f24 + sub.ps $f22, $f24, $f26 + suxc1 $f26, $6($7) + + c.eq.ps $fcc3, $f10, $f12 # warns + movf.ps $f26, $f28, $fcc3 # warns + + # test assembly of mips32 instructions + + .set arch=mips32 + + # unprivileged CPU instructions + + clo $1, $2 + clz $3, $4 + madd $5, $6 + maddu $7, $8 + msub $9, $10 + msubu $11, $12 + mul $13, $14, $15 + pref 4, ($16) + pref 4, 32767($17) + pref 4, -32768($18) + ssnop + + # unprivileged coprocessor instructions. + # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. + + bc2f text_label + nop + bc2fl text_label + nop + bc2t text_label + nop + bc2tl text_label + nop + # XXX other BCzCond encodings not currently expressable + cfc2 $1, $2 + cop2 0x1234567 # disassembles as c2 ... + ctc2 $2, $3 + mfc2 $3, $4 + mfc2 $4, $5, 0 # disassembles without sel + mfc2 $5, $6, 7 + mtc2 $6, $7 + mtc2 $7, $8, 0 # disassembles without sel + mtc2 $8, $9, 7 + + # privileged instructions + + cache 5, ($1) + cache 5, 32767($2) + cache 5, -32768($3) + eret + tlbp + tlbr + tlbwi + tlbwr + wait + wait 0 # disassembles without code + wait 0x56789 + + # Instructions in previous ISAs or CPUs which are now slightly + # different. + break + break 0 # disassembles without code + break 0x12345 + sdbbp + sdbbp 0 # disassembles without code + sdbbp 0x56789 + + # test assembly of mips32r2 instructions + + .set arch=mips32r2 + + # unprivileged CPU instructions + + ehb + + ext $4, $5, 6, 8 + + ins $4, $5, 6, 8 + + jalr.hb $8 + jalr.hb $20, $9 + + jr.hb $8 + + # Note, further testing of rdhwr is done in hwr-names-mips32r2.d + rdhwr $10, $0 + rdhwr $11, $1 + rdhwr $12, $2 + rdhwr $13, $3 + rdhwr $14, $4 + rdhwr $15, $5 + + # This file checks that in fact HW rotate will + # be used for this arch, and checks assembly + # of the official MIPS mnemonics. (Note that disassembly + # uses the traditional "ror" and "rorv" mnemonics.) + # Additional rotate tests are done by rol-hw.d. + rotl $25, $10, 4 + rotr $25, $10, 4 + rotl $25, $10, $4 + rotr $25, $10, $4 + rotrv $25, $10, $4 + + seb $7 + seb $8, $10 + + seh $7 + seh $8, $10 + + synci 0x5555($10) + + wsbh $7 + wsbh $8, $10 + + # cp0 instructions + + di + di $0 + di $10 + + ei + ei $0 + ei $10 + + rdpgpr $10, $25 + + wrpgpr $10, $25 + + # FPU (cp1) instructions + # + # Even registers are supported w/ 32-bit FPU, odd + # registers supported only for 64-bit FPU. + # Only the 32-bit FPU instructions are tested here. + + mfhc1 $17, $f0 + mthc1 $17, $f0 + + # cp2 instructions + + mfhc2 $17, 0x5555 + mthc2 $17, 0x5555 + + .set arch=mips64 + + # test assembly of mips64 instructions + + # unprivileged CPU instructions + + dclo $1, $2 + dclz $3, $4 + + # unprivileged coprocessor instructions. + # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. + + dmfc2 $3, $4 + dmfc2 $4, $5, 0 # disassembles without sel + dmfc2 $5, $6, 7 + dmtc2 $6, $7 + dmtc2 $7, $8, 0 # disassembles without sel + dmtc2 $8, $9, 7 + + .set arch=vr4111 + + dmadd16 $4,$5 + madd16 $5,$6 + + .set arch=vr4120 + + # Include mflos to check for nop insertion. + mflo $4 + dmacc $4,$5,$6 + dmacchi $4,$5,$6 + dmacchis $4,$5,$6 + dmacchiu $4,$5,$6 + dmacchius $4,$5,$6 + dmaccs $4,$5,$6 + dmaccu $4,$5,$6 + dmaccus $4,$5,$6 + mflo $4 + macc $4,$5,$6 + macchi $4,$5,$6 + macchis $4,$5,$6 + macchiu $4,$5,$6 + macchius $4,$5,$6 + maccs $4,$5,$6 + maccu $4,$5,$6 + maccus $4,$5,$6 + + .set arch=vr5400 + + /* Integer instructions. */ + + mulu $4,$5,$6 + mulhi $4,$5,$6 + mulhiu $4,$5,$6 + muls $4,$5,$6 + mulsu $4,$5,$6 + mulshi $4,$5,$6 + mulshiu $4,$5,$6 + macc $4,$5,$6 + maccu $4,$5,$6 + macchi $4,$5,$6 + macchiu $4,$5,$6 + msac $4,$5,$6 + msacu $4,$5,$6 + msachi $4,$5,$6 + msachiu $4,$5,$6 + + ror $4,$5,25 + rorv $4,$5,$6 + dror $4,$5,25 + dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ + dror32 $4,$5,25 + drorv $4,$5,$6 + + /* Debug instructions. */ + + dbreak + dret + mfdr $3,$3 + mtdr $3,$3 + + /* Coprocessor 0 instructions, minus standard ISA 3 ones. + That leaves just the performance monitoring registers. */ + + mfpc $4,1 + mfps $4,1 + mtpc $4,1 + mtps $4,1 + + /* Multimedia instructions. */ + + .macro nsel2 op + /* Test each form of each vector opcode. */ + \op $f0,$f2 + \op $f4,$f6[2] + \op $f6,15 + .if 0 /* Which is right?? */ + /* Test negative numbers in immediate-value slot. */ + \op $f4,-3 + .else + /* Test that it's recognized as an unsigned field. */ + \op $f4,31 + .endif + .endm + + .macro nsel3 op + /* Test each form of each vector opcode. */ + \op $f0,$f2,$f4 + \op $f2,$f4,$f6[2] + \op $f6,$f4,15 + .if 0 /* Which is right?? */ + /* Test negative numbers in immediate-value slot. */ + \op $f4,$f6,-3 + .else + /* Test that it's recognized as an unsigned field. */ + \op $f4,$f6,31 + .endif + .endm + + nsel3 add.ob + nsel3 and.ob + nsel2 c.eq.ob + nsel2 c.le.ob + nsel2 c.lt.ob + nsel3 max.ob + nsel3 min.ob + nsel3 mul.ob + nsel2 mula.ob + nsel2 mull.ob + nsel2 muls.ob + nsel2 mulsl.ob + nsel3 nor.ob + nsel3 or.ob + nsel3 pickf.ob + nsel3 pickt.ob + nsel3 sub.ob + nsel3 xor.ob + + /* ALNI, SHFL: Vector only. */ + alni.ob $f0,$f2,$f4,5 + shfl.mixh.ob $f0,$f2,$f4 + shfl.mixl.ob $f0,$f2,$f4 + shfl.pach.ob $f0,$f2,$f4 + shfl.pacl.ob $f0,$f2,$f4 + + /* SLL,SRL: Scalar or immediate. */ + sll.ob $f2,$f4,$f6[3] + sll.ob $f4,$f6,14 + srl.ob $f2,$f4,$f6[3] + srl.ob $f4,$f6,14 + + /* RZU: Immediate, must be 0, 8, or 16. */ + rzu.ob $f2,13 + + /* No selector. */ + rach.ob $f2 + racl.ob $f2 + racm.ob $f2 + wach.ob $f2 + wacl.ob $f2,$f4 + + ror $4,$5,$6 + rol $4,$5,15 + dror $4,$5,$6 + drol $4,$5,31 + drol $4,$5,62 + + .set arch=vr5500 + + /* Prefetch instructions. */ + # We don't test pref because currently the disassembler will + # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, + # while pref is correct for mips4. Unfortunately, the + # disassembler does not know which architecture it is + # disassembling for. + # pref 4,0($4) + + prefx 4,$4($5) + + /* Miscellaneous instructions. */ + + wait + wait 0 # disassembles without code + wait 0x56789 + + ssnop + + clo $3,$4 + dclo $3,$4 + clz $3,$4 + dclz $3,$4 + + luxc1 $f0,$4($2) + suxc1 $f2,$4($2) + + tlbp + tlbr + +.set arch=default + +# make objdump print ... + .space 8 |