diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-add-addi.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-add-addi.s | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
5 files changed, 26 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index e722633..92869a3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-02-19 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/gas/riscv/c-add-addi.d: New testcase. + * testsuite/gas/riscv/c-add-addi.s: Likewise. + 2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com> PR 25576 diff --git a/gas/testsuite/gas/riscv/c-add-addi.d b/gas/testsuite/gas/riscv/c-add-addi.d new file mode 100644 index 0000000..14913df --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+0:[ ]+4605[ ]+li[ ]+a2,1 +[ ]+2:[ ]+852e[ ]+mv[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/c-add-addi.s b/gas/testsuite/gas/riscv/c-add-addi.s new file mode 100644 index 0000000..5274491 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-add-addi.s @@ -0,0 +1,3 @@ +.option rvc +addi a2, zero, 1 +add a0, zero, a1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0df7e50..e5aa59d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-02-19 Nelson Chu <nelson.chu@sifive.com> + + * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed + c.mv/c.li if rs1 is zero. + 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CpuABM with diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index cc46d16..ceedcaf 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -269,12 +269,14 @@ const struct riscv_opcode riscv_opcodes[] = {"addi", 0, INSN_CLASS_C, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, +{"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, /* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc applied to an add instruction, for relaxation to use. */ |